CMOS-BASED SEMICONDUCTOR DEVICE ON MICRO-HOTPLATE AND METHOD OF FABRICATION

Abstract

It is disclosed herein a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device is made using partly CMOS or CMOS based processing steps, and it includes a semiconductor substrate, a dielectric region over the semiconductor substrate, a heater within the dielectric region and a patterned layer of noble metal above the dielectric region. The method includes the deposition of a photoresist material over the dielectric region, and patterning the photo-resist material to form a patterned region over the dielectric region. The steps of depositing the photo-resist material and patterning the photo-resist material may be performed in sequence using similar photolithography and etching steps to those used in a CMOS process. The resulting semiconductor device is then subjected to further processing steps which ensure that a dielectric membrane and a metal structure within the membrane are formed in the patterned region over the dielectric region.

Claims

1. A method of manufacturing a microhotplate comprising a semiconductor substrate, a dielectric region over the semiconductor substrate, a resistive heater within the dielectric region, the method comprising: forming the semiconductor substrate, the dielectric region and the resistive heater using complementary metal oxide semiconductor, CMOS, compatible processing steps; depositing a photo-resist material over the dielectric region using the CMOS compatible processing steps; patterning the photo-resist material to form a patterned region over the dielectric region using the CMOS compatible processing steps; etching at least a portion of the semiconductor substrate to form a dielectric membrane, wherein the steps of depositing the photo-resist material, patterning the photo-resist material and etching the portion of the semiconductor substrate are performed in sequence; and subjecting the dielectric membrane to a further process which ensures that a metal structure is deposited in the patterned region over the dielectric region.

2. A method according to claim 1, wherein the steps of forming the semiconductor substrate, the dielectric region and the resistive heater, and the steps of depositing and patterning the photoresist material are performed within the CMOS processing steps.

3. A method according to claim 1, wherein the steps of forming the semiconductor substrate, the dielectric region and the resistive heater are performed within the CMOS processing steps, and the steps of depositing and patterning the photoresist material are performed separately from the CMOS processing steps using a processing tool which is usable in the CMOS processing steps.

4. A method according to claim 1, wherein said further process comprises at least one of depositing the metal structure by applying a sputtering or evaporation technique or depositing the metal structure both in the patterned region and on top of the photo-resist material.

5. (canceled)

6. A method according to claim 4, wherein said further process comprises removing the photo-resist material and the part of the metal structure on top of the photoresist material so that the metal structure formed in the patterned region is retained over the dielectric region, and optionally the photo-resist material and the part of the metal structure on top of the photo-resist material are removed using a chemical solution or a chemical solvent, and/or the photo-resist material and the part of the metal structure on top of the photo-resist material are removed using a lift-off technique.

7-8. (canceled)

9. A method according to claim 1, wherein the step of patterning the photo-resist material comprises at least one of applying a mask to define the patterned region over the dielectric layer or using a photolithography technique within the CMOS processing steps to define the patterned region over the dielectric region.

10. (canceled)

11. A method according to claim 1, wherein the step of etching the semiconductor substrate comprises applying a mask adjacent the semiconductor substrate to define the portion of the semiconductor substrate to be etched.

12. A method according to claim 1, wherein the step of etching the semiconductor substrate comprises one of: applying a Deep Reactive Ion Etching, DRIE, technique; or applying a wet etching technique, preferably using potassium hydroxide (KOH) or tetramethyl ammonium hydroxide (TMAH).

13. (canceled)

14. A method according to claim 1, wherein the resistive heater comprises a material selected from a group comprising tungsten, titanium, aluminum, polysilicon and single crystal silicon, and/or further comprising forming a first barrier layer adjacent the resistive heater within the dielectric region.

15. (canceled)

16. A method according to claim 1, wherein, after the etching of the substrate and prior to depositing the metal structures, the method further comprises depositing a second diffusion barrier layer on top of the photoresist region and in the patterned region over the dielectric region, optionally wherein the second diffusion barrier or adhesive layer comprises one or more material selected from a group comprising titanium, nickel and chromium.

17. (canceled)

18. A method according to claim 1, further comprising patterning the metal structure into one or more shapes selected from a group comprising: (1) interdigitated electrodes (2) electrodes arranged in shapes of concentric rings (3) spiral shaped electrodes, and (4) only two electrodes next to one another.

19. A method according to claim 1, further comprising at least one of: patterning the metal structure into a series of dots or holes; or depositing a gas sensitive layer on the metal structure, and optionally wherein the gas sensitive layer comprises a pure or doped metal oxide material selected from a group comprising tin oxide, tungsten oxide and zinc oxide.

20-22. (canceled)

23. A method according to claim 19, wherein the gas sensitive layer comprises a material selected from a group comprising polymers, nanowires, nanorods, nanoparticles and nano-plates.

24. A method according to claim 19, wherein the gas sensitive layer is a porous layer and/or a nanostructured layer.

25. A method according to claim 19, wherein the gas sensitive layer at least one of is deposited using a technique selected from a group comprising screen printing, sputtering, chemical vapour deposition (CVD) ink-jet and drop coating, or has a drop or conformal shape.

26. (canceled)

27. A method according to claim 1, wherein the microhotplate is formed from a bulk silicon wafer or a silicon-on-insulator (SOI) wafer.

28. A method according to claim 1, further comprising at least one of: forming a passivation layer on the dielectric region using the CMOS compatible processing steps, the metal structure being deposited on the passivation layer, wherein optionally the passivation layer comprises a material comprising silicon dioxide or silicon nitride; forming a temperature sensor within the dielectric region using the CMOS compatible processing steps, wherein optionally the temperature sensor is selected from a group comprising a diode temperature sensor, and a single crystal silicon, polysilicon or metal resistive temperature sensor; forming a heat spreading plate within the dielectric region using the CMOS compatible processing steps, and optionally the heat spreading plate comprises a material selected from a group comprising single crystal silicon, polysilicon and a metal; or integrating CMOS circuitry on the same chip as the microhotplate using the CMOS compatible processing steps, and optionally further comprising integrating a temperature sensor outside the dielectric membrane and within the same chip.

29-36. (canceled)

37. A method according to claim 1, wherein at least one of the microhotplate has a circular or rectangular shape, the dielectric membrane has a circular or rectangular shape, or the metal structure comprises gold or platinum.

38-39. (canceled)

40. A microhotplate comprising: a semiconductor substrate having an etched portion; a dielectric region over the semiconductor substrate; a resistive heater formed within the dielectric region; and a patterned metal layer formed over the dielectric region, wherein the semiconductor substrate, the dielectric region, the resistive heater, the etched portion in the substrate and the patterned metal layer are formed using the method according to any preceding claim.

41. A microhotplate comprising: a semiconductor substrate having an etched portion; a dielectric region over the semiconductor substrate; a resistive heater formed within the dielectric region; and a patterned metal layer formed over the dielectric region, wherein the semiconductor substrate, the dielectric region, the resistive heater are formed using a CMOS compatible technique, and wherein a pattern for the patterned metal layer is defined by the CMOS compatible technique, and wherein the etched portion in the substrate is formed using an etching technique and wherein the patterned metal layer is formed using a further technique.

42. A microhotplate according to claim 41, wherein the pattern is defined by the CMOS compatible technique to define geometrical features such as shape, area, width, length, diameter of the patterned metal layer and the distance/pitch between different features of the metal layer.

43. A microhotplate according to claim 41, wherein the further technique is a post CMOS compatible technique.

44. A microhotplate according to claim 42, wherein at least one of: the resistive heater comprises a material selected from a group comprising tungsten, titanium, aluminum, polysilicon and single crystal silicon; or the patterned metal layer comprises gold or platinum, and optionally further comprising a second diffusion barrier or adhesive layer present directly below the patterned metal layer, the second layer comprising one or more material selected from a group comprising titanium, nickel and chromium, wherein the second layer is processed by similar techniques with those used for the patterned metal layer.

45-46. (canceled)

47. A microhotplate according to claim 41, further comprising at least one of: a first barrier layer adjacent the resistive heater within the dielectric region; a passivation layer on top of the dielectric region; or a gas sensitive layer on top of the patterned metal layer, optionally wherein the gas sensitive layer has a drop or conformal shape.

48-51. (canceled)

52. An IR source incorporating the microhotplate according to claim 41, wherein said patterned metal layer is used to form plasmonic metal structures to enhance the IR emissivity for particular wavelengths and/or to reduce the IR emissivity for other particular wavelengths, optionally where said plasmonic metal structures comprise dots or holes.

53. (canceled)

54. A gas sensor incorporating the microhotplate according to claim 41.

Description

BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0053] Some preferred embodiments of the invention will now be described by way of example only and with reference to the accompanying drawings, in which:

[0054] FIG. 1 illustrates a schematic cross-section of a micro-hotplate made in a CMOS SOI process with post processed electrodes for resistive gas sensing;

[0055] FIG. 2 illustrates a schematic cross-section of an alternative micro-hotplate made in an SOI process with a post processed plasmonic structure for use as an IR emitter, where the plasmonic structure is used to enhance the emission;

[0056] FIG. 3 illustrates a schematic cross-section of an alternative micro-hotplate made in an SOI process for use as an IR emitter with to top metal deposited as a sheet during post-processing to increase the emissivity of the emitter;

[0057] FIG. 4 illustrates a schematic cross-section of an alternative micro-hotplate made in SOI process with post processed electrodes for resistive gas sensing. The heater has a further adhesion layer added to the heater material to improve the adhesion and reliability of the heater;

[0058] FIG. 5 illustrates a schematic cross-section of an alternative micro-hotplate made in a CMOS process with a starting bulk wafer with post processed electrodes for resistive gas sensing;

[0059] FIG. 6 illustrates a schematic cross-section of an alternative micro-hotplate made in a CMOS process with a starting bulk wafer with post processed electrodes for resistive gas sensing, where a layer is deposited just below the surface metal to improve the adhesion to the top surface, and/or reduce/prevent diffusion into the top surface;

[0060] FIG. 7 illustrates a schematic cross-section of an alternative micro-hotplate made in a CMOS process with post processed electrodes, where the back etching is done by KOH etching;

[0061] FIG. 8 shows the steps of the proposed method to deposit post processed Interdigitated electrodes (IDEs) on top of an SOI micro-hotplate;

[0062] FIG. 9 shows a top view of a square micro-hotplate with post processed IDEs;

[0063] FIG. 10 shows a top view of a circular micro-hotplate with post processed IDEs;

[0064] FIG. 11 shows a top view of some possible designs of electrodes for measuring the resistance of the sensing material on resistive gas sensors;

[0065] FIG. 12 shows a top view of an IR emitter with plasmonic structures deposited on it;

[0066] FIG. 13 shows the top view of a CMOS chip with micro-hotplates based gas sensors and interface circuitry on the same chip;

[0067] FIG. 14 illustrates a schematic cross-section of a micro-hotplate made in a CMOS SOI process with post processed electrodes for resistive gas sensing, and a chemical or gas sensing layer deposited as a drop layer; and

[0068] FIG. 15 illustrates a schematic cross-section of a micro-hotplate made in a CMOS SOI process with post processed electrodes for resistive gas sensing, and a chemical or gas sensing layer deposited as a conformal coating.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0069] Embodiments of the invention describe a method of manufacturing a CMOS based micro-hotplate fabricated with gold or platinum electrodes deposited over the device structure. In this method, the device is fabricated in a state-of-the-art CMOS process. The process could be either bulk CMOS or SOI CMOS. The heater can be made using tungsten, polysilicon, a MOSFET, aluminium or single crystal siliconall of these layers being CMOS compatible.

[0070] The micro-hotplate is then further processed by spinning and patterning a resist on the front side (near the resistive heater) of the wafer for the deposition of the gold electrodes, before the release of the membrane. The wafer is then back-etched using either dry etching through Deep Reactive Ion etching (DRIE) or wet etching using KOH. Gold or platinum is then sputtered on the front side to form the gold electrodes. Before one of these metal layers is deposited, it is possible that other layers of metals such as nickel, chromium or titanium are formed to improve adhesion and minimise diffusion into the dielectric layers or oxide layers. The process is completed when the lift-off is carried out to achieve the desired pattern (previously defined by the photolithography step in the CMOS)

[0071] Using this method, according to preferred embodiments, the lithography is performed on a wafer with standard thickness, without membranes, while at the same time, the metal deposition is done after the etching process, and so the etch equipment is not contaminated. Both Platinum and Gold are contaminants and so their use in CMOS or etch equipment is best avoided.

[0072] Preferably the back etch of the membrane is carried out using a Deep Reactive Ion Etch (DRIE). This results in vertical walls and hence reduced area consumption, and additionally good control of the final shape of the membrane, which in turn ensure high reproducibility across the wafer. Alternatively the membrane can be formed by wet etching using for example Potassium Hydroxide (KOH) or TetraMethyl Ammonium Hydroxide (TMAH). This results in a cheaper process.

[0073] In one embodiment, the device and the method described above are not limited to resistive gas sensors, but can be applied to other membrane based devices. According to a further embodiment, such a device and the method to produce it can be applied to CMOS based IR emitters.

[0074] FIG. 1 shows the schematic cross-section of a micro-hotplate made in an SOI process with post processed electrodes for resistive gas sensing. The device consists of a silicon substrate 1 and a membrane consisting of buried oxide 4, dielectric layers 5 and passivation 6 which is supported by the substrate. A resistive heater 2 is embedded within the membrane, and tracks 3 are used to connect the heater to the pads. On top of the passivation there are electrodes 7 formed of either gold or platinum which can be used to make contact to the sensing material. The etching is done by deep reactive ion etching (DRIE) to achieve near vertical sidewalls of the trench. The heater 2 is made within the CMOS sequence. The photolithography of the electrodes 7 is done as one of the last steps of the CMOS sequence and before the DRIE. The final pattern of the electrodes 7 is finalised by a lift-off technique (using the photolithography step done within the CMOS) after the DRIE. It will be appreciated that a standard silicon wafer can be used instead of the SOI wafer. In such a case, the silicon wafer would not have the buried oxide 4 used in the structure of FIG. 1.

[0075] FIG. 2 shows another embodiment of the invention where the device is an IR emitter and has plasmonic structures 8 made of either gold or platinum on the top surface to enhance the IR emission of the device. These structures, 8 are done in a similar manner with the electrodes 7 shown in FIG. 1.

[0076] FIG. 3 shows an IR emitter where the top metal layer of gold or platinum is used to form a coating 9 that enhances the IR emission of the device.

[0077] FIG. 4 shows a micro-hotplate with post processed electrodes for resistive gas sensing. In this device, the heater has an additional layer 10 below the metal layer to improve the adhesion and the stability of the heater. It would be apparent that the additional layer 10 can also be applied to the heater if it is used in an IR emitter device.

[0078] FIG. 5 shows a micro-hotplate with post processed electrodes for resistive gas sensing, fabricated using a process where the starting substrate was a bulk silicon substrate. In such a device, the buried oxide layer is not present.

[0079] FIG. 6 shows a micro-hotplate device, where the post processed electrodes have an additional layer 11 below them. This layer is to improve the adhesion of the metal (which can be gold or platinum) to the passivation. This layer maybe made from any material, or maybe a metal such as chromium, nickel or titanium, or can be more than one material layer.

[0080] FIG. 7 shows a micro-hotplate device with post processed electrodes, where the back etching has been perform by wet etching (for example using KOH or TMAH). This results in slanting sidewalls of the trench, as opposed to the vertical sidewalls created by DRIE.

[0081] FIG. 8 shows the main process involved in the deposition of the top metal layer structure of gold or tungsten. After the CMOS processing, the device is as shown in (a)

[0082] (a) It consists of a silicon substrate 1, a buried oxide layer 4, a heater 2 and tracks 3, dielectric oxide 5 and passivation 6. All these layers are formed within the CMOS sequence.

[0083] (b) Then a front side lithography mask 13 and a back side lithography mask 12 is spun and patterned on the front and back side of the wafer. This is one of the last steps of the CMOS sequence and defines the pattern of the future metal 7 that is done in step (d).

[0084] (c) The device is subsequently back etched using preferably a DRIE method.

[0085] (d) The top metal layer 7 (gold or platinum) is then deposited onto the device using sputtering or evaporation. If needed, one or more layers are deposited before the deposition of the final metal layer (gold or platinum) to improve the metal adhesion to the passivation surface and avoid diffusion into the oxide or passivation layers below.

[0086] (e) The photoresist done in step (b) is then removed together with unwanted parts of the top metal layer (gold or platinum).

[0087] It will be understood that the semiconductor structure of FIG. 1 (a) is manufactured using the standard CMOS process. One example of the detailed CMOS manufacturing steps is described as follows:

[0088] For the CMOS part of the process to form a simple metal heater (only steps relevant to the fabrication of a simple micro-hotplate are given): [0089] 1. The starting substrate is a silicon or an SOI wafer. [0090] 2. (only for the case of a starting SOI wafer) Patterning and defining the thin silicon layers, and having oxide in the rest. For the micro-hotplate area the design would typically replace the thin silicon with oxide. However, several other patterns are possible [0091] 3. A layer of dielectric 5 (silicon dioxide or silicon nitride) is deposited across the whole chip (micro-hotplate are and any circuitry). [0092] 4. A patterned metal layer is deposited. This forms the heater 2 within the micro-hotplate area. [0093] 5. Another layer of dielectric is deposited on top of the heater 2. [0094] 6. Another metal layer is deposited. This can optionally be used to form a plate or some other pattern above the heater. [0095] 7. Another layer of dielectric is deposited. [0096] 8. Another metal layer is deposited. This can optionally be used to form a plate or some other pattern above the heater. [0097] 9. A passivation layer 6 of silicon dioxide and/or silicon nitride is deposited.

[0098] It will be appreciated that this gives only one sequence of steps, and many other variations are possible and will be obvious to one well versed in the art. The CMOS process may contain other steps (such as p well and/or n well doping, polysilicon deposition, high p+ and n+ doping etc. to form a MOSFET)for a simple device these will not have an effect in the micro-hotplate region, but maybe used to fabricate circuitry on the same chip. The process may also have a different number of metal layers.

[0099] Additionally, by varying the use of different layers, the heater can be made of either single crystal silicon (p doped or n doped), or of polysilicon (p doped or n doped), or of one of the other metal layers. The metal layers may have one or more layers or a different material above or below it to improve adhesion and reliability. The device may also have a diode or a resistive temperature sensor made of single crystal silicon, polysilicon or a metal layer.

[0100] FIG. 9 shows the top view of a micro-hotplate with interdigitated electrodes for resistive gas sensing. It has a rectangular membrane 14, and the electrodes are interdigitated. FIG. 10 shows a similar structure, but one where the membrane, heater and electrodes are circular.

[0101] FIG. 11 shows some different shapes for electrodes used for resistive gas sensing. (a) shows a circular interdigitated shape. (b) shows interdigitated concentric rings. (c) shows electrodes in a spiral shape. Many other different shapes are possible. In particular, the electrodes can be rectangular in shape, or can be just 2 electrodes side by side. This figure shows only a few possible examples, and to one versed in the art many different shapes are possible.

[0102] FIG. 12 shows the top view of an IR emitter with plasmonic structures formed of gold or platinum to enhance the emission. The figure shows these structures to be rectangular, however they maybe circular, triangular or trapezoidal shaped, or indeed any shape depending on the required emission spectral profile.

[0103] FIG. 13 shows the top view of a chip 15 with a micro-hotplate device and circuitry 16 on the same chip. This is made possible by the use of CMOS processing, allowing both the sensor device and circuitry to be on the same chip. The use of a CMOS compatible post processing method allows the top metal layers of gold or platinum to be deposited on the membrane.

[0104] FIG. 14 shows the schematic cross-section of a micro-hotplate made in an SOI process with post processed electrodes for resistive gas sensing. The device has a chemical or gas sensing layer 17 deposited on the metal electrodes 7. The sensing material is like a drop on the metal electrodes.

[0105] FIG. 15 shows the schematic cross-section of a micro-hotplate made in an SOI process with post processed electrodes for resistive gas sensing. The device has a chemical or gas sensing layer 18 deposited on the metal electrodes 7. The sensing material is coated conformably over the electrodes.

[0106] It will be appreciated that the process/method of the present invention can also be used to manufacture arrays of microhotplates. It is possible that the arrays are made on different membranes or have more than one microhotplate on a single membrane. For example, the proposed method can make a membrane with 4 heaters and 4 electrodes spaced laterally, or 4 membranes with 1 heater and 1 electrodes each.

[0107] The skilled person will understand that in the preceding description and appended claims, positional terms such as above, below, front, back, vertical, underneath etc. are made with reference to conceptual illustrations of a semiconductor device, such as those showing standard cross-sectional perspectives and those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a semiconductor device when in an orientation as shown in the accompanying drawings.

[0108] Although the invention has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the invention, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.