METHOD OF FABRICATING A TRANSISTOR CHANNEL STRUCTURE WITH UNIAXIAL STRAIN

Abstract

Method for creation of stressed channel structure transistors wherein at least one amorphising ion implantation of the surface layer of a substrate of the semiconductor-on-insulator type is carried out through openings in a mask, so as to render zones of the surface layers amorphous and to induce relaxation of a zone intended to form a channel and located between the zones that have been rendered amorphous, the relaxation being carried out in a direction orthogonal to that in which it is intended that the channel current flows.

Claims

1. Method for creating stressed channel structure transistors comprising steps consisting of: forming a mask on a surface layer of a semiconductor-on-insulator type substrate comprising a support layer, an insulating layer separating the support layer from a surface layer, the surface layer being based on a semiconductor material stressed with a biaxial stress, the mask being formed from at least one block of elongated form arranged on a first zone of the surface layer, the first zone having a length measured parallel to a first direction and a width measured parallel to a second direction, the first zone being capable of forming a transistor channel structure wherein a current is meant to pass in the first direction, the mask being configured such that one or several openings of elongated form and which extend parallel to the first direction are arranged on either side of the masking block and respectively reveal the second zones of the surface layer arranged on either side of the first zone, execution of at least one ion implantation of the surface layer through the openings in the mask, so as to render the second zones amorphous and to induce relaxation of the first zone in the second direction, the method furthermore comprising a step consisting of transforming the second zones of the surface layer revealed by the openings of the mask into insulating zones.

2. Method according to claim 1 wherein the transformation of the second zones into insulating zones is achieved using at least one implantation step.

3. Method according to claim 2, wherein the amorphisation of the second zones and the transformation of the second zones into insulating zones are carried out concomitantly by implantation.

4. Method according to claim 2 wherein the transformation of the second zones into insulating zones comprises at least one thermal oxidation step.

5. Method according to claim 1, wherein at least one insulating zone formed by transformation of the second zones, forms a separation with another transistor.

6. Method according to claim 1 wherein, after transformation of the second zones that have been rendered amorphous into insulating zones, a thickness of these insulating zones is removed.

7. Method according to claim 1 furthermore comprising, after arnorphisation of the second zones of the surface layer, steps consisting of: removing the mask, then forming at least one transistor gate on the first semiconductor zone, the gate extending parallel to the second direction, then growth, on the semiconductor material of the surface layer, of source and drain blocks on either side of the gate.

8. Method according to claim 1, wherein the mask is a first mask, the method furthermore comprising, after formation of the first mask and prior to the arnorphisation of the second zones, the formation of a second mask resting on the first mask and arranged opposite given regions of the surface layer, the second mask comprising an opening revealing the first mask, then after amorphisation of the second zones, steps for removal of a portion of the first mask through the opening of the second mask, formation of a gate in the opening of the second mask, removal of the second mask and of remaining portions of the first mask, then, formation of source and drain blocks on either side of the gate.

9. Method according to claim 1 wherein, prior to the formation of the mask, the following steps are carried out: formation of a sacrificial gate on the surface layer, then, formation of source and drain blocks on either side of the sacrificial gate, removal of the sacrificial gate so as to leave room for an opening between the source and drain blocks, then, after formation of the mask in the opening and amorphisation of the second zones of the surface layer, a gate is formed in the opening between the source and drain blocks.

10. Method according to claim 1, wherein the mask has an intrinsic stress.

Description

BRIEF DESCRIPTION OF THE ILLUSTRATIONS

[0042] The present invention will be better understood on reading the description of example embodiments given, purely as an indication and in no sense restrictively, making reference to the appended illustrations in which:

[0043] FIGS. 1A-1G show an example of a method according to one embodiment of the invention, wherein a stressed channel structure is relaxed in a direction orthogonal to that in which the channel current is intended to flow;

[0044] FIG. 2 shows an implantation step for the simultaneous implementation of a transformation of amorphous semiconductor zones into insulating zones and the relaxation of stress in a semiconductor zone located between these insulating zones in a direction orthogonal to that along which this semiconductor zone extends;

[0045] FIG. 3 shows an embodiment example wherein the semiconductor zones transformed into insulating zones serve to define one or more insulating outlines which separate and mark the extent of the active transistor zones;

[0046] FIG. 4 shows an example of a possible starting substrate for a method according to the invention;

[0047] FIGS. 5A-5G show an embodiment example of the gate first type wherein the relaxation of the channel structure in a direction orthogonal to that in which the current is intended to flow is carried out in a localised region in which a transistor gate is envisaged;

[0048] FIGS. 6A-6D show an embodiment example of a gate last type used to implement the relaxation of a semiconductor zone located between source and drain blocks;

[0049] FIG. 7 shows an example of a method wherein a thickness is removed from the surface layer zones of a substrate transformed into insulating zones;

[0050] FIG. 8 shows an example of a method wherein a gate is formed on the lateral flanks of a channel structure;

[0051] FIGS. 9A and 9B give example of chains of steps for methods for manufacturing stressed channel transistor devices with a uniaxial stress;

[0052] Identical, similar or equivalent portions of the various figures have the same numerical references, to make it easier to go from one figure to another.

[0053] In order to make the figures more readable, the various parts shown in the figures are not necessarily shown at a uniform scale.

[0054] Furthermore, in the description hereafter, terms which depend on the orientation, such as under, on, surface, lateral etc. for a structure are applied assuming that the structure is oriented in the manner shown in the figures.

DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS

[0055] One example of a method for producing a stressed channel structure transistor will now be described in relation to FIGS. 1A-1G.

[0056] The starting material in this method may be a stressed semiconductor-on-insulator type substrate, and thus may comprise a semiconductor support layer 10, an insulating layer 11 located on and in contact with the support layer 10, as well as a so-called surface semiconductor layer 12 which comprises an intrinsic stress, and which is located on and in contact with the insulating layer 11.

[0057] An example of a stressed silicon on insulator type substrate is the sSOI (strained silicon on insulator) substrate wherein the surface semiconductor layer 12 is based on Si that is stressed in particular under tension with a biaxial stress (FIG. 1A),

[0058] The transistor created may use, for example, FDSOI (Fully Depleted Silicon on Insulator) technology. In this case the surface semiconductor layer 12 has a thickness e.sub.1 which may be for example between 3 and 20 nm, whereas the insulating layer 11 commonly called BOX (Buried Oxide) and which is SiO.sub.2 based may have a thickness e.sub.2 for example between 5 nm and 145 nm (the thicknesses e.sub.1 and e.sub.2 being dimensions measured parallel to the z axis of an orthogonal reference [O; x; y; z] shown in FIG. 1A).

[0059] A mask 20 is then formed on the stressed surface layer 12. The mask 20 may be a hard mask, for example SiN or SiO.sub.2 based.

[0060] In the embodiment example shown in FIG. 1B, the mask 20 is formed of several blocks 22 arranged respectively on the first zones 12a of the surface layer 12. The mask blocks 22 have an oblong or elongated shape, advantageously a parallelepiped shape. The term elongated means that they have a width (measured parallel to the x axis of the reference [O; x; y; z]) less than and in particular 3 times smaller than their length (itself measured parallel to the y axis of the reference [O; x; y; z]). The mask blocks 22 may be envisaged with a width for example of between 5 nm and 50 nm and a length for example of between 100 nm and 10 m.

[0061] The mask comprises openings 23 revealing, respectively, the second zones 12b of the surface layer 12, The openings 23 also have an oblong or elongated shape, for example a rectangular shape, and extend on either side of the blocks 22 of the mask 20, alongside the latter.

[0062] The first zones 12a of the surface layer located respectively opposite the mask blocks thus have an elongated shape. Then amorphisation is performed on the second zones 12b of the surface layer 12 revealed by the openings 23 of the mask 20. This amorphisation is performed using one of more ion implantations, the blocks 22 of the mask 20 protecting the first zones 12a of the surface layer on which they rest. The implanted species may be for example Si or Ge or As.

[0063] The amorphising implantation may be executed for example based on atoms of Ge, or of Si, or of As, or of C, or, of Ar, or of P, or of N, at an energy chosen according to the nature of the implanted species, the nature and thickness of the surface layer, of the implantation current density and of the temperature of the substrate during implantation. In order to render amorphous a layer of 10 nm to 30 nm of Si or of SiGe, an implantation of Si or of Ge can be carried out using an energy of between 6 keV and 40 keV and using a dose between 5e14 and 1e15 atoms/cm.sup.2.

[0064] For example, in order to render amorphous a thickness of 15 nm of Si, Si ions can be implanted at an energy of between 6 keV and 8 keV with a dose of the order of 110.sup.15 atoms/cm.sup.2. In order to render amorphous a thickness of 30 nm of Si, Si ions can be implanted for example at an energy of between 14 keV and 25 keV with a dose of the order of 510.sup.14 atoms cm.sup.2.

[0065] Thus, the second zones 12b of the surface layer 12, which extends against the first zones 12a of the non-implanted surface layer and whose crystalline structure is preserved, are rendered amorphous. The amorphisation of the second zones 12b leads to a relaxation of the stress in the second zones 12b in a direction which is orthogonal to that in which the first zones and the second zones extend, this direction also being parallel to the principal plane of the surface layer 12. The term principal plane of the surface layer 12 here means a plane passing through the surface layer 12 and which is parallel to a plane [O; x ; y] of the orthogonal reference [O; x; y; z].

[0066] Due to the shape of the first zones 12a and to their arrangement in relation to the second zones 12b which are joined adjacent to them, the amorphisation also induces a relaxation of the stress in the first zones 12a in the direction in which the first zones 12a extend.

[0067] In the example in FIG. 1C, the direction in which the relaxation occurs is parallel to the direction in which the width W.sub.1 of the first semiconductor zones 12a is measured. In other words, relaxation in a direction parallel to the x axis of the orthogonal reference [O; x; y; x] is performed.

[0068] A stress is however preserved in the first zones 12a in another direction which corresponds to the direction in which the first zones 12a extend, that is, in a direction taken parallel to the length L.sub.1 of the first semiconductor zones 12a. In other words, a stress is preserved in a direction taken parallel to the y axis of the orthogonal reference [O; x; y];

[0069] The relaxation may thus be realised without etching of the surface layer, in other words, without creating a relief. This may facilitate the creation of a transistor gate later. For a given thickness e.sub.1 of the surface layer 10, L.sub.1 is preferably envisaged as being greater than 10e.sub.1, and W.sub.1 preferably less than 5e.sub.1.

[0070] These first zones 12a are meant to form a transistor channel structure. A current is meant to pass in this channel parallel to the first direction, in other words, parallel to the y axis in FIG. 1C. By implementing a relaxation in the second direction, that is, a direction orthogonal to that in which it is intended to pass a current, the performance of the channel structure in terms of carrier mobility is improved.

[0071] In order to allow the first zones 12a to further relax in the second direction, the mask 20 itself may be based on a material which has an intrinsic stress which is opposite to that of the surface layer 12. For example, in order to allow the first zones 12a based on Si and stressed under tension to relax, a compressive mask, for example SIN based, may be used. In another case, for example, where the first zones 12a are compression stressed SiGe based, a mask based on tension stressed SiN may be used.

[0072] The second semiconductor zones 12b can then be transformed into insulating zones 15 (FIG. 1D). The transformation of the second semiconductor zones 12b which have been rendered amorphous, into insulating zones on either side of a first semiconductor zone 12a allows the implementation of a lateral insulation of this first semiconductor zone.

[0073] Preferably, this transformation is achieved by using the mask 20, which acts as protection of the first semiconductor zones 12a. Thus, using the same mask, a uniaxial stress can be created in the surface layer 12 and insulating zones 15 can be formed in this same surface layer 12.

[0074] The transformation of the second zones 12b into insulating zones 15 can be achieved for example using one of more implantations, once more using the mask 20 as an implementation mask.

[0075] For example, oxygen may be implanted in order to transform the second semiconductor zones 12b into semiconductor oxide zones, in particular silicon oxide.

[0076] Alternatively, nitrogen could be implanted in order to transform the second semiconductor zones 12b into nitride zones, in particular silicon nitride zones. Another alternative embodiment envisages an implantation of oxygen and of nitrogen. The implantation method used may be of the Plasma Immersion Ion Implantation (Pill) type, followed if necessary by high-temperature short-duration annealing. The implantation may be carried out at a temperature between for example 200 C. and 500 C., Subsequent to the implantation, thermal annealing may be carried out in order to improve the quality of the dielectric material obtained.

[0077] Such annealing may be carried out for example at a high temperature between 300 C. and 1100 C. and preferably for a short duration, for example between several minutes at low temperature and several s at high temperature.

[0078] Thermal annealing may also be envisaged in order to remove any defects created during the implantation in the insulating layer 11 and/or at an interface between dielectric material and semiconductor material.

[0079] Another method for transformation of the second semiconductor zones 12b into zones of dielectric material 15 may comprise oxidation of the second zones 12b in order to create a semiconductor oxide in the second zones 12b, In this case the mask 20 is envisaged so as to create an oxidation mask which protects the first semiconductor zones 12a. The oxidation may be achieved for example using plasma or by thermal oxidation. Nitriding using plasma may also be carried out.

[0080] A removal of the mask 20 is then carried out (FIG. 1E).

[0081] In the case of the mask 20 being based on dielectric materials, this material is preferably different from that of the insulating zones 15, and envisaged in particular so as to allow selective removal of this mask 20 without altering the insulating zones 15. In one case, for example, where the insulating zones 15 of the surface layer are silicon oxide based, the mask 20 may have been envisaged for example as being silicon nitride based. In another case, for example, where the insulating zones 15 are silicon nitride based, the mask 20 may have been envisaged as being silicon oxide based,

[0082] After having removed the mask 20, planarisation may then be carried out, for example by CMP polishing.

[0083] Then a gate 30 for the transistor is formed. In order to do this a gate stack is deposited comprising a dielectric and agate material, which is then etched in order to form a gate pattern. The gate 30 created is arranged on the first zones 12a and extends orthogonally to the first semiconductor zones 12a taken in the direction of their length Thus in the example shown in FIG. 1E, the gate 30 extends in a direction parallel to the x axis of the orthogonal reference [O; x; y; z].

[0084] Insulating spacers 31 are then formed on either side of the gate (FIG. 1F).

[0085] Source and drain blocks 41, 42 are then made either side of the gate, by carrying out epitaxial growth on regions of the first semiconductor zones 12a.

[0086] The material of the source and drain blocks may be envisaged so as to optimise the uniaxial stress preserved in the first semiconductor zones 12a. In the case where the transistor made is of the PMOS type, the source and drain regions 41, 42 may for example be SiGe based. In another case for example where the transistor made is of the NMOS type, the source and drain blocks 41, 42 may for example be carbon doped Si (Si:C) based.

[0087] An alternative of the previously described example method is shown in FIG. 2 and advantageously envisages the concomitant execution of arnorphisation of the second zones 12b leading to the relaxation of the first zones 12a, and the transformation of the second zones into dielectric zones, using at least one common implantation step. This implantation of the second zones 12b may be carried out using for example N or O. The energy and the dose are altered depending on the materials and the thickness of the target. In particular plasma immersion implantation Pill may be carried out, a technique which allows implantation at high doses to be carried out over a reasonable time. For example PHI implantation of oxygen using an energy of the order of 1 keV and a dose of the order of 1.sup.e17 atoms/cm.sup.2 can be used to transform a layer of Si with a thickness e.sub.1 less than 8 nm into oxide.

[0088] According to another example, Pill implantation of oxygen using a dose of the order of 1.sup.e17 atoms/cm.sup.2 at an energy of 2.44 keV can be used to transform a layer of Si with a thickness e1<15 nm into oxide.

[0089] According to another example, in order to carry out nitriding of a layer of Si of less than 10 nm, nitrogen implantation at a dose between 6.10.sup.16 and 1*10.sup.17 cm.sup.2 and at a voltage of 2400 V allows a layer of nitride to be formed.

[0090] These implantations are preferably followed by high temperature annealing, for example annealing of the type commonly called spike annealing of very short duration at 950 C.

[0091] According to one implementation possibility for one or other of the method examples previously described, during the steps described in relation to the FIGS. 1C-1D or FIG. 2, some zones 112b of the surface layer 12 which are rendered amorphous and then transformed into insulated zones may be intended to form an insulating separation outline between active zones Z1, Z2, Z3, Z4 or transistor zones of the surface layer 12 (FIG. 3). Thus, whilst relaxing the first zones 12a of the surface layer, Shallow Trench isolation (STI) is achieved.

[0092] Another alternative of one or other of the previously described method examples envisages beginning with a stressed semiconductor-on-insulator substrate, this time of the sSiGeOI (strained silicon germanium on insulator) type. Such a substrate thus possesses a surface semiconductor layer 212 based on biaxial compression stressed SiGe (FIG. 3).

[0093] In this case the amorphisation of the second semiconductor zones 12b of the surface layer 212 is used to relax the compressive stress in a direction that is orthogonal to the direction of elongation of the first semiconductor zones whose crystalline structure has been preserved, whilst preserving a compressive stress in the direction of elongation of the first semiconductor zones 12a.

[0094] An example of a method for forming a layer of stressed SiGe on insulator may comprise the deposition of a layer of SiGe or of a stack of a thin layer of Si and of a layer of SiGe on the surface layer of stressed Si of a sSOI substrate, then carrying out oxidation so as to enrich the stressed surface layer of Si with Germanium. The oxide is then removed.

[0095] A method for relaxation of biaxial stress by arnorphisation as described previously can be carried out on a substrate comprising a region appropriate for the implementation of N-type transistors and which comprises a biaxial stress under tension and another region appropriate for the implementation of P type transistors and comprising a compression biaxial stress.

[0096] Such a substrate may for example be a sSOI substrate which has a surface layer based on tension stressed Si, a region of which is transformed into cSiGe by a Germanium enrichment method as referred to previously.

[0097] For example the relaxation by arnorphisation method described previously in relation to FIG. 1C in a region of the surface layer 12 reserved for N type transistors may be carried out whilst totally masking another region of the surface layer 12 reserved for P type transistors.

[0098] Then, after having removed the mask this other region is transformed into a cSiGe region by Germanium enrichment.

[0099] According to another alternative, a method as previously described in relation to FIG. 1C in which zones of the stressed surface layer of a semiconductor on insulator substrate is rendered amorphous may also be carried out only in a localised region of the surface layer 12 on which it is intended to make the gate. This avoids modifying the regions of the surface layer in which and/or on which it is intended to form the source and drain blocks. Such an alternative is shown in FIGS. 5A-5G.

[0100] After having formed a first mask 20 (the creation of which has been previously described in relation to the FIG. 1B and which is shown in FIG. 5A as a top view), a second masking 120 is carried out. The second mask 120 may be based on the same material as that of the first mask 20, for example of SIN or of SiO.sub.2.

[0101] This second mask 120 comprises blocks 122 arranged opposite the respective locations of a source region and of a drain region of the transistor which are to be made. An opening 123 made between the blocks 122 of the second mask defines a location for the transistor gate that it is intended to form later. This opening 123 thus reveals the blocks 22 of the first mask 20 and the openings 23 envisaged on either side of the blocks 22 of the first mask 23 (FIG. 5B).

[0102] Then at least one ion implementation is carried out so as to render amorphous the second zones 12b of the surface layer 12 which are revealed by the openings 23 of the first mask 20, themselves revealed by the opening 123 of the second mask 120.

[0103] After having thus relaxed the stress in the first zones 12a in a direction orthogonal to that in which they extend, the second zones 12b which are rendered amorphous can be transformed into insulating zones. In order to do this, for example, implantation is carried out through the openings 23 and 123 of the first mask 20 and of the second mask 120 (FIG. 5C).

[0104] Then a portion of the first mask 20 located at the bottom of the opening 123 is then removed. Thus the first zones 12a of the surface layer 12 under uniaxial stress and the second zones 12b of the surface layer 12 transformed into insulating zones are revealed (FIG. 5D).

[0105] In the case of the masks 20 and 120 being based on the same material, then in order to allow the removal of a portion of the first mask 20 whilst preserving sufficient of the second mask 120, the latter could be envisaged with a thickness greater than that of the blocks of the first mask 20.

[0106] Then, a gate 30 is formed in the opening 123 of the second mask 120 (FIG. 5E).

[0107] The second mask 120 is then removed so as to reveal the regions 13a, 13b of the surface layer 12 in which and/or on which it is intended to form the source and drain blocks (FIG. 5F).

[0108] Then, insulating spacers 31 are formed against the lateral flanks of the gate 30. Source and drain blocks are then formed by epitaxy (FIG. 5G),

[0109] With the embodiment example that has just been given, the creation of the source and drain blocks is easier that that described in FIGS. 1A-1G. In effect, it is only done on the regions 13a, 13b of the semiconductor material.

[0110] In the examples of methods that have just been described, the gate is made before the source and drain blocks are formed. As an alternative to these methods of a type which may be called gate first, source and drain blocks can be made by using a sacrificial gate then replacing this sacrificial gate having beforehand transformed the biaxial stress into a uniaxial stress in the first zones 12a of the surface layer 12.

[0111] One such method alternative, of a type that may be called gate last is shown in FIGS. 6A-6D.

[0112] In this example a sacrificial gate 230 is formed on the biaxial stressed surface layer 12 and insulating spacers 31 are formed against the flanks of the sacrificial gate 230. The sacrificial gate may be for example polysilicon based.

[0113] Then source and drain blocks 41, 42 are made on either side of the sacrificial gate 230 (FIG. 6A).

[0114] The sacrificial gate 230 is then removed. The location of the sacrificial gate left vacant forms an opening 233 which reveals the surface layer 12 of the substrate (FIG. 6B),

[0115] In this opening 233 the mask 20 is then formed as described previously in relation to FIG. 1B, and comprises parallel blocks 22 arranged respectively on the first zones 12a of the surface layer 12 with parallel openings envisaged between the blocks 22 of the mask 20 and revealing second zones 12b of the surface layer 12.

[0116] Through the opening 233 between the source and drain blocks and the openings 23 of the mask 20, amorphisation of the second zones 12b is thus carried out so as to transform the biaxial stress into uniaxial stress in the first zones 12a. The second semiconductor zones 12b are also transformed into insulating zones 15 (FIG. 6D).

[0117] Then a replacement gate 30 is formed in the opening 233 (FIG. 6D).

[0118] A method that allows the stress in the first semiconductor zones 12a to be increased and more particularly in a direction parallel to their length L.sub.1 is shown in FIG. 7. In order to do this, a given thickness of the second zones 12b of the surface layer 12 is removed after these zones 12b have been transformed into zones 12b of dielectric material 15. Thus a portion of the lateral flanks 201 of the first semiconductor zones 12a is revealed.

[0119] The thickness removed may be for example between 2 nm and 15 nm.

[0120] A gate 30 can then be formed whose shape matches the shape of the first semiconductor zones 12a, This gate is thus arranged against a portion of the lateral flanks 201 of the first semiconductor zones 12a. Such a gate arrangement shown in FIG. 8 allows improved control of the channel. The gate 30 may be made as in the method example described previously in relation to FIGS. 6A-6D. Thus, the gate 30 can be formed as a replacement of a sacrificial gate and implemented using an inlay method wherein an opening in a mask is filled in.

[0121] A particular example of a chain of steps for manufacturing a microelectronic transistor device which includes an amorphisation step for transforming a biaxial stress into a uniaxial stress is given in FIG. 9A.

[0122] The method is, in this example, of the gate first type.

[0123] First of all step S1) zones reserved for WET and PFET transistors are defined in the surface layer of the biaxial stressed substrate.

[0124] Then (step S21) the transformation of the biaxial stress into uniaxial stress is carried out as described previously, by arnorphisation of zones of the surface layer.

[0125] Amorphous zones are transformed into dielectric zones, which allow STI isolation zones to be formed (step S22, where this step S22 and S21 can be combined and carried out as a single step S2).

[0126] Then a gate is formed (step S3), then spacers (step S4). Then source and drain regions are made (step S5), and annealing is carried out(step 56).

[0127] Then a silicidation and contact creation step (step S7) is carried out.

[0128] Then a first metal interconnection level can be formed (step S8).

[0129] Another particular example of a chain of steps for manufacturing a microelectronic transistor device which includes an amorphisation step for transforming a biaxial stress into a uniaxial stress is given in FIG. 9B.

[0130] The method in this other example is of the gate last type. First of all (step S1) zones reserved for NFET and PFET transistors are defined in the surface layer of the biaxial stressed substrate. Then (step S21) STI insulation zones are formed. Then a dummy gate (step S3) is formed, then spacers (step S4). Then source and drain regions are made (step S5), and annealing (step S6).

[0131] Then a step for encapsulation of source and drain regions and CMP polishing are carried out (step S7).

[0132] The dummy gate is then removed (step S8). Then the transformation of the biaxial stress into uniaxial stress is carried out by amorphisation of zones of the surface layer (step S9).

[0133] Then the replacement gate is formed (step S10), then self-aligned contacts(step S11). Then a first metal interconnection level can be formed (step S12).

[0134] A method according to one or other of the method examples described above can be adapted to the creation of channel structure transistors which are not necessarily planar. For example, transistors of the uniaxial stressed channel finFET type may be made.