3D chip package based on through-silicon-via interconnection elevator

Abstract

A chip package includes a first interconnection scheme; a plurality of first metal contacts under and on the first interconnection scheme and at a bottom surface of the chip package; a first semiconductor IC chip over the first interconnection scheme; a first connector over the first interconnection scheme and at a same horizontal level as the first semiconductor IC chip, wherein the first connector comprises a first substrate and a plurality of first through vias vertically extending through the first substrate of the first connector; a first polymer layer over the first interconnection scheme, wherein the first polymer layer has a top surface coplanar with a top surface of the first semiconductor IC chip, a top surface of the first substrate of the first connector and a top surface of each of the plurality of first through vias; and a second interconnection scheme on the top surface of the first polymer layer, the top surface of the first semiconductor IC chip, the top surface of the first connector and the top surface of each of the plurality of first through vias, wherein the second interconnection scheme comprises a plurality of second metal contacts at a top surface of the chip package.

Claims

1. A chip package comprising: a first interconnection scheme comprising a first interconnection metal layer, a second interconnection metal layer over the first interconnection metal layer and a first insulating dielectric layer between the first and second interconnection metal layers, wherein the first interconnection metal layer couples to the second interconnection metal layer through an opening in the first insulating dielectric layer; a plurality of first metal contacts under and on the first interconnection scheme and at a bottom surface of the chip package; a first semiconductor integrated-circuit (IC) chip over the first interconnection scheme, wherein the first semiconductor integrated-circuit (IC) chip couples to the second interconnection metal layer; a first connector over the first interconnection scheme and at a same horizontal level as the first semiconductor integrated-circuit (IC) chip, wherein the first connector couples to the first semiconductor integrated-circuit (IC) chip through the second interconnection metal layer, wherein the first connector comprises a first silicon substrate, a second insulating dielectric layer on a bottom surface of the first silicon substrate, a plurality of first through silicon vias each extending, in a vertical direction, in the first silicon substrate of the first connector, and a plurality of second metal contacts at a bottom of the first connector, wherein each of the plurality of second metal contacts is in contact with and couples to a bottom surface of one of the plurality of first through silicon vias, wherein each of the plurality of second metal contacts comprises a first adhesion layer on and in contact with the bottom surface of one of the plurality of first through silicon vias and under the second insulating dielectric layer, a first copper layer on a bottom surface of the first adhesion layer and a second copper layer on a bottom surface of the first copper layer, wherein the first silicon substrate has left and right sidewalls in the vertical direction, wherein the left sidewall of the first silicon substrate is opposite to the right sidewall of the first silicon substrate, wherein the plurality of first through silicon vias are between the left and right sidewalls of the first silicon substrate; a polymer layer on and over the first interconnection scheme, wherein the polymer layer has a portion between the first semiconductor integrated-circuit (IC) chip and first connector; and a second interconnection scheme over a top surface of the polymer layer, a top surface of the first semiconductor integrated-circuit (IC) chip, a top surface of the first silicon substrate of the first connector and a top surface of each of the plurality of first through silicon vias, wherein the second interconnection scheme comprises a third interconnection metal layer over the top surface of the first silicon substrate of the first connector and on the top surface of each of the plurality of first through silicon vias, wherein the third interconnection metal layer couples to the first semiconductor integrated-circuit (IC) chip through, in sequence, a first through silicon via of the plurality of first through silicon vias, a second metal contact of the plurality of second metal contacts and the second interconnection metal layer, wherein the second interconnection scheme comprises a plurality of third metal contacts at a top surface of the chip package.

2. The chip package of claim 1, wherein the plurality of first metal contacts comprise more than twenty first metal contacts under and on the first interconnection scheme and at the bottom surface of the chip package, wherein the plurality of third metal contacts comprise more than twenty third metal contacts at the top surface of the chip package, wherein each of the more than twenty third metal contacts is vertically aligned with one of the more than twenty first metal contacts.

3. The chip package of claim 2, wherein the more than twenty first metal contacts are vertically under the first semiconductor integrated-circuit (IC) chip and the more than twenty third metal contacts are vertically over the first semiconductor integrated-circuit (IC) chip.

4. The chip package of claim 1, wherein the plurality of first metal contacts comprises a first metal contact vertically under the first semiconductor integrated-circuit (IC) chip, and the plurality of third metal contacts comprises a third metal contact vertically over the first semiconductor integrated-circuit (IC) chip, wherein the first metal contact couples to the third metal contact through a second through silicon via of the plurality of first through silicon vias.

5. The chip package of claim 1, wherein the plurality of first metal contacts comprise more than fifty first metal contacts under and on the first interconnection scheme and at the bottom surface of the chip package, wherein the plurality of third metal contacts comprise more than fifty second metal contacts at the top surface of the chip package, wherein each of the more than fifty third metal contacts is vertically aligned with one of the more than fifty first metal contacts.

6. The chip package of claim 1, wherein the first connector has no transistor therein.

7. The chip package of claim 1, wherein the first semiconductor integrated-circuit (IC) chip comprises a fourth metal contact at a bottom of the first semiconductor integrated-circuit (IC) chip and coupling to the first interconnection scheme.

8. The chip package of claim 1, wherein the second copper layer has a thickness between 1 and 60 micrometers.

9. The chip package of claim 1 further comprising a second semiconductor integrated-circuit (IC) chip over the first interconnection scheme, under the second interconnection scheme and at a same horizontal level as the first semiconductor integrated-circuit (IC) chip and first connector, wherein the third interconnection metal layer couples to the second semiconductor integrated-circuit (IC) chip through, in sequence, a second through silicon via of the plurality of first through silicon vias and the second interconnection metal layer, and wherein the second semiconductor integrated-circuit (IC) chip couples to the first semiconductor integrated-circuit (IC) chip through the second interconnection metal layer.

10. The chip package of claim 9, wherein the first semiconductor integrated-circuit (IC) chip is a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the second semiconductor integrated-circuit (IC) chip is a memory chip.

11. The chip package of claim 9, wherein the first semiconductor integrated-circuit (IC) chip comprises a first input/output (I/O) circuit coupling to a second input/output (I/O) circuit of the second semiconductor integrated-circuit (IC) chip, wherein each of the first and second input/output (I/O) circuits has an I/O power efficiency smaller than 0.5 pico-Joules per bit.

12. The chip package of claim 1 further comprising a second connector over the first interconnection scheme, under the second interconnection scheme and at a same horizontal level as the first semiconductor integrated-circuit (IC) chip and first connector, wherein the second connector couples to the first semiconductor integrated-circuit (IC) chip through the second interconnection metal layer, wherein the second connector comprises a second silicon substrate and a plurality of second through silicon vias vertically in the second silicon substrate of the second connector, wherein the third interconnection metal layer couples to the first semiconductor integrated-circuit (IC) chip through, in sequence, a second through silicon via of the plurality of second through silicon vias and the second interconnection metal layer.

13. The chip package of claim 1, wherein the first through silicon via is used to deliver a voltage of power supply (Vcc) to the first semiconductor integrated-circuit (IC) chip.

14. The chip package of claim 1, wherein the first through silicon via is used to deliver a voltage of ground reference (Vss) to the first semiconductor integrated-circuit (IC) chip.

15. The chip package of claim 1, wherein the first semiconductor integrated-circuit (IC) chip is a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.

16. The chip package of claim 1, wherein the top surface of the polymer layer is substantially coplanar with the top surface of the first semiconductor integrated-circuit (IC) chip and the top surface of the first silicon substrate of the first connector, and wherein each of the plurality of first through silicon vias has a top surface at a top of the first connector.

17. The chip package of claim 1, wherein the first semiconductor integrated-circuit (IC) chip comprises an input/output (I/O) circuit coupling to the first interconnection scheme, wherein the input/output (I/O) circuit has a driving capability between 0.05 pF and 2 pF.

18. The chip package of claim 1, wherein the third interconnection metal layer is further over the top surface of the polymer layer and the top surface of the first semiconductor integrated-circuit (IC) chip.

19. The chip package of claim 1, wherein the plurality of second metal contacts are horizontally arranged in a plurality of regions of arrays of second metal contacts, wherein the plurality of second metal contacts in each region of the plurality of regions of arrays of second metal contacts are arranged in a plurality of columns and a plurality of rows, wherein the first connector comprises a reserved scribe line between neighboring two regions of the plurality of regions of arrays of second metal contacts, wherein a first horizontal space between neighboring two of the plurality of second metal contacts and across the reserved scribe line is greater than a second horizontal space between neighboring two of the plurality of second metal contacts within a region of the plurality regions of arrays of second metal contacts.

20. The chip package of claim 19, wherein the first horizontal space is greater than 40 micrometers and the second horizontal space is smaller than 30 micrometers.

21. The chip package of claim 1, wherein each of the plurality of first through silicon vias comprises a third copper layer vertically in the first silicon substrate and a second adhesion layer at a sidewall of the third copper layer thereof and between the third copper layer thereof and first silicon substrate.

22. The chip package of claim 1, wherein the first connector further comprises an insulating-material layer under and on the second insulating dielectric layer, wherein an opening in the insulating-material layer is under and vertically aligned with the bottom surface of the first through silicon via, wherein the second metal contact is under and on a bottom surface of the insulating-material layer, extends into the opening in the insulating-material layer and couples to the bottom surface of the first through silicon via through the opening in the insulating-material layer.

23. The chip package of claim 22, wherein the second copper layer of the second metal contact has a first portion in the opening in the insulating-material layer and a second portion under the first portion of the second copper layer and the bottom surface of the insulating-material layer, and the first adhesion layer of the second metal contact has a first portion between the bottom surface of the first through silicon via and a top of the first portion of the second copper layer of the second metal contact, a second portion between a sidewall of the opening in the insulating-material layer and a sidewall of the first portion of the second copper layer of the second metal contact and a third portion between the bottom surface of the insulating-material layer and a top of the second portion of the second copper layer of the second metal contact, wherein the first and second portions of the second copper layer of the second metal contact are integral and the first, second and third portions of the first adhesion layer of the second metal contact are integral.

24. The chip package of claim 22, wherein the insulating-material layer comprises a polymer.

25. The chip package of claim 1, wherein each of the plurality of first metal contacts is a metal bump and each of the plurality of third metal contacts is a metal pad.

26. The chip package of claim 1, wherein the first connector further comprises a third insulating dielectric layer at a sidewall of each of the plurality of first through silicon vias and between said each of the plurality of first through silicon vias and the first silicon substrate.

27. The chip package of claim 1, wherein each of the plurality of first through silicon vias extends into an opening in the second insulating dielectric layer.

28. The chip package of claim 1 further comprising a tin-containing layer under the second copper layer of the second metal contact, between the second copper layer of the second metal contact and the first interconnection scheme and coupling the second copper layer of the second metal contact to the first interconnection scheme.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The drawings disclose illustrative embodiments of the present application. They do not set forth all embodiments. Other embodiments may be used in addition or instead. Details that may be apparent or unnecessary may be omitted to save space or for more effective illustration. Conversely, some embodiments may be practiced without all of the details that are disclosed. When the same reference number or reference indicator appears in different drawings, it may refer to the same or like components or steps.

(2) Aspects of the disclosure may be more fully understood from the following description when read together with the accompanying drawings, which are to be regarded as illustrative in nature, and not as limiting. The drawings are not necessarily to scale, emphasis instead being placed on the principles of the disclosure. In the drawings:

(3) FIGS. 1A and 1B are schematically cross-sectional views showing first and second types of vertical-through-via (VTV) connectors for a first alternative for a first case in accordance with an embodiment of the present application.

(4) FIGS. 1C and 1D are schematically cross-sectional views showing first and second types of vertical-through-via (VTV) connectors for a first alternative for a second case in accordance with an embodiment of the present application.

(5) FIGS. 1E and 1F are schematically cross-sectional views showing first and second types of vertical-through-via (VTV) connectors for a first alternative for a third case in accordance with an embodiment of the present application.

(6) FIGS. 2A and 2B are schematically cross-sectional views showing first and second types of vertical-through-via (VTV) connectors for a second alternative for the first case in accordance with an embodiment of the present application.

(7) FIGS. 2C and 2D are schematically cross-sectional views showing a process for forming first and second types of vertical-through-via (VTV) connectors for a second alternative for the second case in accordance with an embodiment of the present application.

(8) FIGS. 2E and 2F are schematically cross-sectional views showing a process for forming first and second types of vertical-through-via (VTV) connectors for a second alternative for the third case in accordance with an embodiment of the present application.

(9) FIG. 3A is a schematically cross-sectional view showing a decoupling capacitor in a first type of vertical-through-via (VTV) connector in accordance with an embodiment of the present application.

(10) FIG. 3B is a schematically top view showing a decoupling capacitor between four vertical through vias (VTVs) in accordance with an embodiment of the present application, wherein FIG. 3A is a schematically cross-sectional view along a cross-sectional line A-A on FIG. 3B.

(11) FIG. 3C is a schematically cross-sectional view showing a decoupling capacitor in a first type of vertical-through-via (VTV) connector in accordance with another embodiment of the present application.

(12) FIG. 3D is a schematically top view showing a decoupling capacitor among four through silicon vias (TSVs) in accordance with another embodiment of the present application, wherein FIG. 3C is a schematically cross-sectional view along a cross-sectional line B-B on FIG. 3D.

(13) FIG. 4A is a schematically cross-sectional view showing a first type of vertical-through-via (VTV) connector for a third alternative for the first case in accordance with an embodiment of the present application.

(14) FIG. 4B is a schematically cross-sectional view showing a first type of vertical-through-via (VTV) connector for a third alternative for the second case in accordance with an embodiment of the present application.

(15) FIG. 4C is a schematically cross-sectional view showing a first type of vertical-through-via (VTV) connector for a third alternative for the third case in accordance with an embodiment of the present application.

(16) FIG. 5A is a schematically cross-sectional view showing a first type of vertical-through-via (VTV) connector for a fourth alternative for the first case in accordance with an embodiment of the present application.

(17) FIG. 5B is a schematically cross-sectional view showing a first type of vertical-through-via (VTV) connector for a fourth alternative for the second case in accordance with an embodiment of the present application.

(18) FIG. 5C is a schematically cross-sectional view showing a first type of vertical-through-via (VTV) connector for a fourth alternative for the third case in accordance with an embodiment of the present application.

(19) FIG. 6 is a schematically cross-sectional view showing a first type of vertical-through-via (VTV) connector for a fifth alternative in accordance with an embodiment of the present application.

(20) FIG. 7 is a schematic view showing a block diagram of a programmable logic cell in accordance with an embodiment of the present application.

(21) FIG. 8 is a circuit diagram illustrating programmable interconnects controlled by a programmable switch cell in accordance with an embodiment of the present application.

(22) FIG. 9 is a schematically top view showing a block diagram of a standard commodity FPGA IC chip in accordance with an embodiment of the present application.

(23) FIG. 10 is a schematically top view showing a block diagram of a dedicated programmable interconnection (DPI) integrated-circuit (IC) chip in accordance with an embodiment of the present application.

(24) FIG. 11 is a schematically top view showing a block diagram of an auxiliary and supporting (AS) integrated-circuit (IC) chip in accordance with an embodiment of the present application.

(25) FIG. 12A is a schematically top view showing arrangement for various semiconductor integrated-circuit (IC) chips or operation units packaged in a standard commodity logic drive in accordance with an embodiment of the present application.

(26) FIG. 12B is a block diagram showing interconnection in a standard commodity logic drive in accordance with an embodiment of the present application.

(27) FIGS. 13A and 13B are schematically cross-sectional views showing various fine-line interconnection bridges in accordance with an embodiment of the present application.

(28) FIGS. 14A-14F are schematically cross-sectional views showing various semiconductor integrated-circuit (IC) chips in accordance with an embodiment of the present application.

(29) FIGS. 15A and 15C are schematically cross-sectional views showing various first type of memory modules in accordance with an embodiment of the present application.

(30) FIGS. 15B and 15D are schematically cross-sectional views showing various second type of memory modules in accordance with an embodiment of the present application.

(31) FIGS. 16A and 16B are schematically cross-sectional views showing a process of bonding a thermal compression bump to a thermal compression pad in accordance with an embodiment of the present application.

(32) FIGS. 16C and 16D are schematically cross-sectional views showing a direct bonding process in accordance with an embodiment of the present application.

(33) FIGS. 17A-17F are schematically cross-sectional views showing a process for fabricating a first type of operation unit in accordance with an embodiment of the present application.

(34) FIG. 17G is a schematically cross-sectional view showing a first type of operation unit in accordance with another embodiment of the present application.

(35) FIGS. 18A and 18B are schematically cross-sectional views showing a process of bonding a thermal compression bump to a thermal compression pad in accordance with an embodiment of the present application.

(36) FIGS. 19A-19G are schematically cross-sectional views showing a process for fabricating a first type of operation unit in accordance with another embodiment of the present application.

(37) FIG. 19H is a schematically cross-sectional view showing a first type of operation unit in accordance with another embodiment of the present application.

(38) FIGS. 20A and 20B are schematically cross-sectional views showing various second type of operation units in accordance with an embodiment of the present application.

(39) FIGS. 21A and 21B are schematically cross-sectional views showing various second type of operation units in accordance with another embodiment of the present application.

(40) FIGS. 22A-22H are schematically cross-sectional views showing a process for forming a first type of multichip package in accordance with a first embodiment of the present application.

(41) FIG. 22I is a schematically cross-sectional view showing a first type of single-chip/unit package in accordance with a first embodiment of the present application.

(42) FIGS. 23A and 23B are schematically cross-sectional views showing a process for forming a second type of multichip package in accordance with a first embodiment of the present application.

(43) FIG. 23C is a schematically top view showing a second type of multichip package in accordance with a first embodiment of the present application, wherein FIG. 23B is a schematically cross-sectional view along a cross-sectional line C-C on FIG. 23C.

(44) FIG. 23D is a schematically cross-sectional view along a cross-sectional line D-D on FIG. 23C.

(45) FIG. 23E is a schematically cross-sectional view showing a second type of single-chip/unit package in accordance with a first embodiment of the present application.

(46) FIGS. 24A and 24B are schematically cross-sectional views showing a process for forming various package-on-package (POP) assemblies for multiple first type of chip packages in accordance with a first embodiment of the present application.

(47) FIG. 25 is a schematically cross-sectional view showing a process for forming a package-on-package (POP) assembly for multiple second type of chip packages in accordance with a first embodiment of the present application.

(48) FIG. 26 is a schematically cross-sectional view showing a fan-out interconnection scheme in accordance with various embodiments of the present application.

(49) FIGS. 27A-27G are schematically cross-sectional views showing a process for forming a first type of multichip package in accordance with a second embodiment of the present application.

(50) FIG. 27H is a schematically cross-sectional view showing a second type of single-chip/unit package in accordance with a first embodiment of the present application.

(51) FIGS. 28A and 28B are schematically cross-sectional views showing a process of bonding a thermal compression bump of a semiconductor integrated-circuit chip to a thermal compression pad of a fan-out interconnection scheme for a logic drive or device (FOISD) in accordance with an embodiment of the present application.

(52) FIGS. 29A and 29B are schematically cross-sectional views showing a process of bonding a thermal compression bump of a first type of vertical-through-via (VTV) connector to a thermal compression pad of a fan-out interconnection scheme for a logic drive or device (FOISD) in accordance with an embodiment of the present application.

(53) FIGS. 30A-30C are schematically cross-sectional views showing a process for forming a second type of multichip package in accordance with a second embodiment of the present application.

(54) FIG. 30D is a schematically cross-sectional view showing a second type of single-chip/unit package in accordance with a second embodiment of the present application.

(55) FIG. 31 is a schematically cross-sectional view showing a process for forming a package-on-package (POP) assembly for multiple first type of chip packages in accordance with a second embodiment of the present application.

(56) FIG. 32 is a schematically cross-sectional view showing a process for forming a package-on-package (POP) assembly for multiple second type of chip packages in accordance with a second embodiment of the present application.

(57) FIG. 33A is a schematically cross-sectional view showing a first type of interposer in accordance with an embodiment of the present application.

(58) FIG. 33B is a schematically cross-sectional view showing a second type of interposer in accordance with an embodiment of the present application.

(59) FIGS. 34A-34H are schematically cross-sectional views showing a process for forming a first type of multichip package in accordance with a third embodiment of the present application.

(60) FIG. 34I is a schematically cross-sectional view showing a first type of single-chip/unit package in accordance with a third embodiment of the present application.

(61) FIGS. 35A and 35B are schematically cross-sectional views showing a process of bonding a thermal compression bump of a semiconductor integrated-circuit (IC) chip to a thermal compression pad of an interposer in accordance with an embodiment of the present application.

(62) FIGS. 36A and 36B are schematically cross-sectional views showing a process of bonding a thermal compression bump of a first type of vertical-through-via (VTV) connector to a thermal compression pad of an interposer in accordance with an embodiment of the present application.

(63) FIGS. 37A-37C are schematically cross-sectional views showing another process for forming a first type of multichip package in accordance with a third embodiment of the present application.

(64) FIG. 37D is a schematically cross-sectional view showing another first type of single-chip/unit package in accordance with a third embodiment of the present application.

(65) FIGS. 38A and 38B are schematically cross-sectional views showing a process for forming a second type of multichip packages in accordance with a third embodiment of the present application.

(66) FIG. 38C is a schematically cross-sectional view showing a second type of single-chip/unit package in accordance with a third embodiment of the present application.

(67) FIG. 39A is a schematically cross-sectional views showing another second type of multichip packages in accordance with a third embodiment of the present application.

(68) FIG. 39B is a schematically cross-sectional view showing another second type of single-chip/unit package in accordance with a third embodiment of the present application.

(69) FIGS. 40A and 40B are schematically cross-sectional views showing a process for forming various package-on-package (POP) assemblies for multiple first type of chip packages in accordance with a third embodiment of the present application.

(70) FIGS. 41A and 41B are schematically cross-sectional views showing a process for forming various package-on-package (POP) assemblies for multiple second type of chip packages in accordance with a third embodiment of the present application.

(71) FIGS. 42A-42E are schematically cross-sectional views showing a process for forming a first type of multichip package in accordance with a fourth embodiment of the present application.

(72) FIG. 42F is a schematically cross-sectional view showing a first type of single-chip/unit package in accordance with a fourth embodiment of the present application.

(73) FIGS. 43A and 43B are schematically cross-sectional views showing a process of bonding a thermal compression bump for a high-density, small-size bump of a semiconductor chip to a thermal compression pad for a high-density, small-size pad of an interconnection substrate in accordance with an embodiment of the present application.

(74) FIGS. 43C and 43D are schematically cross-sectional views showing a process of bonding a thermal compression bump for a low-density, large-size bump of a semiconductor chip to a thermal compression pad for a low-density, large-size pad of an interconnection substrate in accordance with an embodiment of the present application.

(75) FIGS. 44A and 44B are schematically cross-sectional views showing a process of bonding a thermal compression bump for a high-density, small-size bump of a vertical-through-via (VTV) connector to a thermal compression pad for a high-density, small-size pad of an interconnection substrate in accordance with an embodiment of the present application.

(76) FIGS. 44C and 44D are schematically cross-sectional views showing a process of bonding a thermal compression bump for a low-density, large-size bump of a vertical-through-via (VTV) connector to a thermal compression pad for a low-density, large-size pad of an interconnection substrate in accordance with an embodiment of the present application.

(77) FIGS. 45A and 45B are schematically cross-sectional views showing a process for forming a second type of multichip package in accordance with a fourth embodiment of the present application.

(78) FIG. 45C is a schematically cross-sectional view showing a second type of single-chip/unit package in accordance with a fourth embodiment of the present application.

(79) FIG. 46 is schematically a cross-sectional view showing a process for forming a package-on-package (POP) assembly for multiple first type of chip packages in accordance with a fourth embodiment of the present application.

(80) FIG. 47 is a schematically cross-sectional view showing a process for forming a package-on-package (POP) assembly for multiple second type of chip packages in accordance with a fourth embodiment of the present application.

(81) FIG. 48A is a schematically cross-sectional view showing a multichip package in accordance with a fifth embodiment of the present application.

(82) FIG. 48B is a schematically cross-sectional view showing a process for forming a package-on-package (POP) assembly for multiple chip packages in accordance with a fifth embodiment of the present application.

(83) FIG. 49 is a circuit diagram showing a method for controlling each semiconductor integrated-circuit (IC) chip of a package-on-package assembly in accordance with an embodiment of the present application.

(84) FIG. 50 is a circuit diagram showing a method for controlling each semiconductor integrated-circuit (IC) chip of a package-on-package assembly in accordance with an embodiment of the present application.

(85) FIG. 51 is a chart showing a trend of relationship between non-recurring engineering (NRE) costs and technology nodes.

(86) While certain embodiments are depicted in the drawings, one skilled in the art will appreciate that the embodiments depicted are illustrative and that variations of those shown, as well as other embodiments described herein, may be envisioned and practiced within the scope of the present application.

DETAILED DESCRIPTION OF THE DISCLOSURE

(87) Illustrative embodiments are now described. Other embodiments may be used in addition or instead. Details that may be apparent or unnecessary may be omitted to save space or for a more effective presentation. Conversely, some embodiments may be practiced without all of the details that are disclosed.

(88) Specification for First and Second Types of Vertical-Through-Via (VTV) Connectors (Vertical-Interconnect-Elevator (VIE) Chips or Components)

(89) A vertical-through-via (VTV) connector is provided with multiple vertical through vias (VTVs) for vertical connection to transmit signals or clocks or deliver power or ground in a vertical direction. The vertical-through-via (VTV) connector may be of a first or second type mentioned as below:

(90) 1. First Alternative for First and Second Types of Vertical-Through-Via (VTV) Connectors for Through-Silicon-Via Interconnect Elevators (TSVIEs)

(91) FIGS. 1A and 1B are schematically cross-sectional views showing first and second types of vertical-through-via (VTV) connectors for a first alternative for a first case in accordance with an embodiment of the present application. FIGS. 1C and 1D are schematically cross-sectional views showing first and second types of vertical-through-via (VTV) connectors for a first alternative for a second case in accordance with an embodiment of the present application. FIGS. 1E and 1F are schematically cross-sectional views showing first and second types of vertical-through-via (VTV) connectors for a first alternative for a third case in accordance with an embodiment of the present application. In a first alternative, referring to each of FIGS. 1A, 1C and 1E, a first type of vertical-through-via (VTV) connectors 467 may include (1) a semiconductor substrate 2, i.e., silicon substrate, (2) an insulating dielectric layer 12 on the semiconductor substrate 2, wherein the insulating dielectric layer 12 may include a silicon-oxide layer having a thickness between 0.1 and 2 μm, and wherein multiple blind holes 2a may be formed in the insulating dielectric layer 12 and semiconductor substrate 2, and each of the blind holes 2a may have a depth between 30 μm and 2,000 μm and a diameter or largest transverse dimension between 2 μm and 20 μm or between 4 μm and 10 μm, and (3) multiple through silicon vias (TSVs) 157 each in one of the blind holes 2a, wherein each of the through silicon vias (TSVs) 157 may vertically extend in one of the blind holes 2a in the semiconductor substrate 2 and through the insulating dielectric layer 12. Each of the through silicon vias (TSVs) 157 may include (1) an insulating lining layer 153, such as a layer of thermally grown silicon oxide (SiO.sub.2), a layer of CVD silicon nitride (Si.sub.3N.sub.4) or a combination thereof, on a sidewall and bottom of one of the blind holes 2a, (2) a copper layer 156 electroplated in said one of the blind holes 2a, wherein the copper layer 156 may have a top surface coplanar with a top surface of the insulating dielectric layer 12, (3) an adhesion layer 154, such as a layer of titanium (Ti) or titanium nitride (TiN) having a thickness between 1 nm to 50 nm, on the insulating lining layer 153, between the insulating lining layer 153 and copper layer 156 and at a sidewall and bottom of the copper layer 156, and (4) a seed layer 155, such as a layer of copper having a thickness between 3 nm and 200 nm, between the adhesion layer 154 and copper layer 156 and at a sidewall and bottom of the copper layer 156. Each of the through silicon vias (TSVs) 157 may be used as a vertical through via (VTV) 358 for a dedicated vertical path. Each of the vertical through vias (VTVs) 358 formed by the through silicon vias (TSVs) may have a depth between 30 μm and 200 and a largest transverse dimension, such as diameter or width, between 2 μm and 20 μm or between 4 μm and 10 μM.

(92) Referring to each of FIGS. 1A, 1C and 1E, each of the first type of vertical-through-via (VTV) connectors 467 may further include a passivation layer 14 on a top surface of the insulating dielectric layer 12. The passivation layer 14 may include a mobile ion-catching layer or layers, for example, a combination of silicon nitride, silicon oxynitride, and/or silicon carbon nitride layer or layers deposited by a chemical vapor deposition (CVD) process. For example, the passivation layer 14 may include a silicon-nitride layer having a thickness of more than 0.3 micrometers. Alternatively, the passivation layer 14 may include a polymer layer, such as polyimide, having a thickness between 1 and 5 micrometers. Next, multiple openings 14a may be formed in the passivation layer 14 and each of the openings 14a may expose the copper layer 156 of one of the through silicon vias (TSVs) 157. Each of the openings 14a may have a transverse dimension d, from a top view, between 0.5 and 20 micrometers or between 20 and 200 micrometers. The shape of the opening 14a from a top view may be a circle, and the diameter of the circle-shaped opening 14a may be between 0.5 and 20 micrometers or between 20 and 200 micrometers. Alternatively, the shape of the opening 14a from a top view may be a square, and the width of the square-shaped opening 14a may be between 0.5 and 20 micrometers or between 20 and 200 micrometers. Alternatively, the shape of the opening 14a from a top view may be a polygon, such as hexagon or octagon, and the polygon-shaped opening 14a may have a width between 0.5 and 20 micrometers or between 20 and 200 micrometers. Alternatively, the shape of the opening 14a from a top view may be a rectangle, and the rectangle-shaped opening 14a may have a shorter width between 0.5 and 20 micrometers or between 20 and 200 micrometers.

(93) Referring to each of FIGS. 1A, 1C and 1E, each of the first type of vertical-through-via (VTV) connectors 467 may further include multiple micro-bumps or micro-pads 34, i.e., metal bumps, pads or conductive interconnects, each on the copper layer 156 of one of the through silicon vias (TSVs) 157 at a bottom of one of the openings 14a in the passivation layer 14. The micro bumps or micro-pads 34 may be of various types. A first type of micro-bump or micro-pad 34 may include (1) an adhesion layer 26a, such as titanium (Ti) or titanium nitride (TiN) layer having a thickness between 1 nm and 50 nm, on the copper layer 156 of the through silicon vias (TSVs) 157, (2) a seed layer 26b, such as copper, on its adhesion layer 26a and (3) a copper layer 32 having a thickness between 1 μm and 60 μm on its seed layer 26b.

(94) Alternatively, a second type of micro-bump or micro-pad 34 may include the adhesion layer 26a, seed layer 26b and copper layer 32 as mentioned above, and may further include, as seen in FIG. 1B, a tin-containing solder cap 33 made of tin or a tin-silver alloy having a thickness between 1 μm and 50 μm on its copper layer 32.

(95) Alternatively, a third type of micro-bump or micro-pad 34 may be a thermal compression bump, including the adhesion layer 26a and seed layer 26b as mentioned above, and may further include, as seen in any of FIGS. 16A, 18A, 28A, 29A, 35A and 36A, a copper layer 37 having a thickness t3 between 2 μm and 20 μm and a largest transverse dimension w3, such as diameter in a circular shape, between 1 μm and 25 μm on its seed layer 26b and a solder cap 38 made of a tin-silver alloy, a tin-gold alloy, a tin-copper alloy, a tin-indium alloy, indium or tin, which has a thickness between 1 μm and 15 μm and a largest transverse dimension, such as diameter in a circular shape, between 1 μm and 15 μm on its copper layer 37. A pitch between neighboring two of the third type of micro-bumps or micro-pads 34 may be between 5 and 30 micrometers or between 10 and 25 micrometers.

(96) Alternatively, a fourth type of micro-bump or micro-pad 34 may be a thermal compression pad, including the adhesion layer 26a and seed layer 26b as mentioned above, and may further include, as seen in FIG. 18A, a copper layer 48 having a thickness t2 between 1 μm and 20 μm or between 2 μm and 10 μm and a largest transverse dimension w2, such as diameter in a circular shape, between 5 μm and 50 μm, on its seed layer 26b and a solder cap 49 made of a tin-silver alloy, a tin-gold alloy, a tin-copper alloy, a tin-indium alloy, indium, tin or gold, which has a thickness between 0.1 μm and 5 μm on its copper layer 48. A pitch between neighboring two of the fourth type of micro-bumps or micro-pads 34 may be between 5 and 30 micrometers or between 10 and 25 micrometers.

(97) In the first alternative, a second type of vertical-through-via (VTV) connector 467 as seen in FIG. 1B, 1D or 1F is similar to the first type of vertical-through-via (VTV) connector 467 as illustrated in FIG. 1A, 1C or 1E respectively, but has none of the passivation layer 14 and micro-bumps or micro-pads 34 as illustrated in FIG. 1A, 1C or 1E and the insulating dielectric layer 12 of the second type of vertical-through-via (VTV) connector 467 as seen in each of FIGS. 1B, 1D and 1F may act as an insulating bonding layer 52.

(98) In the first alternative, for the first case, referring to FIGS. 1A and 1B, a pitch W.sub.p between each neighboring two of the vertical through vias (VTVs) 358 in the semiconductor substrate 2 may range from 20 to 150 micrometers or from 40 to 100 micrometers or may be smaller than 50, 40 or 30 micrometers; and a space W.sub.sptsv between each neighboring two of the vertical through vias (VTVs) 358 in the semiconductor substrate 2 may range from 20 to 150 micrometers or from 40 to 100 micrometers or may be smaller than 50, 40 or 30 micrometers. Multiple trenches 14b for reserved scribe lines may be formed in the passivation layer 14 to form multiple insulating-material islands 14c between neighboring two of the trenches 14b. The vertical through vias (VTVs) 358 arranged in only one line are arranged between neighboring two of the reserved scribe lines 141. Each of the insulating-material islands 14c may be aligned with only one of the vertical through vias (VTVs) 358, and one of the openings 14a in said each of the insulating-material islands 14c may be arranged over said only one of the vertical through vias (VTVs) 358. None of the vertical through vias (VTVs) 358 may be arranged under each of the trenches 14b. Accordingly, the pitch W.sub.p and space W.sub.sptsv between each neighboring two of the vertical through vias (VTVs) 358 may be greater than a width W.sub.sb of the reserved scribe lines 141 or greater than the width W.sub.sb of the reserved scribe lines 141 plus two times of a predetermined space W.sub.sbt between one of the reserved scribe lines 141 and one of said each neighboring two of the vertical through vias (VTVs) 358 adjacent to said one of the first reserved scribe lines 141. For each of the first and second types of vertical-through-via (VTV) connectors 467, the distance W.sub.sbt between its edge and one of its vertical through vias (VTVs) 358 may be smaller than the space W.sub.sptsv between neighboring two of its vertical through vias (VTVs) 358 and optionally its edge may be aligned with an edge of said one of its vertical through vias (VTVs) 358.

(99) In the first alternative, for the second case, referring to FIGS. 1C and 1D, the vertical through vias (VTVs) 358 may be populated regularly in multiple islands or regions 188 of arrays of vertical through vias (VTVs) with the reserved scribe lines 141 each between neighboring two of the islands or regions 188 of arrays of vertical through vias (VTVs). A pitch W.sub.p between each neighboring two of the vertical through vias (VTVs) 358 aligned with one of the islands or regions 188 of arrays of vertical through vias (VTVs) may range from 5 to 50 micrometers or from 5 to 20 micrometers or may be smaller than 50, 40 or 30 micrometers; and a space W.sub.sptsv between neighboring two of the vertical through vias (VTVs) 358 aligned with one of the islands or regions 188 of arrays of vertical through vias (VTVs) may range from 5 to 50 micrometers or from 5 to 20 micrometers or may be smaller than 50, 40 or 30 micrometers. For each of the islands or regions 188 of arrays of vertical through vias (VTVs), its vertical through vias (VTVs) 358 may be arranged in multiple columns and in multiple rows; its insulating-material island 14c may be aligned with its vertical through vias (VTVs) 358, and multiple of the openings 14a in its insulating-material island 14c may be arranged over its vertical through vias (VTVs) 358 respectively. The pitch W.sub.p and space W.sub.sptsv between each neighboring two of the vertical through vias (VTVs) 358 aligned with one of the islands or regions 188 of arrays of vertical through vias (VTVs) may be smaller than the width W.sub.sb of the reserved scribe lines 141 and/or smaller than a first space W.sub.spild between neighboring two of the vertical through vias (VTVs) 358 aligned with neighboring two of the islands or regions 188 of arrays of vertical through vias (VTVs) respectively and across one of the reserved scribe lines 141 between said neighboring two of the islands or regions 188 of arrays of vertical through vias (VTVs). The space W.sub.spild or a width of the trench 14b between neighboring two of the insulating-material islands 14c may be greater than 50, 40 or 30 micrometers. The space W.sub.spild may be greater than the width W.sub.sb of the reserved scribe lines 141 or greater than the width W.sub.sb of the reserved scribe lines 141 plus two times of a predetermined space W.sub.sbt between one of the reserved scribe lines 141 and one of the vertical through vias (VTVs) 358 adjacent to said one of the reserved scribe lines 141. For each of the first and second types of vertical-through-via (VTV) connectors 467, each of its first and second spaces W.sub.spild between neighboring two of its vertical through vias (VTVs) 358 and across one of its first and second reserved scribe lines 141 and 142 between said neighboring two of its vertical through vias (VTVs) 358 may be greater than 50 or 40 micrometers, and the distance W.sub.sbt between its edge and one of its vertical through vias (VTVs) 358 may be smaller than the space W.sub.sptsv between neighboring two of its vertical through vias (VTVs) 358 and optionally its edge may be aligned with an edge of said one of its vertical through vias (VTVs) 358.

(100) In the first alternative, for the third case, referring to FIGS. 1E and 1F, a pitch W.sub.p between each neighboring two of the vertical through vias (VTVs) 358 in the semiconductor substrate 2 may range from 5 to 50 micrometers or from 5 to 20 micrometers or may be smaller than 50, 40 or 30 micrometers; and a space W.sub.sptsv between neighboring two of the vertical through vias (VTVs) 358 may range from 5 to 50 micrometers or from 5 to 20 micrometers or may be smaller than 50, 40 or 30 micrometers. Each reserved scribe line 141 may extend in line with multiple of the vertical through vias (VTVs) 358 arranged in a line. Accordingly, the pitch W.sub.p and space W.sub.sptsv between each neighboring two of the vertical through vias (VTVs) 358 may be smaller than a width W.sub.sb of the reserved scribe lines 141 or smaller than the width W.sub.sb of the reserved scribe lines 141 plus two times of a predetermined space W.sub.sbt between one of the reserved scribe lines 141 and one of the vertical through vias (VTVs) 358 adjacent to said one of the reserved scribe lines 141. For each of the first and second types of vertical-through-via (VTV) connectors 467, the distance W.sub.sbt between its edge and one of its vertical through vias (VTVs) 358 may be smaller than the space W.sub.sptsv between neighboring two of its vertical through vias (VTVs) 358 and optionally its edge may be aligned with an edge of said one of its vertical through vias (VTVs) 358, wherein the space W.sub.sptsv between neighboring two of its vertical through vias (VTVs) 358 may be smaller than 50, 40 or 30 micrometers.

(101) In the first alternative, for the first case, referring to FIG. 1A, a pitch WB.sub.p between each neighboring two of the first, second, third or fourth type of micro-bumps or micro-pads 34 may range from 20 to 150 micrometers or from 40 to 100 micrometers; and a space WB.sub.sptsv between each neighboring two of the first, second, third or fourth type of micro-bumps or micro-pads 34 may range from 20 to 150 micrometers or from 40 to 100 micrometers. The first, second, third or fourth type of micro-bumps or micro-pads 34 arranged in only one line are arranged between neighboring two of the reserved scribe lines 141. Each of the insulating-material islands 14c may be aligned with only one of the first, second, third or fourth type of micro-bumps or micro-pads 34, and one of the openings 14a in said each of the insulating-material islands 14c may be arranged under said only one of the first, second, third or fourth type of micro-bumps or micro-pads 34. Accordingly, the pitch WB.sub.p and space WB.sub.sptsv between each neighboring two of the first, second, third or fourth type of micro-bumps or micro-pads 34 may be greater than the width W.sub.sb of the second reserved scribe lines 142 or greater than the width W.sub.sb of the reserved scribe lines 141 plus two times of a predetermined space WB.sub.sbt between one of the reserved scribe lines 141 and one of said each neighboring two of the first, second, third or fourth type of micro-bumps or micro-pads 34 adjacent to said one of the reserved scribe lines 141. For the first type of vertical-through-via (VTV) connector 467, the distance WB.sub.Sbt between its edge and one of its first, second, third or fourth type of micro-bumps or micro-pads 34 may be smaller than the space WB.sub.sptsv between neighboring two of its first, second, third or fourth type of micro-bumps or micro-pads 34 and optionally its edge may be aligned with an edge of said one of its first, second, third or fourth type of micro-bumps or micro-pads 34; alternatively, the distance WB.sub.sbt between its edge and one of its first, second, third or fourth type of micro-bumps or micro-pads 34 may be smaller than 50, 40 or 30 micrometers.

(102) In the first alternative, for the second case, referring to FIG. 1C, the first, second, third or fourth type of micro-bumps or micro-pads 34 may be populated regularly in multiple islands or regions 88 of arrays of micro-bumps or micro-pads with the reserved scribe lines 141 each between neighboring two of the islands or regions 88 of arrays of micro-bumps or micro-pads. A pitch WB.sub.p between each neighboring two of the first, second, third or fourth type of micro-bumps or micro-pads 34 aligned with one of the islands or regions 88 of arrays of micro-bumps or micro-pads may range from 5 to 50 micrometers or from 5 to 20 micrometers or may be smaller than 50, 40 or 30 micrometers; and a space WB.sub.sptsv between neighboring two of the first, second, third or fourth type of micro-bumps or micro-pads 34 aligned with one of the islands or regions 88 of arrays of micro-bumps or micro-pads may range from 5 to 50 micrometers or from 5 to 20 micrometers or may be smaller than 50, 40 or 30 micrometers. For each of the islands or regions 88 of arrays of micro-bumps or micro-pads, its first, second, third or fourth type of micro-bumps or micro-pads 34 may be arranged in multiple columns and in multiple rows; its insulating-material island 14c may be aligned with its first, second, third or fourth type of micro-bumps or micro-pads 34, and multiple of the openings 14a in its insulating-material island 14c may be arranged under its first, second, third or fourth type of micro-bumps or micro-pads 34 respectively. The pitch WB.sub.p and space WB.sub.sptsv between each neighboring two of the first, second, third or fourth type of micro-bumps or micro-pads 34 aligned with one of the islands or regions 88 of arrays of micro-bumps or micro-pads may be smaller than the width W.sub.sb of the reserved scribe lines 141 and/or smaller than a space WB.sub.spild between neighboring two of the first, second, third or fourth type of micro-bumps or micro-pads 34 aligned with neighboring two of the islands or regions 88 of arrays of micro-bumps or micro-pads respectively and across one of the reserved scribe lines 141 between said neighboring two of the islands or regions 88 of arrays of micro-bumps or micro-pads. The space WB.sub.spild or a width of the trench 14b between neighboring two of the insulating-material islands 14c may be greater than 50, 40 or 30 micrometers. The space WB.sub.spild may be greater than the width W.sub.sb of the reserved scribe lines 141 or greater than the width W.sub.sb of the reserved scribe lines 141 plus two times of a predetermined space WB.sub.sbt between one of the reserved scribe lines 141 and one of the first, second, third or fourth type of micro-bumps or micro-pads 34 adjacent to said one of the reserved scribe lines 141. The first type of vertical-through-via (VTV) connector 467 may include the insulating-material islands 14c having the trench 14b therebetween having a width greater than 50 or 40 micrometers; each of its spaces WB.sub.spild each between neighboring two of its first, second, third or fourth type of micro-bumps or micro-pads 34 and across one of its reserved scribe lines 141 between said neighboring two of its first, second, third or fourth type of micro-bumps or micro-pads 34 may be greater than 50, 40 or 30 micrometers; the distance WB.sub.sbt between its edge and one of its first, second, third or fourth type of micro-bumps or micro-pads 34 may be smaller than the space WB.sub.sptsv between neighboring two of its first, second, third or fourth type of micro-bumps or micro-pads 34 and optionally its edge may be aligned with an edge of said one of its first, second, third or fourth type of micro-bumps or micro-pads 34; alternatively, the distance WB.sub.sbt between its edge and one of its first, second, third or fourth type of micro-bumps or micro-pads 34 may be smaller than 50, 40 or 30 micrometers.

(103) In the first alternative, for the third case, referring to FIG. 1E, a pitch WB.sub.p between each neighboring two of the first, second, third or fourth type of micro-bumps or micro-pads 34 may range from 5 to 50 micrometers or from 5 to 20 micrometers or may be smaller than 50, 40 or 30 micrometers; and a space WB.sub.sptsv between neighboring two of the first, second, third or fourth type of micro-bumps or micro-pads 34 may range from 5 to 50 micrometers or from 5 to 20 micrometers or may be smaller than 50, 40 or 30 micrometers. Each of the reserved scribe lines 141 may extend in line with multiple of the first, second, third or fourth type of micro-bumps or micro-pads 34 arranged in a line. Accordingly, the pitch WB.sub.p and space WB.sub.sptsv between each neighboring two of the first, second, third or fourth type of micro-bumps or micro-pads 34 may be smaller than the width W.sub.sb of the reserved scribe lines 141 or smaller than the width W.sub.sb of the reserved scribe lines 141 plus two times of a predetermined space W.sub.sbt between one of the reserved scribe lines 141 and one of the first, second, third or fourth type of micro-bumps or micro-pads 34 adjacent to said one of the reserved scribe lines 141. For the first type of vertical-through-via (VTV) connector 467, the distance WB.sub.sbt between its edge and one of its first, second, third or fourth type of micro-bumps or micro-pads 34 may be smaller than the space WB.sub.sptsv, between neighboring two of its first, second, third or fourth type of micro-bumps or micro-pads 34 and optionally its edge may be aligned with an edge of said one of its first, second, third or fourth type of micro-bumps or micro-pads 34; alternatively, the distance WB.sub.sbt between its edge and one of its first, second, third or fourth type of micro-bumps or micro-pads 34 may be smaller than 50, 40 or 30 micrometers; the space WB.sub.sptsv between neighboring two of its first, second, third or fourth type of micro-bumps or micro-pads 34 may be smaller than 50, 40 or 30 micrometers.

(104) Referring to FIGS. 1A-1F for the first alternative, the aspect ratio of the length to the width for each of its first and second types of vertical-through-via (VTV) connectors 467 may be between 2 and 10, between 4 and 10 or between 2 and 40. Each of the first and second types of vertical-through-via (VTV) connectors 467 may be provided with passive elements, such as capacitors, but without any active device, i.e., transistor, therein. Each of the first and second types of vertical-through-via (VTV) connectors 467 may be manufactured by packaging manufacturing companies or facilities without front-end of line manufacturing capability.

(105) Accordingly, in the first alternative, for each of the first, second and third cases as seen in FIGS. 1A-1F, each of the first and second types of vertical-through-via (VTV) connectors 467 may be arranged with a size for containing the vertical through vias (VTVs) 358 arranged in an array with M1 row(s) by N1 column(s); furthermore, for each of the first, second and third cases as seen in FIGS. 1A, 1C and 1E, the first type of vertical-through-via (VTV) connector 467 may be arranged with a size for containing the first, second, third or fourth type of micro bumps or micro-pads 34 arranged in an array with M2 row(s) by N2 column(s), wherein M1, M2, N1 and N2 are integers, M1 is greater than N1 and M2 is greater than N2. For an example, each of the numbers M1 and M2 may be greater than or equal to 50 and smaller than or equal to 500, and each of the numbers N1 and N2 may be greater than or equal to 1 and smaller than or equal to 15. For another example, each of the numbers N1 and N2 may be greater than or equal to 30 and smaller than or equal to 200, and each of the numbers M1 and M2 may be greater than or equal to 1 and smaller than or equal to 10.

(106) 2. Second Alternative for First and Second Types of Vertical-Through-Via (VTV) Connectors for Through-Silicon-Via Interconnect Elevators (TSVIEs)

(107) FIGS. 2A and 2B are schematically cross-sectional views showing first and second types of vertical-through-via (VTV) connectors for a second alternative for the first case in accordance with an embodiment of the present application. FIGS. 2C and 2D are schematically cross-sectional views showing a process for forming first and second types of vertical-through-via (VTV) connectors for a second alternative for the second case in accordance with an embodiment of the present application. FIGS. 2E and 2F are schematically cross-sectional views showing a process for forming first and second types of vertical-through-via (VTV) connectors for a second alternative for the third case in accordance with an embodiment of the present application. In a second alternative, referring to each of FIGS. 2A, 2C and 2E, a first type of vertical-through-via (VTV) connectors 467 may include (1) multiple semiconductor substrates 2, i.e., silicon substrates, (2) multiple insulating dielectric layers 12 each on a first surface of one of the semiconductor substrates 2, wherein each of the insulating dielectric layers 12 may include a silicon-oxide layer having a thickness between 0.1 and 2 wherein one of the insulating dielectric layers 12 on the first surface of the bottommost one of the semiconductor substrates 2 may be attached to one of the insulating dielectric layers 12 on the first surface of the second bottommost one of the semiconductor substrates 2, (3) one or more insulating bonding layers 52 each on a second surface of one of the second bottommost through topmost ones of the semiconductor substrates 2, wherein the second surface of said one of the second bottommost through topmost ones of the semiconductor substrates 2 is opposite to the first surface of said one of the second bottommost through topmost ones of the semiconductor substrates 2, wherein each of the insulating bonding layers 52 may be made a layer of silicon oxide having a thickness between 1 and 1,000 nanometers, and wherein one of the insulating bonding layers 52 on the second surface of a lower one of the second bottommost through topmost ones of the semiconductor substrates 2 may have silicon oxide bonded to silicon oxide of one of the insulating dielectric layers 12 on the first surface of an upper one of the second bottommost through topmost ones of the semiconductor substrates 2, and (4) multiple through silicon vias (TSVs) 157 in each of the semiconductor substrates 2 and extending vertically through one of the insulating dielectric layers 12 on the first surface of said each of the semiconductor substrates 2 and/or one of the insulating bonding layers 52 on the second surface of said each of the semiconductor substrates 2.

(108) In the second alternative, referring to each of FIGS. 2A, 2C and 2E, each of the through silicon vias (TSVs) 157 in the bottommost one of the semiconductor substrates 2 and extending vertically through one of the insulating dielectric layers 12 on the first surface of the bottommost one of the semiconductor substrates 2 may include (1) an insulating lining layer 153, such as a layer of thermally grown silicon oxide (SiO.sub.2), a layer of CVD silicon nitride (Si.sub.3N.sub.4) or a combination thereof, on a sidewall and bottom of one of blind holes 2a in the bottommost one of the semiconductor substrates 2, (2) a copper layer 156 electroplated in said one of the blind holes 2a, wherein the copper layer 156 may have a top surface coplanar with a top surface of the insulating dielectric layer 12 on the first surface of the bottommost one of the semiconductor substrates 2, (3) an adhesion layer 154, such as a layer of titanium (Ti) or titanium nitride (TiN) having a thickness between 1 nm to 50 nm, on the insulating lining layer 153, between the insulating lining layer 153 and copper layer 156 and at a sidewall and bottom of the copper layer 156, and (4) a seed layer 155, such as a layer of copper having a thickness between 3 nm and 200 nm, between the adhesion layer 154 and copper layer 156 and at a sidewall and bottom of the copper layer 156.

(109) In the second alternative, referring to each of FIGS. 2A, 2C and 2E, each of the through silicon vias (TSVs) 157 in each of the second bottommost through topmost ones of the semiconductor substrates 2 and extending vertically through one of the insulating dielectric layers 12 on the first surface of said each of the second bottommost through topmost ones of the semiconductor substrates 2 and one of the insulating bonding layers 52 on the second surface of said each of the second bottommost through topmost ones of the semiconductor substrates 2 may include (1) an insulating lining layer 153, such as a layer of thermally grown silicon oxide (SiO.sub.2), a layer of CVD silicon nitride (Si.sub.3N.sub.4) or a combination thereof, on a sidewall of one of through holes in said each of the second bottommost through topmost ones of the semiconductor substrates 2, (2) a copper layer 156 electroplated in said one of the through holes, wherein the copper layer 156 may have a bottom surface coplanar with a bottom surface of the insulating dielectric layer 12 on the first surface of said each of the second bottommost through topmost ones of the semiconductor substrates 2 and a top surface coplanar with a top surface of the insulating bonding layer 52 on the second surface of said each of the second bottommost through topmost ones of the semiconductor substrates 2, (3) an adhesion layer 154, such as a layer of titanium (Ti) or titanium nitride (TiN) having a thickness between 1 nm to 50 nm, on the insulating lining layer 153, between the insulating lining layer 153 and copper layer 156 and at a sidewall of the copper layer 156, and (4) a seed layer 155, such as a layer of copper having a thickness between 3 nm and 200 nm, between the adhesion layer 154 and copper layer 156 and at a sidewall of the copper layer 156.

(110) In the second alternative, referring to each of FIGS. 2A, 2C and 2E, multiple of the through silicon vias (TSVs) 157 may be stacked with each other or one another to form a vertical through via (VTV) 358 for a dedicated vertical path, wherein the copper layer 156 of an upper one of the through silicon vias (TSVs) 157 may have the bottom surface bonded to the top surface of the copper layer 156 of a lower one of the through silicon vias (TSVs) 157. Each of the vertical through vias (VTVs) 358 may include multiple of the through silicon vias (TSVs) 157 stacked up to a total height between 100 and 2,000 micrometers, between 100 and 1,000 micrometers or between 100 and 500 micrometers.

(111) In the second alternative, referring to each of FIGS. 2A, 2C and 2E, the first type of vertical-through-via (VTV) connectors 467 may further include (1) a passivation layer 14, which may have the same specification as that as illustrated in each of FIGS. 1A, 1C and 1E, on the top surface of the insulating bonding layer 52 on the second surface of the topmost one of the semiconductor substrates 2, wherein each opening 14a in the passivation layer 14 may be vertically over the top surface of the copper layer 156 of one of the vertical through vias (VTVs) 358, wherein each of the openings 14a may have the same specification as that as illustrated in each of FIGS. 1A, 1C and 1E, and (2) multiple micro-bump or micro-pad 34, which may be of one of the first through fourth types having the same specifications as the first through fourth types of micro-bumps or micro-pads 34 as illustrated in each of FIGS. 1A, 1C and 1E respectively, each on the top surface of the copper layer 156 of one of the vertical through vias (VTVs) 358.

(112) In the second alternative, a second type of vertical-through-via (VTV) connector 467 as seen in FIG. 2B, 2D or 2F is similar to the first type of vertical-through-via (VTV) connector 467 as illustrated in FIG. 2A, 2C or 2E respectively, but has none of the passivation layer 14 and micro-bumps or micro-pads 34 as illustrated in FIG. 2A, 2C or 2E.

(113) In the second alternative, referring to FIGS. 2A and 2B for the first case, the arrangements for the vertical through vias (VTVs) 358 for each of the first and second types of vertical-through-via (VTV) connectors 467 may be the same as those as illustrated in FIGS. 1A and 1B for the first case for the first alternative; the arrangements for the trenches 14b, insulating-material islands 14c and first, second, third or fourth type of micro-bumps or micro-pads 34 for the first type of vertical-through-via (VTV) connector 467 may be the same as those as illustrated in FIG. 1A for the first case for the first alternative.

(114) Alternatively, in the second alternative, referring to FIGS. 2C and 2D for the second case, the arrangements for the vertical through vias (VTVs) 358 and islands or regions 188 of arrays of vertical through vias (VTVs) for each of the first and second types of vertical-through-via (VTV) connectors 467 may be the same as those as illustrated in FIGS. 1C and 1D for the second case for the first alternative; the arrangements for the islands or regions of arrays 88 of micro-bumps or micro-pads, trenches 14b, insulating-material islands 14c and first, second, third or fourth type of micro-bumps or micro-pads 34 for the first type of vertical-through-via (VTV) connector 467 may be the same as those as illustrated in FIG. 1C for the second case for the first alternative.

(115) Alternatively, in the second alternative, referring to FIGS. 2E and 2F for the third case, the arrangements for the vertical through vias (VTVs) 358 for each of the first and second types of vertical-through-via (VTV) connectors 467 may be the same as those as illustrated in FIGS. 1E and 1F for the third case for the first alternative; the arrangements for the first, second, third or fourth type of micro-bumps or micro-pads 34 for the first type of vertical-through-via (VTV) connector 467 may be the same as those as illustrated in FIG. 1E for the third case for the first alternative.

(116) Referring to FIGS. 2A-2F for the second alternative, the aspect ratio of the length to the width for each of the first and second types of vertical-through-via (VTV) connectors 467 may be between 2 and 10, between 4 and 10 or between 2 and 40. Each of the first and second types of vertical-through-via (VTV) connector 467 may be provided with passive elements, such as capacitors, but without any active device, i.e., transistor, therein.

(117) 3. Decoupling Capacitors in First Type of Vertical-Through-Via (VTV) Connector for Through-Silicon-Via Interconnect-Elevator (TSVIE)

(118) FIG. 3A is a schematically cross-sectional view showing a decoupling capacitor in a first type of vertical-through-via (VTV) connector in accordance with an embodiment of the present application. FIG. 3B is a schematically top view showing a decoupling capacitor between four vertical through vias (VTVs) in accordance with an embodiment of the present application, wherein FIG. 3A is a schematically cross-sectional view along a cross-sectional line A-A on FIG. 3B. For the first alternative for the first through third cases as illustrated in each of FIGS. 1A, 1C and 1E, the first type of vertical-through-via (VTV) connector 467 may further include a decoupling capacitor 401 therein as seen in FIGS. 3A and 3B, provided with (1) a first electrode 402 in a deep trench 2c having a depth between 30 μm and 2,000 μm in the semiconductor substrate 2 and vertically extending through the insulating dielectric layer 12, (2) a second electrode 404 in a shallow trench 2d having a depth between 5 μm and 30 μm or between 5 and 20 micrometers and less than the depth of the deep trenches 2c in the semiconductor substrate 2 and vertically extending through the insulating dielectric layer 12, and (3) a dielectric layer 403 between the first and second electrodes 402 and 404 and at a sidewall and bottom of the shallow trench 2d. The first electrode 402 of the decoupling capacitor 401 may include (1) an insulating lining layer 153, such as a layer of thermally grown silicon oxide (SiO.sub.2), a layer of CVD silicon nitride (Si.sub.3N.sub.4) or a combination thereof, on a sidewall and bottom of the deep trench 2c, (2) a copper layer 156 electroplated in the deep trench 2c, wherein the copper layer 156 of the first electrode 402 may have a top surface coplanar with a top surface of the insulating dielectric layer 12, (3) an adhesion layer 154, such as a layer of titanium (Ti) or titanium nitride (TiN) having a thickness between 1 nm to 50 nm, on the insulating lining layer 153 of the first electrode 402, between the insulating lining layer 153 and copper layer 156 of the first electrode 402 and at a sidewall and bottom of the copper layer 156 of the first electrode 402, and (4) a seed layer 155, such as a layer of copper having a thickness between 3 nm and 200 nm, between the adhesion layer 154 and copper layer 156 of the first electrode 402 and at a sidewall and bottom of the copper layer 156 of the first electrode 402. The dielectric layer 403 of the decoupling capacitor 401 may be a layer of tantalum oxide (Ta.sub.2O.sub.5), hafnium oxide (HfO.sub.2), zirconium oxide (ZrO.sub.2), titanium oxide (TiO.sub.2) or silicon nitride (Si.sub.3N.sub.4) having a thickness between 100 and 1,000 angstroms on a sidewall and bottom of the shallow trench 2d. The second electrode 404 of the decoupling capacitor 401 may include (1) a copper layer 156 electroplated in the shallow trench 2d, wherein the copper layer 156 of the second electrode 404 may have a top surface coplanar with the top surface of the insulating dielectric layer 12, (2) an adhesion layer 154, such as a layer of titanium (Ti) or titanium nitride (TiN) having a thickness between 1 nm to 50 nm, on the dielectric layer 403 of the decoupling capacitor 401, between the dielectric layer 403 of the decoupling capacitor 401 and the copper layer 156 of the second electrode 404 and at a sidewall and bottom of the copper layer 156 of the second electrode 404, and (3) a seed layer 155, such as a layer of copper having a thickness between 3 nm and 200 nm, between the adhesion layer 154 and copper layer 156 of the second electrode 404 and at a sidewall and bottom of the copper layer 156 of the second electrode 404.

(119) Accordingly, referring to FIGS. 3A and 3B, the decoupling capacitor 401 may be provided with the dielectric layer 403 between the first and second electrodes 402 and 404 thereof, wherein the first electrode 402 of the decoupling capacitor 401 may have a depth between 30 and 2,000 micrometers and the second electrode 404 of the decoupling capacitor 401 may have a depth between 5 and 30 micrometers or between 5 and 20 micrometers. It is noted that one of the first, second, third or fourth type of micro-bumps or micro-pads 34 may be formed on the copper layer 156 of one of the through silicon vias (TSVs) 157 and the second electrode 404 of the decoupling capacitor 401 beside the copper layer 156 of said one of the through silicon vias (TSVs) 157 to couple said one of the through silicon vias (TSVs) 157 to the second electrode 404 of the decoupling capacitor 401. Each of the through silicon vias (TSVs) 157 may be used as a vertical through via (VTV) 358 for a dedicated vertical path. For an element indicated by the same reference number shown in FIGS. 1A, 1C, 1E, 3A and 3B, the specification of the element as seen in FIGS. 3A and 3B may be referred to that of the element as illustrated in FIGS. 1A, 1C and 1E.

(120) Alternatively, FIG. 3C is a schematically cross-sectional view showing a decoupling capacitor in a first type of vertical-through-via (VTV) connector in accordance with another embodiment of the present application. FIG. 3D is a schematically top view showing a decoupling capacitor among four through silicon vias (TSVs) in accordance with another embodiment of the present application, wherein FIG. 3C is a schematically cross-sectional view along a cross-sectional line B-B on FIG. 3D. For the first alternative for the first through third cases as illustrated in each of FIGS. 1A, 1C and 1E, the first type of vertical-through-via (VTV) connector 467 may further include a decoupling capacitor 401 therein as seen in FIGS. 3C and 3D, provided with (1) a first electrode 402 in a first shallow trench 2f, which has a depth between 5 μm and 30 μm or between 5 μm and 20 μm and less than the depth of the blind holes 2a, in the semiconductor substrate 2 and vertically extending through the insulating dielectric layer 12, (2) a second electrode 404 in a second shallow trench 2g, which has a depth between 5 μm and 30 nm or between 5 nm and 20 nm and less than the depth of the blind holes 2a, in the semiconductor substrate 2 and vertically extending through the insulating dielectric layer 12, and (3) a dielectric layer 403 between the first and second electrodes 402 and 404 and at a sidewall and bottom of the second shallow trench 2g. The first electrode 402 of the decoupling capacitor 401 may include (1) a copper layer 156 electroplated in the first shallow trench 2f, wherein the copper layer 156 of the first electrode 402 may have a top surface coplanar with a top surface of the insulating dielectric layer 12, (2) an adhesion layer 154, such as a layer of titanium (Ti) or titanium nitride (TiN) having a thickness between 1 nm to 50 nm, on a sidewall and bottom of the first shallow trench 2f and at a sidewall and bottom of the copper layer 156 of the first electrode 402, and (3) a seed layer 155, such as a layer of copper having a thickness between 3 nm and 200 nm, between the adhesion layer 154 and copper layer 156 of the first electrode 402 and at a sidewall and bottom of the copper layer 156 of the first electrode 402. The dielectric layer 403 of the decoupling capacitor 401 may be a layer of tantalum oxide (Ta.sub.2O.sub.5), hafnium oxide (HfO.sub.2), zirconium oxide (ZrO.sub.2), titanium oxide (TiO.sub.2) or silicon nitride (Si.sub.3N.sub.4) having a thickness between 100 and 1,000 angstroms on a sidewall and bottom of the second shallow trench 2g. The second electrode 404 of the decoupling capacitor 401 may include (1) a copper layer 156 electroplated in the second shallow trench 2g, wherein the copper layer 156 of the second electrode 404 may have a top surface coplanar with the top surface of the insulating dielectric layer 12, (2) an adhesion layer 154, such as a layer of titanium (Ti) or titanium nitride (TiN) having a thickness between 1 nm to 50 nm, on the dielectric layer 403 of the decoupling capacitor 401, between the dielectric layer 403 of the decoupling capacitor 401 and the copper layer 156 of the second electrode 404 and at a sidewall and bottom of the copper layer 156 of the second electrode 404, and (4) a seed layer 155, such as a layer of copper having a thickness between 3 nm and 200 nm, between the adhesion layer 154 and copper layer 156 of the second electrode 404 and at a sidewall and bottom of the copper layer 156 of the second electrode 404.

(121) Accordingly, referring to FIGS. 3C and 3D, the decoupling capacitor 401 may be provided with the dielectric layer 403 between the first and second electrodes 402 and 404 thereof, wherein The first and second electrodes 402 and 404 of the decoupling capacitor 401 may have substantially the same depth between 5 and 30 μm or between 5 and 20 μm and less than the depth of the through silicon vias (TSVs) 157, wherein the depth of the through silicon vias (TSVs) 157 may range from 30 to 2,000 μm. It is noted that a first one of the first, second, third or fourth type of micro-bumps or micro-pads 34 may be formed on the copper layer 156 of a first one of the through silicon vias (TSVs) 157 and the first electrode 402 of the decoupling capacitor 401 beside the copper layer 156 of the first one of the through silicon vias (TSVs) 157 to couple the first one of the through silicon vias (TSVs) 157 to the first electrode 402 of the decoupling capacitor 401; a second one of the first, second, third or fourth type of micro-bumps or micro-pads 34 may be formed on the copper layer 156 of a second one of the through silicon vias (TSVs) 157 and the second electrode 404 of the decoupling capacitor 401 beside the copper layer 156 of the second one of the through silicon vias (TSVs) 157 to couple the second one of the through silicon vias (TSVs) 157 to the second electrode 404 of the decoupling capacitor 401. The first electrode 402 of the decoupling capacitor 401 is configured to electrically couple to the semiconductor substrate 2 and configured to electrically couple to a voltage Vss of ground reference via the first one of the first, second, third or fourth type of micro-bumps or micro-pads 34. Each of the through silicon vias (TSVs) 157 may be used as a vertical through via (VTV) 358 for a dedicated vertical path. For an element indicated by the same reference number shown in FIGS. 1A, 1C, 1E, 3C and 3D, the specification of the element as seen in FIGS. 3C and 3D may be referred to that of the element as illustrated in FIGS. 1A, 1C and 1E.

(122) For example, the decoupling capacitor 401 as illustrated in each of FIGS. 3A and 3C may have capacitance between 10 and 5,000 nF. The decoupling capacitor 401 as illustrated in each of FIGS. 3A and 3C may be formed (1) for the first case among any four of the vertical through vias (VTVs) 358 and in the semiconductor substrate 2 of the first or second type of vertical-through-via (VTV) connector 467 as seen in FIG. 1A or 1B, (2) for the second case among any four of the vertical through vias (VTVs) 358 and in the semiconductor substrate 2 of the first or second type of vertical-through-via (VTV) connector 467 as seen in FIG. 1C or 1D, or (3) for the third case among any four of the vertical through vias (VTVs) 358 and in the semiconductor substrate 2 of the first or second type of vertical-through-via (VTV) connector 467 as seen in FIG. 1E or 1F. Alternatively, the decoupling capacitor 401 as illustrated in each of FIGS. 3A and 3C may be formed (1) for the first case among any four of the vertical through vias (VTVs) 358, i.e., among any four of the through silicon vias (TSVs) 157, and in one of the semiconductor substrates 2 of the first or second type of vertical-through-via (VTV) connector 467 as seen in FIG. 2A or 2B, (2) for the second case among any four of the vertical through vias (VTVs) 358, i.e., among any four of the through silicon vias (TSVs) 157, and in one of the semiconductor substrates 2 of the first or second type of vertical-through-via (VTV) connector 467 as seen in FIG. 2C or 2D, or (3) for the third case among any four of the vertical through vias (VTVs) 358, i.e., among any four of the through silicon vias (TSVs) 157, and in one of the semiconductor substrates 2 of the first or second type of vertical-through-via (VTV) connector 467 as seen in FIG. 2E or 2F.

(123) 4. Third Alternative for First Type of Vertical-Through-Via (VTV) Connector for Through-Glass-Via Interconnect Elevator (TGVIE)

(124) FIG. 4A is a schematically cross-sectional view showing a first type of vertical-through-via (VTV) connector for a third alternative for the first case in accordance with an embodiment of the present application. FIG. 4B is a schematically cross-sectional view showing a first type of vertical-through-via (VTV) connector for a third alternative for the second case in accordance with an embodiment of the present application. FIG. 4C is a schematically cross-sectional view showing a first type of vertical-through-via (VTV) connector for a third alternative for the third case in accordance with an embodiment of the present application. In a third alternative, referring to each of FIGS. 4A-4C, a first type of vertical-through-via (VTV) connector 467 may include (1) a glass substrate 202 made of silicon oxide, (2) multiple through glass vias (TGVs) 259 each in the glass substrate 202 and vertically extending through the glass substrate 202, and (3) a glass wetting layer 708, such as a layer of silicon oxide having a thickness between 0.01 and 1 micrometers, at a sidewall of each of the through glass vias (TGVs) 259, around said each of the through glass vias (TGVs) 259 and between said each of the through glass vias (TGVs) 259 and the glass substrate 202. Each of the through glass vias (TGVs) 259 may include (1) a copper post 706 having a circular shape with a diameter or largest transverse dimension between 3 and 30 micrometers and a height between 30 and 100 micrometers in the glass substrate 202 and vertically extending through the glass substrate 202, wherein the glass wetting layer 708 may surround the copper post 706, and wherein the copper post 706 may have a top surface coplanar with a top surface of the glass substrate 202 and a bottom surface coplanar with a bottom surface of the glass substrate 202, and (2) a metal lining layer 707, such as a layer of a titanium-tungsten alloy, tungsten, titanium nitride or a high melting-point metal having a melting temperature greater than 1,100 or 1,500 degrees Celsius, having a thickness between 0.1 and 2 micrometers at a sidewall of the copper post 706, around the copper post 706 and between the copper post 706 and the glass wetting layer 708. Each of the through glass vias (TGVs) 259 may have a thickness between 30 and 100 micrometers to be used as a vertical through via (VTV) 358 for a dedicated vertical path.

(125) In the third alternative, referring to each of FIGS. 4A-4C, the first type of vertical-through-via (VTV) connector 467 may further include multiple fifth type of micro-bumps or micro-pads 34, i.e., metal bumps or pads, each on the top surface of the copper post 706 of one of the through glass vias (TGVs) 259. Each of the fifth type of micro bumps or micro-pads 34 may include (1) a coper layer 717 having a thickness between 3 and 10 micrometers on the top surface of the copper post 706 of one of the through glass vias (TGVs) 259, (2) a nickel layer 718 having a thickness between 1 and 5 micrometers on a top and sidewall of the copper layer 717, and (3) a solder layer 719, such as a tin-silver alloy or a tin-lead alloy, having a thickness between 1 and 20 micrometers on a top surface and side surface of the nickel layer 718.

(126) In the third alternative, referring to FIG. 4A for the first case, the arrangements for the vertical through vias (VTVs) 358 for the first type of vertical-through-via (VTV) connector 467 may be the same as those as illustrated in FIG. 1A for the first case for the first alternative; the arrangements for the fifth type of micro-bumps or micro-pads 34 for the first type of vertical-through-via (VTV) connector 467 may be the same as those for the first, second, third or fourth type of micro-bumps or micro-pads 34 as illustrated in FIG. 1A for the first case for the first alternative.

(127) In the third alternative, referring to FIG. 4B for the second case, the arrangements for the vertical through vias (VTVs) 358 for the first type of vertical-through-via (VTV) connector 467 may be the same as those as illustrated in FIG. 1C for the second case for the first alternative; the arrangements for the fifth type of micro-bumps or micro-pads 34 for the first type of vertical-through-via (VTV) connector 467 may be the same as those for the first, second, third or fourth type of micro-bumps or micro-pads 34 as illustrated in FIG. 1C for the second case for the first alternative.

(128) In the third alternative, referring to FIG. 4C for the third case, the arrangements for the vertical through vias (VTVs) 358 for the first type of vertical-through-via (VTV) connector 467 may be the same as those as illustrated in FIG. 1A for the third case for the first alternative; the arrangements for the fifth type of micro-bumps or micro-pads 34 for the first type of vertical-through-via (VTV) connector 467 may be the same as those for the first, second, third or fourth type of micro-bumps or micro-pads 34 as illustrated in FIG. 1A for the third case for the first alternative.

(129) Referring to each of FIGS. 4A-4C for the third alternative, the aspect ratio of the length to the width for the first type of vertical-through-via (VTV) connector 467 may be between 2 and 10, between 4 and 10 or between 2 and 40. The first type of vertical-through-via (VTV) connector 467 may be provided with passive elements, such as capacitors, but without any active device, i.e., transistor, therein.

(130) 5. Fourth Alternative for First Type of Vertical-Through-Via (VTV) Connector for Through-Glass-Via Interconnect Elevator (TGVIE)

(131) FIG. 5A is a schematically cross-sectional view showing a first type of vertical-through-via (VTV) connector for a fourth alternative for the first case in accordance with an embodiment of the present application. FIG. 5B is a schematically cross-sectional view showing a first type of vertical-through-via (VTV) connector for a fourth alternative for the second case in accordance with an embodiment of the present application. FIG. 5C is a schematically cross-sectional view showing a first type of vertical-through-via (VTV) connector for a fourth alternative for the third case in accordance with an embodiment of the present application. In a fourth alternative, referring to each of FIGS. 5A, 5B and 5C, a first type of vertical-through-via (VTV) connectors 467 may include (1) multiple glass substrates 202, an upper of which may have a bottom surface bonded onto a top surface of a lower one of which, (2) multiple through glass vias (TGVs) 259 in each of the glass substrates 202 and extending vertically through said each of the glass substrates 202, wherein each of the through glass vias (TGVs) 259 may have a thickness between 30 and 100 micrometers, and (3) a glass wetting layer 708, such as a layer of silicon oxide having a thickness between 0.01 and 1 micrometers, at a sidewall of each of the through glass vias (TGVs) 259 in each of the glass substrates 202, around said each of the through glass vias (TGVs) 259 and between said each of the through glass vias (TGVs) 259 and said each of the glass substrates 202. Each of the through glass vias (TGVs) 259 in each of the glass substrates 202 and vertically extending through said each of the glass substrates 202 may include (1) a copper post 706 having a circular shape with a diameter or largest transverse dimension between 3 and 30 micrometers and a height between 30 and 100 micrometers in said each of the glass substrates 202 and vertically extending through said each of the glass substrates 202, wherein the glass wetting layer 708 in said each of the glass substrates 202 may surround the copper post 706, and wherein the copper post 706 may have a top surface coplanar with a top surface of said each of the glass substrates 202 and a bottom surface coplanar with a bottom surface of said each of the glass substrates 202, and (2) a metal lining layer 707, such as a layer of a titanium-tungsten alloy, tungsten, titanium nitride or a high melting-point metal having a melting temperature greater than 1,100 or 1,500 degrees Celsius, having a thickness between 0.1 and 2 micrometers at a sidewall of the copper post 706, around the copper post 706 and between the copper post 706 and the glass wetting layer 708.

(132) In the fourth alternative, referring to each of FIGS. 5A, 5B and 5C, multiple of the through glass vias (TGVs) 259 may be stacked with each other or one another to form a vertical through via (VTV) 358 for a dedicated vertical path, wherein the copper post 706 of an upper one of the through glass vias (TGVs) 259 may have the bottom surface directly bonded to the top surface of the copper post 706 of a lower one of the through glass vias (TGVs) 259. Each of the vertical through vias (VTVs) 358 may include multiple of the through glass vias (TGVs) 259 stacked up to a total height between 100 and 2,000 micrometers, between 100 and 1,000 micrometers or between 100 and 500 micrometers.

(133) In the fourth alternative, referring to each of FIGS. 5A, 5B and 5C, the first type of vertical-through-via (VTV) connectors 467 may further include multiple micro-bump or micro-pad 34, which may be of the fifth type having the same specifications as the fifth type of micro-bumps or micro-pads 34 as illustrated in each of FIGS. 4A, 4B and 4C, each on the top surface of the copper post 706 of one of the vertical through vias (VTVs) 358.

(134) In the fourth alternative, referring to FIG. 5A for the first case, the arrangements for the vertical through vias (VTVs) 358 for the first type of vertical-through-via (VTV) connector 467 may be the same as those as illustrated in FIG. 1A for the first case for the first alternative; the arrangements for the fifth type of micro-bumps or micro-pads 34 for the first type of vertical-through-via (VTV) connector 467 may be the same as those for the first, second, third or fourth type of micro-bumps or micro-pads 34 as illustrated in FIG. 1A for the first case for the first alternative.

(135) In the fourth alternative, referring to FIG. 5B for the second case, the arrangements for the vertical through vias (VTVs) 358 for the first type of vertical-through-via (VTV) connector 467 may be the same as those as illustrated in FIG. 1C for the second case for the first alternative; the arrangements for the fifth type of micro-bumps or micro-pads 34 for the first type of vertical-through-via (VTV) connector 467 may be the same as those for the first, second, third or fourth type of micro-bumps or micro-pads 34 as illustrated in FIG. 1C for the second case for the first alternative.

(136) In the fourth alternative, referring to FIG. 5C for the third case, the arrangements for the vertical through vias (VTVs) 358 for the first type of vertical-through-via (VTV) connector 467 may be the same as those as illustrated in FIG. 1A for the third case for the first alternative; the arrangements for the fifth type of micro-bumps or micro-pads 34 for the first type of vertical-through-via (VTV) connector 467 may be the same as those for the first, second, third or fourth type of micro-bumps or micro-pads 34 as illustrated in FIG. 1A for the third case for the first alternative.

(137) Referring to each of FIGS. 5A-5C for the fourth alternative, the aspect ratio of the length to the width for the first type of vertical-through-via (VTV) connector 467 may be between 2 and 10, between 4 and 10 or between 2 and 40. The first type of vertical-through-via (VTV) connector 467 may be provided with passive elements, such as capacitors, but without any active device, i.e., transistor, therein.

(138) 6. Fifth Alternative for First Type of Vertical-Through-Via (VTV) Connector for Through-Polymer-Via Interconnect Elevator (TPVIE)

(139) FIG. 6 is a schematically cross-sectional view showing a first type of vertical-through-via (VTV) connector for a fifth alternative in accordance with an embodiment of the present application. In a fifth alternative, referring to FIG. 6, a first type of vertical-through-via (VTV) connectors 467 may include (1) an epoxy-based polymer layer 317, (2) multiple metal pads 336 at a bottom of the epoxy-based polymer layer 317, wherein each of the metal pads 336 may be made of a nickel layer having a thickness between 1 and 5 micrometers, having a bottom surface coplanar with a bottom surface of the epoxy-based polymer layer 317 and being aligned with one of openings in the epoxy-based polymer layer 317 and at a bottom of said one of the openings in the epoxy-based polymer layer 317, (3) multiple copper posts 318 each in one of the openings in the epoxy-based polymer layer 317 and on a top surface of one of the metal pads 336, wherein each of the copper posts 318 may have a top surface coplanar with a top surface of the epoxy-based polymer layer 317, and (4) multiple sixth type of micro-bumps or micro-pads 34 each on the top surface of one of the copper posts 318, wherein each of the sixth type of micro-bumps or micro-pads 34 may include a nickel layer 320 having a thickness between 1 and 5 micrometers on the top surface of said one of the copper posts 318 and a solder ball 321, such as a tin-silver alloy, having a thickness between 1 and 20 micrometers on a top and side surface of the nickel layer 320. Each of the copper posts 318 and underlying one of the metal pads 336 may be used as a vertical through via (VTV) 358, i.e., through polymer via (TPV), for a dedicated vertical path.

(140) Referring to each of FIG. 6 for the fifth alternative, the aspect ratio of the length to the width for the first type of vertical-through-via (VTV) connector 467 may be between 2 and 10, between 4 and 10 or between 2 and 40. The first type of vertical-through-via (VTV) connector 467 may be provided with passive elements, such as capacitors, but without any active device, i.e., transistor, therein.

(141) Specification for Programmable Logic Blocks

(142) FIG. 7 is a schematic view showing a block diagram of a programmable logic cell in accordance with an embodiment of the present application. Referring to FIG. 7, a programmable logic block (LB) or element may include one or a plurality of programmable logic cells (LC) 2014 each configured to perform logic operation on its input data set at its input points. Each of the programmable logic cells (LC) 2014 may include multiple memory cells 490, i.e., configuration-programming-memory (CPM) cells, each configured to save or store one of resulting values of a look-up table (LUT) 210 and a selection circuit 211, such as multiplexer (MUXER), having a first set of two input points arranged in parallel for a first input data set, e.g., A0 and A1, and a second set of four input points arranged in parallel for a second input data set, e.g., D0, D1, D2 and D3, each associated with one of the resulting values or programming codes of the look-up table (LUT) 210. The selection circuit 211 is configured to select, in accordance with its first input data set associated with the input data set of said each of the programmable logic cells (LC) 2014, a data input, e.g., D0, D1, D2 or D3, from its second input data set as a data output Dout at its output point acting as a data output of said each of the programmable logic cells (LC) 2014 at an output point of said each of the programmable logic cells (LC) 2014.

(143) Referring to FIG. 7, the selection circuit 211 may have the second input data set, e.g., D0, D1, D2 and D3, each associated with a data output, i.e., configuration-programming-memory (CPM) data, of one of the memory cells 490, i.e., configuration-programming-memory (CPM) cells. For each of the programmable logic cells (LC) 2014, each of the resulting values or programing codes of its look-up table (LUT) 210 stored in one of its memory cells 490 that may be of a first type, i.e., volatile memory cell such as static random-access memory (SRAM) cell, may be associated with data saved or stored in a non-volatile memory cell, such as ferroelectric random-access-memory (FRAM) cell, magnetoresistive random access memory (MRAM) cell, resistive random access memory (RRAM) cell, anti-fuse or e-fuse. Alternatively, for each of the programmable logic cells (LC) 2014, each of its memory cells 490 may be of a second type, i.e., non-volatile memory cell composed of one or more magnetoresistive random access memory (MRAM) cells, one or more resistive random access memory (RRAM) cells, one or more anti-fuses, one or more e-fuses, or a floating gate of a metal-oxide-semiconductor (MOS) transistor.

(144) Referring to FIG. 7, each of the programmable logic cells (LC) 2014 may have the memory cells 490, i.e., configuration-programming-memory (CPM) cells, configured to be programed to store or save the resulting values or programing codes of the look-up table (LUT) 210 to perform the logic operation, such as AND operation, NAND operation, OR operation, NOR operation, EXOR operation or other Boolean operation, or an operation combining two or more of the above operations. For this case, each of the programmable logic cells (LC) 2014 may perform the logic operation on its input data set, e.g., A0 and A1, at its input points as a data output Dout at its output point. For more elaboration, each of the programmable logic cells (LC) 2014 may include the number 2.sup.n of memory cells 490, i.e., configuration-programming-memory (CPM) cells, each configured to save or store one of resulting values of the look-up table (LUT) 210 and the selection circuit 211 having a first set of the number n of input points arranged in parallel for a first input data set, e.g., A0-A1, and a second set of the number 2.sup.n of input points arranged in parallel for a second input data set, e.g., D0-D3, each associated with one of the resulting values or programming codes of the look-up table (LUT) 210, wherein the number n may range from 2 to 8, such as 2 for this case. The selection circuit 211 is configured to select, in accordance with its first input data set associated with the input data set of said each of the programmable logic cells (LC) 2014, a data input, e.g., one of D0-D3, from its second input data set as a data output Dout at its output point acting as a data output of said each of the programmable logic cells (LC) 2014 at an output point of said each of the programmable logic cells (LC) 2014.

(145) Specification for Programmable or Configurable Switch Cell

(146) FIG. 8 is a circuit diagram illustrating programmable interconnects controlled by a programmable switch cell in accordance with an embodiment of the present application. Referring to FIG. 8, a cross-point switch may be provided for a programmable switch cell 379, i.e., configurable switch cell, including four selection circuits 211 at its top, bottom, left and right sides respectively, each having a multiplexer 213 and a pass/no-pass switch or switch buffer 292 coupling to the multiplexer 213 thereof, and four sets of memory cells 362 each configured to save or store programming codes to control the multiplexer 213 and pass/no-pass switch or switch buffer 292 of one of its four selection circuits 211. For the programmable switch cell 379, the multiplexer 213 of each of its four selection circuits 211 may be configured to select, in accordance with the first input data set thereof at the first set of input points thereof each associated with one of the programming codes saved or stored in its memory cells 362, a data input from the second input data set thereof at the second set of input points thereof as the data output thereof. The pass/no-pass switch 292 of each of its four selection circuits 211 is configured to control, in accordance with a first data input thereof associated with another of the programming codes saved or stored in its memory cells 362, coupling between the input point thereof for a second data input thereof associated with the data output of the multiplexer 213 of said each of its four selection circuits 211 and the output point thereof for a data output thereof and amplify the second data input thereof as the data output thereof to act as a data output of said each of its four selection circuits 211. Each of the second set of three input points of the multiplexer 213 of one of its four selection circuits 211 may couple to one of the second set of three input points of the multiplexer 213 of each of another two of its four selection circuits 211 and to one of the four programmable interconnects 361 coupling to the output point of the other of its four selection circuits 211. Each of the four programmable interconnects 361 may couple to the output point of one of its four selection circuits 211 and one of the second set of three input points of the multiplexer 213 of each of the other three of its four selection circuits 211. Thereby, for each of the four selection circuits 211 of the programmable switch cell 379, its multiplexer 213 may select, in accordance with the first input data set thereof at the first set of input points thereof, a data input from the second input data set thereof at the second set of three input points thereof coupling to respective three of four nodes N23-N26 coupling to respective three of four programmable interconnects 361 extending in four different directions respectively, and its second type of pass/no-pass switch 292 is configured to generate the data output of said each of the four selection circuits 211 at the other of the four nodes N23-N26 coupling to the other of the four programmable interconnects 361.

(147) For example, referring to FIG. 8, for the top one of the four selection circuits 211 of the programmable switch cell 379, its multiplexer 213 may select, in accordance with the first input data set thereof at the first set of input points thereof each associated with one of the programming codes saved or stored in the memory cells 362 of the programmable switch cell 379, a data input from the second input data set thereof at the second set of three input points thereof coupling to the respective three nodes N24-N26 coupling to the respective three programmable interconnects 361 extending in left, down and right directions respectively, and its pass/no-pass switch 292 is configured, in accordance with another of the programming codes saved or stored in the memory cells 362 of the programmable switch cell 379, to or not to generate the data output of the top one of the four selection circuits 211 of the programmable switch cell 379 at the node N23 coupling to the programmable interconnect 361 extending in an up direction. Thereby, data from one of the four programmable interconnects 361 may be switched by the programmable switch cell 379 to be passed to another one, two or three of the four programmable interconnects 361.

(148) Referring to FIG. 8, for the programmable switch cell 379, each of the programming codes saved or stored in one of the memory cells 362 that may be of a first type, i.e., volatile memory cell such as static random-access memory (SRAM) cell, may be associated with data saved or stored in a non-volatile memory cell, such as ferroelectric random-access-memory (FRAM) cell, magnetoresistive random access memory (MRAM) cell, resistive random access memory (RRAM) cell, anti-fuse or e-fuse. Alternatively, for the programmable switch cell 379, each of its memory cells 362 may be of a second type, i.e., non-volatile memory cell composed of one or more magnetoresistive random access memory (MRAM) cells, one or more resistive random access memory (RRAM) cells, one or more anti-fuses, one or more e-fuses, or a floating gate of a metal-oxide-semiconductor (MOS) transistor.

(149) Specification for Standard Commodity Field-Programmable-Gate-Array (FPGA) Integrated-Circuit (IC) Chip

(150) FIG. 9 is a schematically top view showing a block diagram of a standard commodity FPGA IC chip in accordance with an embodiment of the present application. Referring to FIG. 9, the standard commodity FPGA IC chip 200 may include (1) a plurality of programmable logic blocks 201 arranged in an array in a central region thereof, wherein each of the programmable logic blocks 201 may be arranged with multiple programmable logic cells (LC) 2014 as illustrated in FIG. 7 coupling to one another, (2) a plurality of programmable switch cells 379 as illustrated in FIG. 8 arranged around each of the programmable logic blocks (LB) 201, (3) multiple intra-chip interconnects 502 each extending over spaces between neighboring two of the programmable logic blocks 201, wherein the intra-chip interconnects 502 may include the programmable interconnects 361 as seen in FIG. 8 configured to be programmed for interconnection by its memory cells 362 and the non-programmable interconnects 364 as illustrated in FIG. 8 configured not to be programmable for interconnection, and (4) multiple I/O ports 377 having the number ranging from 2 to 64 for example, such as I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4 for this case. Each of the I/O ports 377 may include (1) the small I/O circuits 203 having the number ranging from 4 to 256, such as 64 for this case, arranged in parallel for data transmission with bit width ranging from 4 to 256, such as 64 for this case, and (2) the I/O pads 372 having the number ranging from 4 to 256, such as 64 for this case, arranged in parallel and vertically over the small I/O circuits 203 respectively. Each of its small input/output (I/O) circuits 203 may include a small driver configured to drive data to its external circuits in the same chip package and a small receiver configured to receive data from its external circuits in the same chip package, wherein each of its small input/output (I/O) circuits 203 may have an output capacitance or driving capability or loading, for example, between 0.05 pF and 2 pF or between 0.05 pF and 1 pF, or smaller than 2 pF or 1 pF, and an input capacitance between 0.15 pF and 4 pF or between 0.15 pF and 2 pF, or greater than 0.15 pF; alternatively, each of its small input/output (I/O) circuits 203 may have an I/O power efficiency smaller than 0.5 pico-Joules per bit, per switch or per voltage swing, or between 0.01 and 0.5 pico-Joules per bit, per switch or per voltage swing.

(151) Referring to FIG. 9, in a first clock cycle, for one of the small input/output (I/O) circuits 203 of the standard commodity FPGA IC chip 200, its small driver may be enabled by a data input at a first input point of its small driver and its small receiver may be inhibited by a data input at a first input point of its small receiver. Thereby, its small driver may amplify a data input at a second input point of its small driver, associated with the resulting value or programming code from one of the memory cells 490 of one of the programmable logic cells 2014 of the standard commodity FPGA IC chip 200 or one of the memory cells 362 of one of the programmable switch cells 379 of the standard commodity FPGA IC chip 200, as a data output of its small driver at an output point of its small driver to be transmitted to one of the I/O pads 372 vertically over said one of the small input/output (I/O) circuits 203 for external connection to the external circuits of the standard commodity FPGA IC chip 200, such as non-volatile memory (NVM) integrated-circuit (IC) chip.

(152) In a second clock cycle, for said one of the small input/output (I/O) circuits 203 of the standard commodity FPGA IC chip 200, its small driver may be disabled by a data input at the first input point of its small driver and its small receiver may be activated by a data input at the first input point of its small receiver. Thereby, its small receiver may amplify a data input, i.e., a resulting value or programming code, at a second input point of its small receiver associated with data passed from the external circuits of the standard commodity FPGA IC chip 200, such as non-volatile memory (NVM) integrated-circuit (IC) chip, through said one of the I/O pads 372 as an data output of its small receiver at an output point of its small receiver to be passed to and stored in one of the memory cells 490 of one of the programmable logic cells 2014 of the standard commodity FPGA IC chip 200 or one of the memory cells 362 of one of the programmable switch cells 379 of the standard commodity FPGA IC chip 200.

(153) In a third clock cycle, for said one of the small input/output (I/O) circuits 203 of the standard commodity FPGA IC chip 200, its small driver may be enabled by a data input at the first input point of its small driver and its small receiver may be inhibited by a data input at the first input point of its small receiver. Thereby, its small driver may amplify a data input at the second input point of its small driver, associated with the data output of one of the programmable logic cells 2014 of the standard commodity FPGA IC chip 200 as illustrated in FIG. 7 for example through first one or more of the programmable interconnects 361 of the standard commodity FPGA IC chip 200 and/or one or more of the programmable switch cells 379 of the standard commodity FPGA IC chip 200 each coupled between two of said first one or more of the programmable interconnects 361, as a data output of its small driver at the output point of its small driver to be transmitted to said one of the I/O pads 372 vertically over said one of the small input/output (I/O) circuits 203 for external connection to circuits outside the standard commodity FPGA IC chip 200, such as non-volatile memory (NVM) integrated-circuit (IC) chip.

(154) In a fourth clock cycle, for said one of the small input/output (I/O) circuits 203 of the standard commodity FPGA IC chip 200, its small driver may be disabled by a data input at the first input point of its small driver and its small receiver may be activated by a data input at the first input point of its small receiver. Thereby, its small receiver may amplify a data input at the second input point of its small receiver transmitted from circuits, such as non-volatile memory (NVM) integrated-circuit (IC) chip, outside the standard commodity FPGA IC chip 200 through said one of the I/O pads 372 as a data output of its small receiver at the output point of its small driver associated with a data input of the input data set of one of the programmable logic cells 2014 of the standard commodity FPGA IC chip 200 as illustrated in FIG. 7 for example through second one or more of the programmable interconnects 361 of the standard commodity FPGA IC chip 200 and/or one or more of the programmable switch cells 379 of the standard commodity FPGA IC chip 200 each coupled between two of said second one or more of the programmable interconnects 361.

(155) Referring to FIG. 9, the standard commodity FPGA IC chip 200 may further include a chip-enable (CE) pad 209 configured for enabling or disabling the standard commodity FPGA IC chip 200. For example, when the chip-enable (CE) pad 209 is at a logic level of “0”, the standard commodity FPGA IC chip 200 may be enabled to process data and/or operate with circuits outside of the standard commodity FPGA IC chip 200; when the chip-enable (CE) pad 209 is at a logic level of “1”, the standard commodity FPGA IC chip 200 may be disabled not to process data and/or operate with circuits outside of the standard commodity FPGA IC chip 200.

(156) Referring to FIG. 9, the standard commodity FPGA IC chip 200 may further include multiple input selection (IS) pads 231, e.g., IS1, IS2, IS3 and IS4 pads, each configured to receive a data input associated with the data input at the first input point of the small receiver of each of the small I/O circuits 203 of one of its I/O ports 377, e.g., I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4. For more elaboration, for the standard commodity FPGA IC chip 200, its IS1 pad 231 may receive a data input associated with the data input at the first input point of the small receiver of each of the small I/O circuits 203 of its I/O Port 1; its IS2 pad 231 may receive a data input associated with the data input at the first input point of the small receiver of each of the small I/O circuits 203 of its I/O Port 2; its IS3 pad 231 may receive a data input associated with the data input at the first input point of the small receiver of each of the small I/O circuits 203 of its I/O Port 3; and its IS4 pad may receive a data input associated with the data input at the first input point of the small receiver of each of the small I/O circuits 203 of its I/O Port 4. The standard commodity FPGA IC chip 200 may select, in accordance with logic levels at the input selection (IS) pads 231, e.g., IS1, IS2, IS3 and IS4 pads, one or more from its I/O ports 377, e.g., I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4, to pass data for its input operation. For each of the small I/O circuits 203 of each of the one or more I/O ports 377 selected in accordance with the logic levels at the input selection (IS) pads 231, its small receiver may be activated by the data input at the first input point of its small receiver transmitted from circuits outside of the standard commodity FPGA IC chip 200 through one of the input selection (IS) pads 231 to amplify or pass the data input at the second input point of its small receiver, transmitted from circuits outside the standard commodity FPGA IC chip 200 through one of the I/O pads 372 of said each of the one or more I/O ports 377 selected in accordance with the logic levels at the input selection (IS) pads 231, as the data output of its small receiver associated with a data input of the input data set of one of the programmable logic cells 2014 as seen in FIG. 7 of the standard commodity FPGA IC chip 200 through one or more of the programmable interconnects 361 as seen in FIG. 8 of the standard commodity FPGA IC chip 200, for example. For each of the small I/O circuits 203 of each of the I/O ports 377, not selected in accordance with in accordance with the logic levels at the input selection (IS) pads 231, of the standard commodity FPGA IC chip 200, its small receiver 375 may be inhibited by the data input at the first input point of its small receiver associated with the logic level at one of the input selection (IS) pads 231 of the standard commodity FPGA IC chip 200.

(157) For example, referring to FIG. 9, provided that the standard commodity FPGA IC chip 200 may have (1) the chip-enable (CE) pad 209 at a logic level of “0”, (2) the IS1 pad 231 at a logic level of “1”, (3) the IS2 pad 231 at a logic level of “0”, (4) the IS3 pad 231 at a logic level of “0” and (5) the IS4 pad 231 at a logic level of “0”, the standard commodity FPGA IC chip 200 may be enabled in accordance with the logic level at its chip-enable (CE) pad 209 and may select, in accordance with the logic levels at its IS1, IS2, IS3 and IS4 pads 231, one or more I/O port, e.g., I/O Port 1, from its I/O ports 377, i.e., I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4, to pass data for the input operation. For each of the small I/O circuits 203 of the selected I/O port 377, i.e., I/O Port 1, of the standard commodity FPGA IC chip 200, its small receiver may be activated by the data input at the first input point of its small receiver associated with the logic level at the IS1 pad 231 of the standard commodity FPGA IC chip 200. For each of the small I/O circuits 203 of each of the unselected I/O ports, i.e., I/O Port 2, I/O Port 3 and I/O Port 4, of the standard commodity FPGA IC chip 200, its small receiver may be inhibited by the data input at the first input point of its small receiver associated with the logic level at one of the IS2, IS3 and IS4 pads 231 of the standard commodity FPGA IC chip 200.

(158) For example, referring to FIG. 9, provided that the standard commodity FPGA IC chip 200 may have (1) the chip-enable (CE) pad 209 at a logic level of “0”, (2) the IS1 pad 231 at a logic level of “1”, (3) the IS2 pad 231 at a logic level of “1”, (4) the IS3 pad 231 at a logic level of “1” and (5) the IS4 pad 231 at a logic level of “1”, the standard commodity FPGA IC chip 200 may be enabled in accordance with the logic level at its chip-enable (CE) pad 209 and may select, in accordance with the logic levels at its IS1, IS2, IS3 and IS4 pads 231, all from its I/O ports 377, i.e., I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4, to pass data for the input operation at the same clock cycle. For each of the small I/O circuits 203 of each of the selected I/O ports 377, i.e., I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4, of the standard commodity FPGA IC chip 200, its small receiver may be activated by the data input at the first input point of its small receiver associated with the logic level at one of the IS1, IS2, IS3 and IS4 pads 231 of the standard commodity FPGA IC chip 200.

(159) Referring to FIG. 9, the standard commodity FPGA IC chip 200 may include multiple output selection (OS) pads 232, e.g., OS1, OS2, OS3 and OS4 pads, each configured to receive a data input associated with the data input at the first input point of the small driver of each of the small I/O circuits 203 of one of its I/O ports 377, e.g., I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4. For more elaboration, for the standard commodity FPGA IC chip 200, its OS1 pad 232 may receive a data input associated with the data input at the first input point of the small driver of each of the small I/O circuits 203 of its I/O Port 1; its 052 pad 232 may receive a data input associated with the data input at the first input point of the small driver of each of the small I/O circuits 203 of its I/O Port 2; its 053 pad 232 may receive a data input associated with the data input at the first input point of the small driver of each of the small I/O circuits 203 of its I/O Port 3; its 054 pad 232 may receive a data input associated with the data input at the first input point of the small driver of each of the small I/O circuits 203 of its I/O Port 4. The standard commodity FPGA IC chip 200 may select, in accordance with logic levels at the output selection (OS) pads 232, e.g., OS1, OS2, OS3 and OS4 pads, one or more from its I/O ports 377, e.g., I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4, to pass data for its output operation. For each of the small I/O circuits 203 of each of the one or more I/O ports 377 selected in accordance with the logic levels at the output selection (OS) pads 232, its small driver may be enabled by the data input at the first input point of its small driver transmitted from circuits outside of the standard commodity FPGA IC chip 200 through one of the output selection (OS) pads 232 to amplify or pass the data input at the second input point of its small driver, associated with the data output of one of the programmable logic cells 2014 as seen in FIG. 7 of the standard commodity FPGA IC chip 200 through one or more of the programmable interconnects 361 as seen in FIG. 8 of the standard commodity FPGA IC chip 200, as the data output of its small driver to be transmitted to circuits outside the standard commodity FPGA IC chip 200 through one of the I/O pads 372 of said each of the one or more I/O ports 377 selected in accordance with the logic levels at the output selection (OS) pads 232, for example. For each of the small I/O circuits 203 of each of the I/O ports 377, not selected in accordance with in accordance with the logic levels at the output selection (OS) pads 232, of the standard commodity FPGA IC chip 200, its small driver may be disabled by the data input at the first input point of its small driver associated with the logic level at one of the output selection (OS) pads 232 of the standard commodity FPGA IC chip 200.

(160) For example, referring to FIG. 9, provided that the standard commodity FPGA IC chip 200 may have (1) the chip-enable (CE) pad 209 at a logic level of “0”, (2) the OS1 pad 232 at a logic level of “0”, (3) the OS2 pad 232 at a logic level of “1”, (4) the OS3 pad 232 at a logic level of “1” and (5) the OS4 pad 232 at a logic level of “1”, the standard commodity FPGA IC chip 200 may be enabled in accordance with the logic level at its chip-enable (CE) pad 209 and may select, in accordance with the logic levels at its OS1, OS2, OS3 and OS4 pads 232, one or more I/O port, e.g., I/O Port 1, from its I/O ports 377, i.e., I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4, to pass data for the output operation. For each of the small I/O circuits 203 of the selected I/O port 377, i.e., I/O Port 1, of the standard commodity FPGA IC chip 200, its small driver may be enabled by the data input at the first input point of its small driver associated with the logic level at the OS1 pad 232 of the standard commodity FPGA IC chip 200. For each of the small I/O circuits 203 of each of the unselected I/O ports, i.e., I/O Port 2, I/O Port 3 and I/O Port 4, of the standard commodity FPGA IC chip 200, its small driver may be disabled by the data input at the first input point of its small driver associated respectively with the logic level at one of the OS2, OS3 and OS4 pads 232 of the standard commodity FPGA IC chip 200.

(161) For example, referring to FIG. 9, provided that the standard commodity FPGA IC chip 200 may have (1) the chip-enable (CE) pad 209 at a logic level of “0”, (2) the OS1 pad 232 at a logic level of “0”, (3) the OS2 pad 232 at a logic level of “0”, (4) the OS3 pad 232 at a logic level of “0” and (5) the OS4 pad 232 at a logic level of “0”, the standard commodity FPGA IC chip 200 may be enabled in accordance with the logic level at its chip-enable (CE) pad 209 and may select, in accordance with the logic levels at its OS1, OS2, OS3 and OS4 pads 232, all from its I/O ports 377, i.e., I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4, to pass data for the output operation at the same clock cycle. For each of the small I/O circuits 203 of each of the selected I/O ports 377, i.e., I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4, of the standard commodity FPGA IC chip 200, its small driver may be enabled by the data input at the first input point of its small driver associated with the logic level at one of the OS1, OS2, OS3 and OS4 pads 232 of the standard commodity FPGA IC chip 200.

(162) Thereby, referring to FIG. 9, in a clock cycle, for the standard commodity FPGA IC chip 200, one or more of its I/O ports 377, i.e., I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4, may be selected, in accordance with the logic levels at its IS1, IS2, IS3 and IS4 pads 231, to pass data for its input operation, while another one or more of its I/O ports 377, i.e., I/O Port 1, I/O Port 2, I/O Port 3 and I/O Port 4, may be selected, in accordance with the logic levels at its OS1, OS2, OS3 and OS4 pads 232, to pass data for its output operation. Its input selection (IS) pads 231 and output selection (OS) pads 232 may be provided as I/O-port selection pads.

(163) Referring to FIG. 9, the standard commodity FPGA IC chip 200 may further include (1) multiple power pads 205 for applying the voltage Vcc of power supply to its memory cells 490 for the look-up tables (LUT) 210 of its programmable logic cells (LC) 2014 as illustrated in FIG. 7, the selection circuits 211 of its programmable logic cells (LC) 2014, the memory cells 362 of its programmable switch cells 379 as illustrated in FIG. 8, the selection circuits 211 of its programmable switch cells 379 and/or the small drivers and receivers of its small I/O circuits 203 through one or more of its non-programmable interconnects 364, wherein the voltage Vcc of power supply may be between 0.2V and 2.5V, between 0.2V and 2V, between 0.2V and 1.5V, between 0.1V and 1V, or between 0.2V and 1V, or, smaller or lower than or equal to 2.5V, 2V, 1.8V, 1.5V or 1V, and (2) multiple ground pads 206 for providing the voltage Vss of ground reference to its memory cells 490 for the look-up tables (LUT) 210 of its programmable logic cells (LC) 2014 as illustrated in FIG. 7, the selection circuits 211 of its programmable logic cells (LC) 2014, the memory cells 362 of its programmable switch cells 379 as illustrated in FIG. 8, the selection circuits 211 of its programmable switch cells 379 and/or the small drivers 374 and receivers 375 of its small I/O circuits 203 through one or more of its non-programmable interconnects 364.

(164) Referring to FIG. 9, the standard commodity FPGA IC chip 200 may further include a clock pad (CLK) 229 configured to receive a clock signal from circuits outside of the standard commodity FPGA IC chip 200 and multiple control pads (CP) 378 configured to receive control commands to control the standard commodity FPGA IC chip 200.

(165) Referring to FIG. 9, for the standard commodity FPGA IC chip 200, its programmable logic cells (LC) 2014 as seen in FIG. 7 may be reconfigurable for artificial-intelligence (AI) application. For example, in a clock cycle, one of the programmable logic cells (LC) 2014 of the standard commodity FPGA IC chip 200 may have the memory cells 490 to be programmed to perform OR operation; however, after one or more events happens, in another clock cycle said one of its programmable logic cells (LC) 2014 of the standard commodity FPGA IC chip 200 may have the memory cells 490 to be programmed to perform NAND operation for better AI performance.

(166) Referring to FIG. 9, the standard commodity FPGA IC chip 200 may include a cryptography block or circuit configured to decrypt, in accordance with a password or key stored or saved in a non-volatile memory cell of its cryptography block or circuit, which may be composed of one or more magnetoresistive random access memory (MRAM) cells, one or more resistive random access memory (RRAM) cells, one or more anti-fuses, one or more e-fuses, or a floating gate of a metal-oxide-semiconductor (MOS) transistor, encrypted data from a memory integrated-circuit (IC) chip as decrypted data to be passed to the memory cells 490 for the look-up tables (LUT) 210 of its programmable logic cells (LC) 2014 or the memory cells 362 of its programmable switch cells 379 and to encrypt, in accordance with the password or key, data from the memory cells 490 for the look-up tables (LUT) 210 of its programmable logic cells (LC) 2014 or the memory cells 362 of its programmable switch cells 379 as encrypted data to be passed to the memory integrated-circuit (IC) chip.

(167) Referring to FIG. 9, the standard commodity FPGA IC chip 200 may include a plurality of large input/output (I/O) circuits each having a large driver configured to drive data to its external circuits in a different chip package and a large receiver configured to receive data from its external circuits in a different chip package, wherein each of its large input/output (I/O) circuits may have an output capacitance or driving capability or loading, for example, between 2 pF and 100 pF, between 2 pF and 50 pF, between 2 pF and 30 pF, between 2 pF and 20 pF, between 2 pF and 15 pF, between 2 pF and 10 pF, or between 2 pF and 5 pF, or greater than 2 pF, 5 pF, 10 pF, 15 pF or 20 pF, and an input capacitance between 0.15 pF and 4 pF or between 0.15 pF and 2 pF, or greater than 0.15 pF; alternatively, each of its large input/output (I/O) circuits may have an I/O power efficiency greater than 3, 5 or 10 pico-Joules per bit, per switch or per voltage swing.

(168) Specification for Dedicated Programmable Interconnection (DPI) Integrated-Circuit (IC) Chip

(169) FIG. 10 is a schematically top view showing a block diagram of a dedicated programmable interconnection (DPI) integrated-circuit (IC) chip in accordance with an embodiment of the present application. Referring to FIG. 10, a dedicated programmable interconnection (DPI) integrated-circuit (IC) chip 410 may include (1) multiple memory-array blocks 423 arranged in an array in a central region thereof, (2) multiple groups of programmable switch cells 379 as illustrated in FIG. 8, each group of which is arranged in one or more rings around one of the memory-array blocks 423, and (3) multiple small input/output (I/O) circuits 203 each having a small receiver configured to generate a data output associated with a data input at one of the nodes N23-N26 of one of its programmable switch cells 379 as illustrated in FIG. 8 through one or more of its programmable interconnects 361 and a small driver configured to receive a data input associated with a data output at one of the nodes N23-N26 of another of its programmable switch cells 379 as illustrated in FIG. 8 through another one or more of its programmable interconnects 361, wherein each of its small input/output (I/O) circuits 203 may include a small driver configured to drive data to its external circuits in the same chip package and a small receiver configured to receive data from its external circuits in the same chip package, and each of its small input/output (I/O) circuits 203 may have an output capacitance or driving capability or loading, for example, between 0.05 pF and 2 pF or between 0.05 pF and 1 pF, or smaller than 2 pF or 1 pF, and an input capacitance between 0.15 pF and 4 pF or between 0.15 pF and 2 pF, or greater than 0.15 pF; alternatively, each of its small input/output (I/O) circuits 203 may have an I/O power efficiency smaller than 0.5 pico-Joules per bit, per switch or per voltage swing, or between 0.01 and 0.5 pico-Joules per bit, per switch or per voltage swing.

(170) Referring to FIG. 10, for the DPIIC chip 410, each of its programmable switch cells 379 as seen in FIG. 8 may include the memory cells 362 in one of its four memory-array blocks 423 arranged in an array and the selection circuits 211 close to said one of its memory-array blocks 423, wherein each of the selection circuits 211 of said each of its programmable switch cells 379 may have the first set of input points for multiple data inputs of the first input data set of said each of its selection circuits 211 each associated with a data output, i.e., configuration-programming-memory (CPM) data, of one of the memory cells 362, i.e., configuration-programming-memory (CPM) cells, of said each of its programmable switch cells 379.

(171) Referring to FIG. 10, the DPIIC chip 410 may include the I/O pads 372 each vertically over one of its small input/output (I/O) circuits 203. For one of the small input/output (I/O) circuits 203 of the DPIIC chip 410, in a first clock cycle, data from one of the nodes N23-N26 of one of the programmable switch cells 379 of the DPIIC chip 410 as illustrated in FIG. 8 may be associated with the data input of its small driver through one or more of the programmable interconnects 361 programmed by a first group of the programmable switch cells 379 of the DPIIC chip 410 and then its small driver may amplify or pass the data input of its small driver as a data output of its small driver to be transmitted to one of the I/O pads 372 of the DPIIC chip 410 vertically over said one of the small input/output (I/O) circuits 203 of the DPIIC chip 410 for external connection to circuits outside the DPIIC chip 410. In a second clock cycle, data from circuits outside the DPIIC chip 410 may be associated with a data input of its small receiver through said one of the I/O pads 372 of the DPIIC chip 410, and then its small receiver may amplify or pass the data input of its small receiver as a data output of its small receiver to be passed to one of the nodes N23-N26 of another of the programmable switch cells 379 of the DPIIC chip 410 as illustrated in FIG. 8 through another one or more of the programmable interconnects 361 programmed by a second group of the programmable switch cells 379 of the DPIIC chip 410.

(172) Referring to FIG. 10, the DPIIC chip 410 may further include (1) multiple power pads 205 for applying the voltage Vcc of power supply to the memory cells 362 of its programmable switch cells 379 as illustrated in FIG. 8 and/or the selection circuits 211 of its programmable switch cells 379, wherein the voltage Vcc of power supply may be between 0.2V and 2.5V, between 0.2V and 2V, between 0.2V and 1.5V, between 0.1V and 1V, or between 0.2V and 1V, or, smaller or lower than or equal to 2.5V, 2V, 1.8V, 1.5V or 1V, and (2) multiple ground pads 206 for providing the voltage Vss of ground reference to the memory cells 362 of its programmable switch cells 379 as illustrated in FIG. 8 and/or the selection circuits 211 of its programmable switch cells 379.

(173) Referring to FIG. 10, the DPIIC chip 410 may further include multiple SRAM cells used as cache memory for data latch or storage and a sense amplifier configured for reading, amplifying or detecting data from its SRAM cells acting as the cache memory.

(174) Referring to FIG. 10, the DPIIC chip 410 may include a plurality of large input/output (I/O) circuits each having a large driver configured to drive data to its external circuits in a different chip package and a large receiver configured to receive data from its external circuits in a different chip package, wherein each of its large input/output (I/O) circuits may have an output capacitance or driving capability or loading, for example, between 2 pF and 100 pF, between 2 pF and 50 pF, between 2 pF and 30 pF, between 2 pF and 20 pF, between 2 pF and 15 pF, between 2 pF and 10 pF, or between 2 pF and 5 pF, or greater than 2 pF, 5 pF, 10 pF, 15 pF or 20 pF, and an input capacitance between 0.15 pF and 4 pF or between 0.15 pF and 2 pF, or greater than 0.15 pF; alternatively, each of its large input/output (I/O) circuits may have an I/O power efficiency greater than 3, 5 or 10 pico-Joules per bit, per switch or per voltage swing.

(175) Specification for Auxiliary and Supporting (AS) Integrated-Circuit (IC) Chip

(176) FIG. 11 is a schematically top view showing a block diagram of an auxiliary and supporting (AS) integrated-circuit (IC) chip in accordance with an embodiment of the present application. Referring to FIG. 11, the auxiliary and supporting (AS) integrated-circuit (IC) chip 411 may include one, more or all of the following circuit blocks: (1) a large-input/output (I/O) block 412 configured for serial-advanced-technology-attachment (SATA) ports or peripheral-components-interconnect express (PCIe) ports each having a plurality of large input/output (I/O) circuits configured to couple to a memory integrated-circuit (IC) chip, such as non-volatile memory (NVM) integrated-circuit (IC) chip, NAND flash memory integrated-circuit (IC) chip or NOR flash memory integrated-circuit (IC) chip, for data transmission between the auxiliary and supporting (AS) integrated-circuit (IC) chip 411 and the memory integrated-circuit (IC) chip, wherein each of the large input/output (I/O) circuits may have an output capacitance or driving capability or loading, for example, between 2 pF and 100 pF, between 2 pF and 50 pF, between 2 pF and 30 pF, between 2 pF and 20 pF, between 2 pF and 15 pF, between 2 pF and 10 pF, or between 2 pF and 5 pF, or greater than 2 pF, 5 pF, 10 pF, 15 pF or 20 pF, and an input capacitance between 0.15 pF and 4 pF or between 0.15 pF and 2 pF, or greater than 0.15 pF for example, and alternatively each of the large input/output (I/O) circuits may have an I/O power efficiency greater than 3, 5 or 10 pico-Joules per bit, per switch or per voltage swing, (2) a small-input/output (I/O) block 413 having a plurality of small input/output (I/O) circuits configured to couple to a logic integrated-circuit (IC) chip, such as field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, central-processing-unit (CPU) integrated-circuit (IC) chip, graphic-processing-unit (GPU) integrated-circuit (IC) chip, application-processing-unit (APU) chip or digital-signal-processing (DSP) integrated-circuit (IC) chip, for data transmission between the auxiliary and supporting (AS) integrated-circuit (IC) chip 411 and the logic integrated-circuit (IC) chip, wherein each of the small input/output (I/O) circuits may have an output capacitance or driving capability or loading, for example, between 0.05 pF and 2 pF or between 0.05 pF and 1 pF, or smaller than 2 pF or 1 pF, and an input capacitance between 0.15 pF and 4 pF or between 0.15 pF and 2 pF, or greater than 0.15 pF for example, and alternatively each of the small input/output (I/O) circuits may have an I/O power efficiency smaller than 0.5 pico-Joules per bit, per switch or per voltage swing, or between 0.01 and 0.5 pico-Joules per bit, per switch or per voltage swing, (3) a cryptography block or circuit 517 configured to decrypt, in accordance with a password or key stored or saved in a non-volatile memory cell composed of one or more magnetoresistive random access memory (MRAM) cells, one or more resistive random access memory (RRAM) cells, one or more anti-fuses, one or more e-fuses, or a floating gate of a metal-oxide-semiconductor (MOS) transistor, encrypted data from the memory integrated-circuit (IC) chip as decrypted data to be passed to the logic integrated-circuit (IC) chip and to encrypt, in accordance with the password or key, data from the logic integrated-circuit (IC) chip as encrypted data to be passed to the memory integrated-circuit (IC) chip, (4) a regulating block 415 configured to regulate a voltage of power supply from an input voltage of 12, 5, 3.3 or 2.5 volts as an output voltage of 3.3, 2.5, 1.8, 1.5, 1.35, 1.2, 1.0, 0.75 or 0.5 volts to be delivered to the logic integrated-circuit (IC) chip, and (5) an innovated application-specific-integrated-circuit (ASIC) or customer-owned tooling (COT) block 418, i.e., IAC block, configured to implement intellectual-property (IP) circuits, application-specific (AS) circuits, analog circuits, mixed-mode signal circuits, radio-frequency (RF) circuits, and/or transmitter, receiver, transceiver circuits for customers.

(177) Specification for Logic Drive

(178) FIG. 12A is a schematically top view showing arrangement for various semiconductor integrated-circuit (IC) chips or operation units packaged in a standard commodity logic drive in accordance with an embodiment of the present application. Referring to FIG. 12A, a standard commodity logic drive 300 may be packaged with a standard commodity FPGA IC chip 200, graphic-processing-unit (GPU) integrated-circuit (IC) chip 269a, central-processing-unit (CPU) integrated-circuit (IC) chip 269b, tensor-processing-unit (TPU) integrated-circuit (IC) chip 269c, network-processing-unit (NPU) integrated-circuit (IC) chip 269d and digital-signal-processing (DSP) integrated-circuit (IC) chip 270 each assembled in a single-die type or in an operation unit (OU) 190 as seen in FIGS. 17F, 17G, 19G, 19H, 20A, 20B, 21A, 21B, 22H, 23B, 27G, 30C, 34H, 37C, 38B, 39A, 42E, 45B and 48A. Further, the standard commodity logic drive 300 may be packaged with one or more auxiliary and supporting (AS) integrated-circuit (IC) chips 411 (only one is shown therein) each assembled in a single-die type or in an operation unit (OU) 190 as seen in FIGS. 17F, 17G, 19G, 19H, 20A, 20B, 21A, 21B, 22H, 23B, 27G, 30C, 34H, 37C, 38B, 39A, 42E, 45B and 48A. Further, the standard commodity logic drive 300 may be packaged with multiple high-bandwidth-memory (HBM) integrated-circuit (IC) chips 251 each assembled in a single-die type or in an operation unit (OU) 190 as seen in FIGS. 17F, 17G, 19G, 19H, 20A, 20B, 21A, 21B, 22H, 23B, 27G, 30C, 34H, 37C, 38B, 39A, 42E, 45B and 48A. Each of the HBM IC chips 251 in the standard commodity logic drive 300 may be a high speed, high bandwidth, wide bitwidth dynamic-random-access-memory (DRAM) IC chip, high speed, high bandwidth, wide bitwidth cache static-random-access-memory (SRAM) chip, high speed, high bandwidth, wide bitwidth magnetoresistive random-access-memory (MRAM) chip, high speed, high bandwidth, wide bitwidth resistive random-access-memory (RRAM) chip or high speed, high bandwidth, wide bitwidth phase change random access memory (PCM) chips. For the standard commodity logic drive 300, each of its standard commodity FPGA IC chip 200, graphic-processing unit (GPU) integrated-circuit (IC) chip 269a, central-processing-unit (CPU) integrated-circuit (IC) chip 269b, tensor-processing-unit (TPU) integrated-circuit (IC) chip 269c, network-processing-unit (NPU) integrated-circuit (IC) chip 269d and digital-signal-processing (DSP) integrated-circuit (IC) chip 270 in the single-die type may be arranged horizontally adjacent to one of its HBM IC chips 251 in the single-die type for communication therebetween in a high speed, high bandwidth and wide bitwidth. The standard commodity logic drive 300 may be further packaged with one or more non-volatile memory (NVM) IC chips 250, such as NAND flash integrated-circuit (IC) chips, NOR flash integrated-circuit (IC) chips, ferroelectric random-access-memory (FRAM) integrated-circuit (IC) chips, magnetoresistive random access memory (MRAM) integrated-circuit (IC) chips or resistive random access memory (RRAM) integrated-circuit (IC) chips, (only one is shown therein) configured to store the resulting values or programming codes in a non-volatile manner for programming or configuring the programmable logic cells 2014 and programmable switch cells 379 of its standard commodity FPGA IC chip 200 as seen in FIGS. 7 and 8 and for programming or configuring the cross-point switches 379 of its DPIIC chips 410 as seen in FIG. 10, and to store data in a non-volatile manner from its HBM IC chips 251. The standard commodity logic drive 300 may be further packaged with an innovated application-specific-IC (ASIC) or customer-owned-tooling (COT) (abbreviated as IAC below) integrated-circuit (IC) chip 402 including therein intellectual-property (IP) circuits, application-specific (AS) circuits, analog circuits, mixed-mode signal circuits, radio-frequency (RF) circuits, and/or transmitter, receiver or transceiver circuits, etc. The standard commodity logic drive 300 may be further packaged with a dedicated control and input/output (I/O) chip 260 to control data transmission between any two of its standard commodity FPGA IC chip 200, graphic-processing unit (GPU) integrated-circuit (IC) chip 269a, central-processing-unit (CPU) integrated-circuit (IC) chip 269b, tensor-processing-unit (TPU) integrated-circuit (IC) chip 269c, network-processing-unit (NPU) integrated-circuit (IC) chip 269d, digital-signal-processing (DSP) integrated-circuit (IC) chip 270, auxiliary and supporting (AS) integrated-circuit (IC) chip 411, HBM IC chips 251, IAC IC chip 402 and non-volatile memory (NVM) IC chip 250.

(179) Referring to FIG. 12A, for the standard commodity logic drive, its standard commodity FPGA IC chip 200, graphic-processing unit (GPU) integrated-circuit (IC) chip 269a, central-processing-unit (CPU) integrated-circuit (IC) chip 269b, tensor-processing-unit (TPU) integrated-circuit (IC) chip 269c, network-processing-unit (NPU) integrated-circuit (IC) chip 269d, digital-signal-processing (DSP) integrated-circuit (IC) chip 270, auxiliary and supporting (AS) integrated-circuit (IC) chip 411, HBM IC chips 251, IAC IC chip 402, non-volatile memory (NVM) IC chip 250 and dedicated control and I/O chip 260 may be arranged in an array. The standard commodity logic drive 300 may include multiple inter-chip interconnects 371 each extending alone edges of its standard commodity FPGA IC chip 200, graphic-processing unit (GPU) integrated-circuit (IC) chip 269a, central-processing-unit (CPU) integrated-circuit (IC) chip 269b, tensor-processing-unit (TPU) integrated-circuit (IC) chip 269c, network-processing-unit (NPU) integrated-circuit (IC) chip 269d, digital-signal-processing (DSP) integrated-circuit (IC) chip 270, auxiliary and supporting (AS) integrated-circuit (IC) chip 411, HBM IC chips 251, IAC IC chip 402, non-volatile memory (NVM) IC chip 250 and dedicated control and I/O chip 260.

(180) Referring to FIG. 12A, the standard commodity logic drive 300 may include a plurality of DPIIC chips 410 aligned with a cross of a vertical bundle of inter-chip interconnects 371 and a horizontal bundle of inter-chip interconnects 371. For the standard commodity logic drive 300, each of its DPIIC chips 410 may be arranged at corners of four of its standard commodity FPGA IC chip 200, graphic-processing unit (GPU) integrated-circuit (IC) chip 269a, central-processing-unit (CPU) integrated-circuit (IC) chip 269b, tensor-processing-unit (TPU) integrated-circuit (IC) chip 269c, network-processing-unit (NPU) integrated-circuit (IC) chip 269d, digital-signal-processing (DSP) integrated-circuit (IC) chip 270, auxiliary and supporting (AS) integrated-circuit (IC) chip 411, HBM IC chips 251, IAC IC chip 402, non-volatile memory (NVM) IC chip 250 and dedicated control and I/O chip 260 around said each of its DPIIC chips 410. The inter-chip interconnects 371 may be formed for the programmable interconnect 361. Data transmission may be built (1) between one of the programmable interconnects 361 of the inter-chip interconnects 371 and one of the programmable interconnects 361 of the standard commodity FPGA IC chip 200 via one of the small input/output (I/O) circuits 203 of the standard commodity FPGA IC chip 200, and (2) between one of the programmable interconnects 361 of the inter-chip interconnects 371 and one of the programmable interconnects 361 of one of the DPIIC chips 410 via one of the small input/output (I/O) circuits 203 of said one of the DPIIC chips 410.

(181) Referring to FIG. 12A, for the standard commodity logic drive 300, one or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its standard commodity FPGA IC chip 200 in a single-die type or in the operation unit 190 to all of the DPIIC chips 410. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from the standard commodity FPGA IC chip 200 in a single-die type or in the operation unit 190 to its dedicated control and input/output (I/O) chip 260. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its standard commodity FPGA IC chip 200 in a single-die type or in the operation unit 190 to its NVM IC chip 250. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its standard commodity FPGA IC chip 200 in a single-die type or in the operation unit 190 to its GPU chip 269a in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its standard commodity FPGA IC chip 200 in a single-die type or in the operation unit 190 to its CPU chip 269b in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its standard commodity FPGA IC chip 200 in a single-die type or in the operation unit 190 to its DSP chip 270 in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its standard commodity FPGA IC chip 200 in a single-die type to one of its HBMIC chips 251 in a single-die type next to its standard commodity FPGA IC chip 200 and the communication therebetween may have a data bit width of equal to or greater than 64, 128, 256, 512, 1024, 2048, 4096, 8K, or 16K. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its standard commodity FPGA IC chip 200 in a single-die type or in the operation unit 190 to its IAC IC chip 402. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its standard commodity FPGA IC chip 200 in a single-die type or in the operation unit 190 to its TPU chip 269c in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its standard commodity FPGA IC chip 200 in a single-die type or in the operation unit 190 to its NPU chip 269d in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its standard commodity FPGA IC chip 200 in a single-die type to its standard commodity FPGA IC chip 200 in the operation unit 190.

(182) Referring to FIG. 12A, for the standard commodity logic drive 300, one or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its DPIIC chips 410 to its dedicated control and input/output (I/O) chip 260. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its DPIIC chips 410 to its NVM IC chip 250. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its DPIIC chips 410 to its GPU chip 269a in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its DPIIC chips 410 to its CPU chip 269b in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its DPIIC chips 410 to its DSP chip 270 in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its DPIIC chips 410 to all of its HBM IC chips 251 each in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its DPIIC chips 410 to the others of the DPIIC chips 410. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its DPIIC chips 410 to its IAC IC chip 402. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its DPIIC chips 410 to its TPU chip 269c in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its DPIIC chips 410 to its NPU chip 269d in a single-die type or in the operation unit 190.

(183) Referring to FIG. 12A, for the standard commodity logic drive 300, one or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its CPU chip 269b in a single-die type or in the operation unit 190 to its GPU chip 269a in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its TPU chip 269c in a single-die type or in the operation unit 190 to its GPU chip 269a in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its NPU chip 269d in a single-die type or in the operation unit 190 to its GPU chip 269a in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its DSP chip 270 in a single-die type or in the operation unit 190 to its GPU chip 269a in a single-die type or in the operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its CPU chip 269b in a single-die type or in its operation unit 190 to its NVM IC chip 250. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its TPU chip 269c in a single-die type or in its operation unit 190 to its NVM IC chip 250. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its NPU chip 269d in a single-die type or in its operation unit 190 to its NVM IC chip 250. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its DSP chip 270 in a single-die type or in its operation unit 190 to its NVM IC chip 250. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its CPU chip 269b in a single-die type to one of its HBM IC chips 251 in a single-die type next to its CPU chip 269b and the communication therebetween may have a data bit width of equal to or greater than 64, 128, 256, 512, 1024, 2048, 4096, 8K, or 16K. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its TPU chip 269c in a single-die type to one of its HBM IC chips 251 in a single-die type next to its TPU chip 269c and the communication therebetween may have a data bit width of equal to or greater than 64, 128, 256, 512, 1024, 2048, 4096, 8K, or 16K. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its NPU chip 269d in a single-die type to one of its HBM IC chips 251 in a single-die type next to its NPU chip 269d and the communication therebetween may have a data bit width of equal to or greater than 64, 128, 256, 512, 1024, 2048, 4096, 8K, or 16K. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its DSP chip 270 in a single-die type to one of its HBM IC chips 251 in a single-die type next to its DSP chip 270 and the communication therebetween may have a data bit width of equal to or greater than 64, 128, 256, 512, 1024, 2048, 4096, 8K, or 16K. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its CPU chip 269b in a single-die type or in its operation unit 190 to the IAC IC chip 402. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its TPU chip 269c in a single-die type or in its operation unit 190 to the IAC IC chip 402. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its NPU chip 269d in a single-die type or in its operation unit 190 to the IAC IC chip 402. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its DSP chip 270 in a single-die type or in its operation unit 190 to its IAC IC chip 402. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its CPU chip 269b in a single-die type or in its operation unit 190 to its DSP chip 270 in a single-die type or in its operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its CPU chip 269b in a single-die type or in its operation unit 190 to its TPU chip 269c in a single-die type or in its operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its CPU chip 269b in a single-die type or in its operation unit 190 to its NPU chip 269d in a single-die type or in its operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its TPU chip 269c in a single-die type or in its operation unit 190 to its NPU chip 269d in a single-die type or in its operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its GPU chip 269a in a single-die type to one of its HBM IC chips 251 in a single-die type next to its GPU chip 269a and the communication therebetween may have a data bit width of equal to or greater than 64, 128, 256, 512, 1024, 2048, 4096, 8K, or 16K. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its GPU chip 269a in a single-die type or in its operation unit 190 to its NVM IC chip 250. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its GPU chip 269a in a single-die type to its GPU chip 269a in its operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its GPU chip 269a in a single-die type or in its operation unit 190 to its IAC IC chip 402. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its NVM IC chip 250 to its dedicated control and input/output (I/O) chip 260. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its HBM IC chips 251 in a single-die type or in its operation unit 190 to its dedicated control and input/output (I/O) chip 260. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its GPU chip 269a in a single-die type or in its operation unit 190 to its dedicated control and input/output (I/O) chip 260. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its CPU chip 269b in a single-die type or in its operation unit 190 to its dedicated control and input/output (I/O) chip 260. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its TPU chip 269c in a single-die type or in its operation unit 190 to its dedicated control and input/output (I/O) chip 260. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its NPU chip 269d in a single-die type or in its operation unit 190 to its dedicated control and input/output (I/O) chip 260. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its DSP chip 270 in a single-die type or in its operation unit 190 to its dedicated control and input/output (I/O) chip 260. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its NVM IC chip 250 to each of its HBM IC chips 251 in a single-die type or in its operation unit 190. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its NVM IC chip 250 to its IAC IC chip 402. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its HBM IC chips 251 in a single-die type or in its operation unit 190 to its IAC IC chip 402. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its IAC IC chip 402 to its dedicated control and input/output (I/O) chip 260. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its HBM IC chips 251 in a single-die type or in its operation unit 190 to one of the others of the HBM IC chips 251 in a single-die type or in its operation unit 190.

(184) Referring to FIG. 12A, the standard commodity logic drive 300 may include multiple dedicated input/output (I/O) chips 265 in a peripheral region thereof surrounding a central region thereof, in which its standard commodity FPGA IC chip 200, graphic-processing unit (GPU) integrated-circuit (IC) chip 269a, central-processing-unit (CPU) integrated-circuit (IC) chip 269b, tensor-processing-unit (TPU) integrated-circuit (IC) chip 269c, network-processing-unit (NPU) integrated-circuit (IC) chip 269d, digital-signal-processing (DSP) integrated-circuit (IC) chip 270, HBM IC chips 251, IAC IC chip 402, non-volatile memory (NVM) IC chip 250, dedicated control and I/O chip 260 and DPIIC chips 410 are located. For the standard commodity logic drive 300, one or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its standard commodity FPGA IC chip 200 in a single-die type or in its operation unit 190 to all of its dedicated input/output (I/O) chips 265. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its DPIIC chips 410 to all of its dedicated input/output (I/O) chips 265. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its NVM IC chip 250 to all of its dedicated input/output (I/O) chips 265. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its dedicated control and input/output (I/O) chip 260 to all of its dedicated input/output (I/O) chips 265. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its GPU chip 269a in a single-die type or in its operation unit 190 to all of its dedicated input/output (I/O) chips 265. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its CPU chip 269b in a single-die type or in its operation unit 190 to all of its dedicated input/output (I/O) chips 265. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its TPU chip 269c in a single-die type or in its operation unit 190 to all of its dedicated input/output (I/O) chips 265. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its NPU chip 269d in a single-die type or in its operation unit 190 to all of its dedicated input/output (I/O) chips 265. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its DSP chip 270 in a single-die type or in its operation unit 190 to all of its dedicated input/output (I/O) chips 265. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from each of its HBM IC chips 251 in a single-die type or in its operation unit 190 to all of its dedicated input/output (I/O) chips 265. One or more of the programmable interconnects 361 of its inter-chip interconnects 371 may couple from its IAC IC chip 402 to all of its dedicated input/output (I/O) chips 265. For the standard commodity logic drive 300, its dedicated control and input/output (I/O) chip 260 is configured to control data transmission between each of its dedicated input/output (I/O) chips 265 and one of its standard commodity FPGA IC chip 200, graphic-processing unit (GPU) integrated-circuit (IC) chip 269a, central-processing-unit (CPU) integrated-circuit (IC) chip 269b, tensor-processing-unit (TPU) integrated-circuit (IC) chip 269c, network-processing-unit (NPU) integrated-circuit (IC) chip 269d, digital-signal-processing (DSP) integrated-circuit (IC) chip 270, HBM IC chips 251, IAC IC chip 402, non-volatile memory (NVM) IC chip 250, dedicated control and I/O chip 260 and DPIIC chips 410.

(185) Referring to FIG. 12A, for the standard commodity logic drive 300 being in operation, each of its DPIIC chips 410 may be arranged with the SRAM cells acting as cache memory to store data from any of its standard commodity FPGA IC chip 200, graphic-processing unit (GPU) integrated-circuit (IC) chip 269a, central-processing-unit (CPU) integrated-circuit (IC) chip 269b, tensor-processing-unit (TPU) integrated-circuit (IC) chip 269c, network-processing-unit (NPU) integrated-circuit (IC) chip 269d, digital-signal-processing (DSP) integrated-circuit (IC) chip 270, auxiliary and supporting (AS) integrated-circuit (IC) chip 411, HBM IC chips 251, IAC IC chip 402, non-volatile memory (NVM) IC chip 250, dedicated control and I/O chip 260 and DPIIC chips 410.

(186) Referring to FIG. 12A, for the standard commodity logic drive 300, its non-volatile memory (NVM) IC chip 250 may include multiple large input/output (I/O) circuits each having an output capacitance or driving capability or loading, for example, between 2 pF and 100 pF, between 2 pF and 50 pF, between 2 pF and 30 pF, between 2 pF and 20 pF, between 2 pF and 15 pF, between 2 pF and 10 pF, or between 2 pF and 5 pF, or greater than 2 pF, 5 pF, 10 pF, 15 pF or 20 pF, and an input capacitance between 0.15 pF and 4 pF or between 0.15 pF and 2 pF, or greater than 0.15 pF for example; alternatively, each of the large input/output (I/O) circuits of its non-volatile memory (NVM) IC chip 250 may have an I/O power efficiency greater than 3, 5 or 10 pico-Joules per bit, per switch or per voltage swing. Alternatively, its non-volatile memory (NVM) IC chip 250 may include a cryptography block or circuit configured to decrypt, in accordance with a password or key stored or saved in a non-volatile memory cell of the cryptography block or circuit of its non-volatile memory (NVM) IC chip 250, which may be composed of one or more magnetoresistive random access memory (MRAM) cells, one or more resistive random access memory (RRAM) cells, one or more anti-fuses, one or more e-fuses, or a floating gate of a metal-oxide-semiconductor (MOS) transistor, encrypted data from multiple non-volatile memory cells of its non-volatile memory (NVM) IC chip 250 as decrypted data and to encrypt, in accordance with the password or key, data as encrypted data to be stored in multiple non-volatile memory cells of its non-volatile memory (NVM) IC chip 250.

(187) Referring to FIG. 12A, for a first aspect of the standard commodity logic drive 300, a first one of the large I/O circuits of its NVM IC chip 250 may have a large driver coupling to a large receiver of a second one of the large I/O circuits of one of the AS IC chip 411 via one of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing first encrypted CPM data from the large driver of the first one of the large I/O circuits to the large receiver of the second one of the large I/O circuits. Next, the first encrypted CPM data may be decrypted as illustrated in FIG. 11, in accordance with a password or key, by the cryptography block or circuit 517 of its AS IC chip 411 as first decrypted CPM data. Next, a first one of the small I/O circuits of its AS IC chip 411 may have a small driver coupling to a small receiver of a second one of the small I/O circuits of its standard commodity FPGA IC chip 200 via another of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing the first decrypted CPM data from the small driver of the first one of the small I/O circuits to the small receiver 375 of the second one of the small I/O circuits. Next, one of the first type of memory cells 490 of one of the programmable logic cells (LC) 2014 of its standard commodity FPGA IC chip 200 as seen in FIG. 7 may be programmed or configured in accordance with the first decrypted CPM data, or one of the first type of memory cells 362 of one of the programmable switch cells 379 of its standard commodity FPGA IC chip 200 as seen in FIG. 8 may be programmed or configured in accordance with the first decrypted CPM data. Alternatively, a third one of the small I/O circuits of its standard commodity FPGA IC chip 200 may have a small driver coupling to a small receiver of a fourth one of the small I/O circuits of its AS IC chip 411 via another of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing second CPM data used to program or configure the first type of memory cells 490 of one of the programmable logic cells (LC) 2014 of its standard commodity FPGA IC chip 200 or the first type of memory cells 362 of one of the programmable switch cells 379 of its standard commodity FPGA IC chip 200 from the small driver of the third one of the small I/O circuits to the small receiver of the fourth one of the small I/O circuits. Next, the second CPM data may be encrypted as illustrated in FIG. 11, in accordance with the password or key, by the cryptography block or circuit 517 of its AS IC chip 411 as second encrypted CPM data. Next, a third one of the large I/O circuits of its AS IC chip 411 may have a large driver coupling to a large receiver of a fourth one of the large I/O circuits of its NVM IC chip 250 via another of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing the second encrypted CPM data from the large driver of the third one of the large I/O circuits to the large receiver of the fourth one of the large I/O circuits to be stored in its NVM IC chip 250.

(188) Referring to FIG. 12A, for a second aspect of the standard commodity logic drive 300, a first one of the large I/O circuits of its NVM IC chip 250 may have a large driver coupling to a large receiver of a second one of the large I/O circuits of its AS IC chip 411 via one of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing first encrypted CPM data from the large driver 274 of the first one of the large I/O circuits to the large receiver 275 of the second one of the large I/O circuits 341. Next, a first one of the small I/O circuits of its AS IC chip 411 may have a small driver coupling to a small receiver of a second one of the small I/O circuits of its standard commodity FPGA IC chip 200 via another of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing the first encrypted CPM data from the small driver 374 of the first one of the small I/O circuits to the small receiver of the second one of the small I/O circuits. Next, its standard commodity FPGA IC chip 200 may include the cryptography block or circuit as illustrated in FIG. 9 configured to decrypt, in accordance with a password or key, the first encrypted CPM data as first decrypted CPM data. Next, one of the first type of memory cells 490 of one of the programmable logic cells (LC) 2014 of its standard commodity FPGA IC chip 200 as seen in FIG. 7 may be programmed or configured in accordance with the first decrypted CPM data, or one of the first type of memory cells 362 of one of the programmable switch cells 379 of its standard commodity FPGA IC chip 200 as seen in FIG. 8 may be programmed or configured in accordance with the first decrypted CPM data. Alternatively, second CPM data used to program or configure the first type of memory cells 490 of one of the programmable logic cells (LC) 2014 of its standard commodity FPGA IC chip 200 or the first type of memory cells 362 of one of the programmable switch cells 379 of its standard commodity FPGA IC chip 200 may be encrypted, in accordance with the password or key, by the cryptography block or circuit of its standard commodity FPGA IC chip 200 as second encrypted CPM data. Next, a third one of the small I/O circuits 203 of its standard commodity FPGA IC chips 200 may have a small driver coupling to a small receiver of a fourth one of the small I/O circuits of its AS IC chip 411 via another of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing the second encrypted CPM data from the small driver 374 of the third one of the small I/O circuits 203 to the small receiver 375 of the fourth one of the small I/O circuits 203. Next, a third one of large I/O circuits of its AS IC chip 411 may have a large driver coupling to a large receiver of a fourth one of the large I/O circuits of its NVM IC chip 250 via another of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing the second encrypted CPM data from the large driver of the third one of the large I/O circuits to the large receiver 275 of the fourth one of the large I/O circuits to be stored in its NVM IC chip 250.

(189) Referring to FIG. 12A, for a third aspect of the standard commodity logic drive 300, a first one of the large I/O circuits of its NVM IC chip 250 may have a large driver coupling to a large receiver of a second one of the large I/O circuits of its standard commodity FPGA IC chip 200 via one of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing first encrypted CPM data from the large driver of the first one of the large I/O circuits to the large receiver of the second one of the large I/O circuits. Next, its standard commodity FPGA IC chip 200 may include the cryptography block or circuit as illustrated in FIG. 9 configured to decrypt, in accordance with a password or key, the first encrypted CPM data as first decrypted CPM data. Next, one of the first type of memory cells 490 of one of the programmable logic cells (LC) 2014 of its standard commodity FPGA IC chip 200 as seen in FIG. 7 may be programmed or configured in accordance with the first decrypted CPM data, or one of the first type of memory cells 362 of one of the programmable switch cells 379 of its standard commodity FPGA IC chip 200 as seen in FIG. 8 may be programmed or configured in accordance with the first decrypted CPM data. Alternatively, second CPM data used to program or configure the first type of memory cells 490 of one of the programmable logic cells (LC) 2014 of its standard commodity FPGA IC chip 200 or the first type of memory cells 362 of one of the programmable switch cells 379 of its standard commodity FPGA IC chip 200 may be encrypted, in accordance with the password or key, by the cryptography block or circuit of its standard commodity FPGA IC chip 200 as second encrypted CPM data. Next, a third one of the large I/O circuits of its standard commodity FPGA IC chip 200 may have a large driver coupling to a large receiver of a fourth one of the large I/O circuits of its NVM IC chip 250 via another of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing the second encrypted CPM data from the large driver of the third one of the small I/O circuits 203 to the large receiver of the fourth one of the small I/O circuits 203 to be stored in its NVM IC chip 250.

(190) Referring to FIG. 12A, for a fourth aspect of the standard commodity logic drive 300, its NVM IC chip 250 may include the cryptography block or circuit configured to decrypt, in accordance with a password or key, first encrypted CPM data stored therein as first decrypted CPM data. A first one of the large I/O circuits of its NVM IC chip 250 may have a large driver coupling to a large receiver of a second one of the large I/O circuits of its AS IC chip 411 via one of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing the first decrypted CPM data from the large driver of the first one of the large I/O circuits to the large receiver of the second one of the large I/O circuits. Next, a first one of the small I/O circuits of its AS IC chip 411 may have a small driver coupling to a small receiver of a second one of the small I/O circuits of its standard commodity FPGA IC chip 200 via another of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing the first decrypted CPM data from the small driver of the first one of the small I/O circuits to the small receiver of the second one of the small I/O circuits. Next, one of the first type of memory cells 490 of one of the programmable logic cells (LC) 2014 of its standard commodity FPGA IC chip 200 as seen in FIG. 7 may be programmed or configured in accordance with the first decrypted CPM data, or one of the first type of memory cells 362 of one of the programmable switch cells 379 of its standard commodity FPGA IC chip 200 as seen in FIG. 8 may be programmed or configured in accordance with the first decrypted CPM data. Alternatively, a third one of the small I/O circuits 203 of its standard commodity FPGA IC chip 200 may have a small driver coupling to a small receiver of a fourth one of the small I/O circuits of its AS IC chip 411 via another of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing second CPM data used to program or configure the first type of memory cells 490 of one of the programmable logic cells (LC) 2014 of its standard commodity FPGA IC chip 200 or the first type of memory cells 362 of one of the programmable switch cells 379 of its standard commodity FPGA IC chip 200 from the small driver of the third one of the small I/O circuits to the small receiver of the fourth one of the small I/O circuits. Next, a third one of the large I/O circuits of its AS IC chip 411 may have a large driver coupling to a large receiver of a fourth one of the large I/O circuits of its NVM IC chip 250 via another of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing the second CPM data from the large driver of the third one of the large I/O circuits to the large receiver of the fourth one of the large I/O circuits. The second CPM data may be encrypted, in accordance with the password or key, by the cryptography block or circuit of its NVM IC chip 250 as second encrypted CPM data to be stored in its NVM IC chip 250.

(191) Referring to FIG. 12A, for a fifth aspect of the standard commodity logic drive 300, its NVM IC chip 250 may include the cryptography block or circuit configured to decrypt, in accordance with a password or key, first encrypted CPM data stored therein as first decrypted CPM data. A first one of the large I/O circuits of its NVM IC chip 250 may have a large driver coupling to a large receiver of a second one of the large I/O circuits of its standard commodity FPGA IC chip 200 via one of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing the first decrypted CPM data from the large driver of the first one of the large I/O circuits to the large receiver of the second one of the large I/O circuits. Next, one of the first type of memory cells 490 of one of the programmable logic cells (LC) 2014 of its standard commodity FPGA IC chip 200 as seen in FIG. 7 may be programmed or configured in accordance with the first decrypted CPM data, or one of the first type of memory cells 362 of one of the programmable switch cells 379 of its standard commodity FPGA IC chip 200 as seen in FIG. 8 may be programmed or configured in accordance with the first decrypted CPM data. Alternatively, a third one of the large I/O circuits of its standard commodity FPGA IC chips 200 may have a large driver coupling to a large receiver of a fourth one of the large I/O circuits of its NVM IC chip 250 via another of the non-programmable interconnects 364 of the inter-chip interconnects 371 for passing second CPM data used to program or configure the first type of memory cells 490 of one of the programmable logic cells (LC) 2014 of its standard commodity FPGA IC chip 200 or the first type of memory cells 362 of one of the programmable switch cells 379 of its standard commodity FPGA IC chips 200 from the large driver of the third one of the large I/O circuits to the large receiver of the fourth one of the large I/O circuits. The second CPM data may be encrypted, in accordance with the password or key, by the cryptography block or circuit of its NVM IC chip 250 as second encrypted CPM data to be stored in its NVM IC chip 250.

(192) FIG. 12B is a block diagram showing interconnection in a standard commodity logic drive in accordance with an embodiment of the present application. Referring to FIG. 12B, for the standard commodity logic drive 300 as illustrated in FIG. 12A, each of its dedicated I/O chips 265 and control and I/O chip 260 may include a first group of small I/O circuits 203 each coupling to one of a first group of small I/O circuits 203 of its FPGA IC chip 200 through one of its inter-chip interconnect 371, i.e., programmable or non-programmable interconnect 361 or 364, and a second group of small I/O circuits 203 each coupling to one of a first group of small I/O circuits 203 of its NVM IC chip 250 through one of its inter-chip interconnect 371, i.e., programmable or non-programmable interconnect 361 or 364. Its FPGA IC chip 200 may include a second group of small I/O circuits 203 each coupling to one of a second group of small I/O circuits 203 of its NVM IC chip 250 through one of its inter-chip interconnect 371, i.e., programmable or non-programmable interconnect 361 or 364. Each of its dedicated I/O chips 265 and control and I/O chip 260 may include (1) a first group of large I/O circuits 341 each coupling to one of its metal bumps, pillars or pads 570 or metal pads 583 as seen in FIGS. 22H, 23B, 27G, 30C, 34H, 37C, 38B, 39A, 42E, 45B and 48A for one or more serial-advanced-technology-attachment (SATA) ports 521 and one of the large I/O circuits 341 of its NVM IC chip 250 through one of its programmable or non-programmable interconnects 361 or 364, (2) a second group of large I/O circuits 341 each coupling to one of its metal bumps, pillars or pads 570 or metal pads 583 for one or more universal serial bus (USB) ports 522 through one of its programmable or non-programmable interconnects 361 or 364, (3) a third group of large I/O circuits 341 each coupling to one of its metal bumps, pillars or pads 570 or metal pads 583 for one or more serializer/deserializer (SerDes) ports 523 through one of its programmable or non-programmable interconnects 361 or 364, (4) a fourth group of large I/O circuits 341 each coupling to one of its metal bumps, pillars or pads 570 or metal pads 583 for one or more wide input/output (I/O) ports 523 through one of its programmable or non-programmable interconnects 361 or 364, (5) a fifth group of large I/O circuits 341 each coupling to one of its metal bumps, pillars or pads 570 or metal pads 583 for one or more peripheral-components-interconnect express (PCIe) ports 525 through one of its programmable or non-programmable interconnects 361 or 364, (6) a sixth group of large I/O circuits 341 each coupling to one of its metal bumps, pillars or pads 570 or metal pads 583 for one or more wireless ports 526 through one of its programmable or non-programmable interconnects 361 or 364, (7) a seventh group of large I/O circuits 341 each coupling to one of its metal bumps, pillars or pads 570 or metal pads 583 for one or more IEEE 1394 ports 527 through one of its programmable or non-programmable interconnects 361 or 364 and (8) an eighth group of large I/O circuits 341 each coupling to one of its metal bumps, pillars or pads 570 or metal pads 583 for one or more thunderbolt ports 528 through one of its programmable or non-programmable interconnects 361 or 364.

(193) Embodiment for Fine-line Interconnection Bridge (FIB)

(194) FIGS. 13A and 13B are schematically cross-sectional views showing various fine-line interconnection bridges in accordance with an embodiment of the present application. Referring to FIGS. 13A and 13B, a first or second type of fine-line interconnection bridge (FIB) 690 is provided for horizontal connection to transmit signals in a horizontal direction.

(195) 1. First Type of Fine-line Interconnection Bridge (FIB)

(196) Referring to FIG. 13A, a first type of fine-line interconnection bridge (FIB) 690 may include (1) a semiconductor substrate 2, (2) a first interconnection scheme 560 on the semiconductor substrate 2, wherein its first interconnection scheme 560 may include multiple insulating dielectric layers 12 and multiple interconnection metal layers 6 each in neighboring two of the insulating dielectric layers 12, wherein each of the interconnection metal layers 6 of its first interconnection scheme 560 is patterned with multiple metal pads, lines or traces 8 in an upper one of the neighboring two of the insulating dielectric layers 12 of its first interconnection scheme 560 and multiple metal vias 10 in a lower one of the neighboring two of the insulating dielectric layers 12 of its first interconnection scheme 560, wherein between each neighboring two of the interconnection metal layers 6 of its first interconnection scheme 560 is provided one of the insulating dielectric layers 12 of its first interconnection scheme 560, wherein an upper one of the interconnection metal layers 6 of its first interconnection scheme 560 may couple to a lower one of the interconnection metal layers 6 of its first interconnection scheme 560 through an opening in one of the insulating dielectric layers 12 of its first interconnection scheme 560 between the upper and lower ones of the interconnection metal layers 6 of its first interconnection scheme 560, (3) a passivation layer 14 as illustrated in FIG. 1A, 1C or 1E on its first interconnection scheme 560, wherein the topmost one of the interconnection metal layers 6 of its first interconnection scheme 560 may have the metal pads 8 at bottoms of multiple openings 14a in the passivation layer 14, and (4) multiple micro-bumps or micro-pads 34, which may be of one of the first through fourth types having the same specifications as the first through fourth types of micro-bumps or micro-pads 34 respectively as illustrated in FIG. 1A, 1C or 1E, on the metal pads 8 of the topmost one of the interconnection metal layers 6 of its first interconnection scheme 560 at the bottoms of the openings 14a in its passivation layer 14.

(197) Referring to FIG. 13A, for the first interconnection scheme 560, one of the metal pads, lines or traces 8 of each of its interconnection metal layers 6 may have a thickness between 3 nm and 500 nm and may have a width between 3 nm and 500 nm. A space or pitch between neighboring two of the metal pads, lines or traces 8 of each of its interconnection metal layers 6 may be between 3 nm and 500 nm. Each of its insulating dielectric layers 12 may include a layer of silicon oxide, silicon oxynitride or silicon oxycarbide having a thickness between 3 nm and 500 nm. Each of its interconnection metal layers 6 may include (1) a copper layer 24 having lower portions in openings in a lower one of the insulating dielectric layers 12, such as SiOC layer having a thickness of between 3 nm and 500 nm, and upper portions having a thickness of between 3 nm and 500 nm over the lower one of the insulating dielectric layers 12 and in openings in an upper one of the insulating dielectric layers 12, (2) an adhesion layer 18, such as titanium or titanium nitride having a thickness of between 1 nm and 50 nm, at a bottom and sidewall of each of the lower portions of the copper layer 24 and at a bottom and sidewall of each of the upper portions of the copper layer 24, and (3) a seed layer 22, such as copper, between the copper layer 24 and the adhesion layer 18, wherein the copper layer 24 has a top surface substantially coplanar with a top surface of the upper one of the insulating dielectric layers 12. For an example, the first interconnection scheme 560 may be formed with one or more passive devices, such as resistors, capacitors or inductors.

(198) 2. Second Type of Fine-line Interconnection Bridge (FIB)

(199) Referring to FIG. 13B, a second type of fine-line interconnection bridge (FIB) 690 may have a structure similar to that as illustrated in FIG. 13A. For an element indicated by the same reference number shown in FIGS. 13A and 13B, the specification of the element as seen in FIG. 13B may be referred to that of the element as illustrated in FIG. 13A. The difference between the first and second types of fine-line interconnection bridges (FIB) 690 is that the second type of fine-line interconnection bridge (FIB) 690 may further include a second interconnection scheme 588 over the passivation layer 14, wherein the second interconnection scheme 588 may include one or more interconnection metal layers 27 coupling to the metal pads 8 of the topmost one of the interconnection metal layers 6 of its first interconnection scheme 560 through the openings 14a in its passivation layer 14, and one or more polymer layers 42, i.e., insulating dielectric layers, each between neighboring two of the interconnection metal layers 27 of its second interconnection scheme 588, under a bottommost one of the interconnection metal layers 27 of its second interconnection scheme 588 or over a topmost one of the interconnection metal layers 27 of its second interconnection scheme 588, wherein an upper one of the interconnection metal layers 27 of its second interconnection scheme 588 may couple to a lower one of the interconnection metal layers 27 of its second interconnection scheme 588 through an opening in one of the polymer layers 42 of its second interconnection scheme 588 between the upper and lower ones of the interconnection metal layers 27 of its second interconnection scheme 588, wherein the topmost one of the interconnection metal layers 27 of its second interconnection scheme 588 may have multiple metal pads at bottoms of multiple openings 42a in the topmost one of the polymer layers 42 of its second interconnection scheme 588, and multiple micro-bumps or micro-pads 34 as illustrated in FIG. 1A, 1C or 1E may be formed on the metal pads of the topmost one of the interconnection metal layers 27 of its second interconnection scheme 588 at the bottoms of the openings 42a in the topmost one of the polymer layers 42 of its second interconnection scheme 588.

(200) Referring to FIG. 13B, for the second interconnection scheme 588, each of its interconnection metal layers 27 may include (1) a copper layer 40 having lower portions in openings in one of the polymer layers 42 having a thickness of between 0.3 μm and 20 nm, and upper portions having a thickness 0.3 μm and 20 μm over said one of the polymer layers 42, (2) an adhesion layer 28a, such as titanium or titanium nitride having a thickness of between 1 nm and 50 nm, at a bottom and sidewall of each of the lower portions of the copper layer 40 and at a bottom of each of the upper portions of the copper layer 40, and (3) a seed layer 28b, such as copper, between the copper layer 40 and the adhesion layer 28a, wherein said each of the upper portions of the copper layer 40 may have a sidewall not covered by the adhesion layer 28a. For an example, each of the first and second interconnection schemes 560 and 588 may be formed with one or more passive devices, such as resistors, capacitors or inductors.

(201) Specification for Semiconductor Integrated-circuit (IC) Chip

(202) FIGS. 14A-14F are schematically cross-sectional views showing various semiconductor integrated-circuit (IC) chips in accordance with an embodiment of the present application. Referring to FIGS. 14A-14F, either type of semiconductor integrated-circuit (IC) chip 100 may be provided for the standard commodity FPGA IC chip 200, DPIIC chip 410, dedicated I/O chip 265, dedicated control and I/O chip 260, NVM IC chip 250, IAC IC chip 402, HBM IC chips 251, GPU chip 269a, CPU chip 269b, TPU chip 269c, NPU chip 269d, digital-signal-processing (DSP) integrated-circuit (IC) chip 270 and auxiliary and supporting (AS) integrated-circuit (IC) chip 411 as seen in FIG. 12A.

(203) 1. First Type of Semiconductor Integrated-circuit (IC) Chip

(204) Referring to FIG. 14A, a first type of semiconductor integrated-circuit (IC) chip 100 may have the structure as illustrated in FIG. 13A or 13B. For an element indicated by the same reference number shown in FIGS. 13A, 13B and 14A, the specification of the element as seen in FIG. 14A may be referred to that of the element as illustrated in FIG. 13A or 13B. The difference between the first type of semiconductor integrated-circuit (IC) chip 100 and the second type of fine-line interconnection bridge (FIB) 690 is that the first type of semiconductor integrated-circuit (IC) chip 100 as seen in FIG. 14A may further include multiple semiconductor devices 4 at an active surface of its semiconductor substrate 2 and under its first interconnection scheme 560, wherein each of its semiconductor devices 4 may couple to the interconnection metal layers 6 of its first interconnection scheme 560. For the first type of semiconductor integrated-circuit (IC) chip 100, its semiconductor devices 4 may include a memory cell, logic circuit, passive device, such as resistor, capacitor, inductor or filter, or active device, such as P-type or N-type metal-oxide-semiconductor (MOS) transistor. Multiple of the semiconductor devices 4 may compose the selection circuits 211 of the programmable logic cells (LC) 2014, memory cells 490 of the programmable logic cells (LC) 2014, memory cells 362 for the cross-point switches 379, small I/O circuits 203, large I/O circuits and/or cryptography block or circuit as illustrated in FIGS. 7, 8 and 9, for the standard commodity FPGA IC chip 200 of the standard commodity logic drive 300 as seen in FIG. 12A. The semiconductor devices 4 may compose the memory cells 362 for the programmable switch cells 379 and small I/O circuits 203, as illustrated in FIGS. 8 and 10, for each of the DPIIC chips 410 of the standard commodity logic drive 300 as seen in FIG. 12A. Multiple of the semiconductor devices 4 may compose the large I/O circuits of large-input/output (I/O) block 412, small I/O circuits of the small-input/output (I/O) block 413, cryptography block or circuit 517, regulating block 415 and innovated application-specific-integrated-circuit (ASIC) or customer-owned tooling (COT) block 418, as illustrated in FIG. 11, for the auxiliary and supporting (AS) integrated-circuit (IC) chip 411 of the standard commodity logic drive 300 as seen in FIG. 12A.

(205) 2. Second Type of Semiconductor Integrated-circuit (IC) Chip

(206) Referring to FIG. 14B, a second type of semiconductor integrated-circuit (IC) chip 100 may have similar structure as illustrated in FIG. 14A. For an element indicated by the same reference number shown in FIG. 1A-1F, 13A, 13B, 14A or 14B, the specification of the element as seen in FIG. 14B may be referred to that of the element as illustrated in FIG. 1A-1F, 13A, 13B or 14A. The difference between the first and second types of semiconductor integrated-circuit (IC) chips 100 is that the second type of semiconductor integrated-circuit (IC) chip 100 may further include multiple through silicon vias (TSVs) 157 as illustrated in FIGS. 1A-1F in its semiconductor substrate 2, wherein each of its through silicon vias (TSVs) 157 may couple to one or more of its semiconductor devices 4 through one or more of the interconnection metal layers 6 of its first interconnection scheme 560.

(207) 3. Third Type of Semiconductor Integrated-circuit (IC) Chip

(208) Referring to FIG. 14C, a third type of semiconductor integrated-circuit (IC) chip 100 may have similar structure as illustrated in FIG. 14B. For an element indicated by the same reference number shown in FIG. 1A-1F, 13A, 13B, 14A, 14B or 14C, the specification of the element as seen in FIG. 14C may be referred to that of the element as illustrated in FIG. 1A-1F, 13A, 13B, 14A or 14B. The difference between the second and third types of semiconductor integrated-circuit (IC) chips 100 is that each of the through silicon vias (TSVs) 157 of the third type of semiconductor integrated-circuit (IC) chip 100 may have the copper layer 156 having a backside surface coplanar with a backside 2b of the semiconductor substrate 2 of the third type of semiconductor integrated-circuit (IC) chip 100 and have the insulating lining 153 surrounding the adhesion layer 154, seed layer 155 and copper layer 156 of said each of the through silicon vias (TSVs) 157. The third type of semiconductor integrated-circuit (IC) chip 100 may further include a passivation layer 15 on the backside 2b of its semiconductor substrate 2, wherein each opening 15a in its passivation layer 15 may be aligned with the backside of the copper layer 156 of one of its through silicon vias (TSVs) 157. The passivation layer 15 may have the same specifications as those of the passivation layer 14 as illustrated in FIG. 1A, 1C or 1E. The third type of semiconductor integrated-circuit (IC) chip 100 may further include multiple micro-bumps or micro-pads 570 each on the backside of copper layer 156 of one of its through silicon vias (TSVs) 157. The micro-bumps or micro-pads 570 may be of one of the first through fourth types having the same specifications as the first through fourth types of micro-bumps or micro-pads 34 as illustrated in FIG. 1A, 1C or 1E, respectively.

(209) 4. Fourth Type of Semiconductor Integrated-circuit (IC) Chip

(210) Referring to FIG. 14D, a fourth type of semiconductor integrated-circuit (IC) chip 100 may have similar structure as illustrated in FIG. 14A. For an element indicated by the same reference number shown in FIG. 13A, 14A or 14D, the specification of the element as seen in FIG. 14D may be referred to that of the element as illustrated in FIG. 13A or 14A. The difference between the first and fourth types of semiconductor integrated-circuit (IC) chips 100 is that the fourth type of semiconductor integrated-circuit (IC) chip 100 may be provided with (1) an insulating bonding layer 52 at its active side and on the topmost one of the insulating dielectric layers 12 of its first interconnection scheme 560 and (2) multiple metal pads 6a at its active side and in multiple openings 52a in its insulating bonding layer 52 and on the topmost one of the interconnection metal layers 6 of its first interconnection scheme 560, instead of the passivation layer 14 and micro-bumps or micro-pads 34 as seen in FIG. 14A. For the fourth type of semiconductor integrated-circuit (IC) chip 100, its insulating bonding layer 52 may include a silicon-oxide layer having a thickness between 0.1 and 2 Each of its metal pads 6a may include (1) a copper layer 24 having a thickness of between 3 nm and 500 nm in one of the openings 52a in its insulating bonding layer 52, (2) an adhesion layer 18, such as titanium or titanium nitride having a thickness of between 1 nm and 50 nm, at a bottom and sidewall of the copper layer 24 of said each of its metal pads 6a, and (3) a seed layer 22, such as copper, between the copper layer 24 and adhesion layer 18 of said each of its metal pads 6a, wherein the copper layer 24 of said each of its metal pads 6a may have a top surface substantially coplanar with a top surface of the silicon-oxide layer of its insulating bonding layer 52.

(211) 5. Fifth Type of Semiconductor Integrated-circuit (IC) Chip

(212) Referring to FIG. 14E, a fifth type of semiconductor integrated-circuit (IC) chip 100 may have similar structure as illustrated in FIG. 14D. For an element indicated by the same reference number shown in FIG. 1A-1F, 13A, 14A, 14B, 14D or 14E, the specification of the element as seen in FIG. 14E may be referred to that of the element as illustrated in FIG. 1A-1F, 13A, 14A, 14B or 14D. The difference between the fourth and fifth types of semiconductor integrated-circuit (IC) chips 100 is that the fifth type of semiconductor integrated-circuit (IC) chip 100 may further include multiple through silicon vias (TSVs) 157 as illustrated in FIG. 1A-1F in its semiconductor substrate 2, wherein each of its through silicon vias (TSVs) 157 may couple to one or more of its semiconductor devices 4 through one or more the interconnection metal layers 6 of its first interconnection scheme 560.

(213) 6. Sixth Type of Semiconductor Integrated-circuit (IC) Chip

(214) Referring to FIG. 14F, a sixth type of semiconductor integrated-circuit (IC) chip 100 may have similar structure as illustrated in FIG. 14E. For an element indicated by the same reference number shown in FIG. 1A-1F, 13A, or 14A-14F, the specification of the element as seen in FIG. 14F may be referred to that of the element as illustrated in FIG. 1A-1F, 13A, or 14A-14E. The difference between the fifth and sixth types of semiconductor integrated-circuit (IC) chips 100 is that the sixth type of semiconductor integrated-circuit (IC) chip 100 may be provided with an insulating bonding layer 521 on a backside 2b of its semiconductor substrate 2, wherein the insulating bonding layer 521 may include a silicon-oxide layer having a thickness between 0.1 and 2 For the sixth type of semiconductor integrated-circuit (IC) chip 100, each of its through silicon vias (TSVs) 157 may include the copper layer 156 having a backside substantially coplanar with a bottom surface of its insulating bonding layer 521 and the insulating lining 153 surrounding the adhesion layer 154, seed layer 155 and copper layer 156 of said each of its through silicon vias (TSVs) 157.

(215) Specification for Memory Module (HBM stacked 3D Chip-Scale-Package (CSP)

(216) 1. First Type of Memory Module

(217) FIG. 15A is a schematically cross-sectional view showing a first type of memory module in accordance with an embodiment of the present application. Referring to FIG. 15A, a memory module 159 may include (1) multiple memory chips 251, such as volatile-memory (VM) integrated circuit (IC) chips for a VM module, dynamic-random-access-memory (DRAM) IC chips for a high-bitwidth memory (HBM) module, statistic-random-access-memory (SRAM) IC chips for a SRAM module, magnetoresistive random-access-memory (MRAM) IC chips for a MRAM module, resistive random-access-memory (RRAM) IC chips for a RRAM module, ferroelectric random-access-memory (FRAM) IC chips for a FRAM module or phase change random access memory (PCM) IC chips for a PCM module, vertically stacked together, wherein the number of the memory chips 251 in the memory module 159 may have the number equal to or greater than 2, 4, 8, 16, 32, (2) a control chip 688, i.e., ASIC or logic chip, under the stacked memory chips 251, (3) multiple bonded metal contacts 158 between neighboring two of the memory chips 251 and between the bottommost one of the memory chips 251 and the control chip 688, and (4) multiple micro bumps or micro-pads 34 on a bottom surface of the control chip 688.

(218) Referring to FIG. 15A, each of the memory chips 251 may have the structure as illustrated in FIG. 14C, which may include the through silicon vias (TSVs) 157 in its semiconductor substrate 2, each aligned with and connected to one of the bonded metal contacts 158 at its backside.

(219) FIGS. 16A and 16B are schematically cross-sectional views showing a process of bonding a thermal compression bump to a thermal compression pad in accordance with an embodiment of the present application. For a first case, referring to FIGS. 15A, 16A and 16B, an upper one of the memory chips 251 may have the third type of micro-bumps or micro-pads 34 to be bonded to the fourth type of micro-bumps or micro-pads 570 of a lower one of the memory chips 251. For example, the third type of micro-bumps or micro-pads 34 of the upper one of the memory chips 251 may have the solder caps 38 to be thermally compressed, at a temperature between 240 and 300 degrees Celsius, at a pressure between 0.3 and 3 MPa and for a time period between 3 and 15 seconds, onto the metal caps 49 of the fourth type of micro-bumps or micro-pads 570 of the lower one of the memory chips 251 into multiple bonded metal contacts 158 between the upper and lower ones of the memory chips 251. A force applied to the upper one of the memory chips 251 in the thermal compression process may be substantially equal to the pressure times a contact area between one of the third type of micro-bumps or micro-pads 34 and one of the fourth type of micro-bumps or micro-pads 570 times the total number of the third type of micro-bumps or micro-pads 34 of the upper one of the memory chips 251. Each of the third type of micro-bumps or micro-pads 34 of the upper one of the memory chips 251 may have the copper layer 37 having the thickness t3 greater than the thickness t2 of the copper layer 48 of each of the fourth type of micro-bumps or micro-pads 570 of the lower one of the memory chips 251 and having the largest transverse dimension w3 equal to between 0.7 and 0.1 times of the largest transverse dimension w2 of the copper layer 48 of each of the fourth type of micro-bumps or micro-pads 570 of the lower one of the memory chips 251. Alternatively, each of the third type of micro-bumps or micro-pads 34 may be provided with the copper layer 37 having a cross-sectional area equal to between 0.5 and 0.01 times of the cross-sectional area of the copper layer 48 of each of the fourth type of micro-bumps or micro-pads 570 of the lower one of the memory chips 251. For example, for the upper one of the memory chips 251, its third type of micro-bumps or micro-pads 34 may be formed respectively on a front surface of the metal pads 6b provided by the frontmost one of the interconnection metal layers 27 of its second interconnection scheme 588 or by, if the second interconnection scheme 588 is not provided, the frontmost one of the interconnection metal layers 6 of its first interconnection scheme 560, wherein each of the metal pads 6b may have a thickness t1 between 1 and 10 micrometers or between 2 and 10 micrometers and a largest transverse dimension w1, such as diameter in a circular shape, between 1 μm and 25 μm and each of its third type of micro-bumps or micro-pads 34 may be provided with the copper layer 37 having the thickness t3 greater than the thickness t1 of its metal pads 6b and having the largest transverse dimension w3 equal to between 0.7 and 0.1 times of the largest transverse dimension w1 of its metal pads 6b; alternatively, each of its third type of micro-bumps or micro-pads 34 may be provided with the copper layer 37 having a cross-sectional area equal to between 0.5 and 0.01 times of the cross-sectional area of its metal pads 6b. A bonded solder between the copper layers 37 and 48 of each of the bonded metal contacts 158 may be mostly kept on a top surface of the copper layer 48 of one of the fourth type of micro-bumps or micro-pads 570 of the lower one of the memory chips 251 and extends out of the edge of the copper layer 48 of said one of the fourth type of micro-bumps or micro-pads 570 of the lower one of the memory chips 251 less than 0.5 micrometers. Thus, a short between neighboring two of the bonded metal contacts 158 even in a fine-pitched fashion may be avoided.

(220) Alternatively, for a second case, referring to FIG. 15A, an upper one of the memory chips 251 may have the second type of micro-bumps or micro-pads 34 to be bonded to the first type of micro-bumps or micro-pads 570 of a lower one of the memory chips 251. For example, the second type of micro-bumps or micro-pads 34 of the upper one of the memory chips 251 may have the solder caps 33 to be bonded onto the copper layer 32 of the first type of micro-bumps or micro-pads 570 of the lower one of the memory chips 251 into multiple bonded metal contacts 158 between the upper and lower ones of the memory chips 251. Each of the second type of micro-bumps or micro-pads 34 of the upper one of the memory chips 251 may have the copper layer 32 having a thickness greater than that of the copper layer 32 of each of the first type of micro-bumps or micro-pads 570 of the lower one of the memory chips 251.

(221) Alternatively, for a third case, referring to FIG. 15A, an upper one of the memory chips 251 may have the first type of micro-bumps or micro-pads 34 to be bonded to the second type of micro-bumps or micro-pads 570 of a lower one of the memory chips 251. For example, the first type of micro-bumps or micro-pads 34 of the upper one of the memory chips 251 may have the electroplated metal layer 32, e.g. copper layer, to be bonded onto the solder caps 33 of the second type of micro-bumps or micro-pads 570 of the lower one of the memory chips 251 into multiple bonded metal contacts 158 between the upper and lower ones of the memory chips 251. Each of the first type of micro-bumps or micro-pads 34 of the upper one of the memory chips 251 may have the copper layer 32 having a thickness greater than that of the copper layer 32 of each of the second type of micro-bumps or micro-pads 570 of the lower one of the memory chips 251.

(222) Alternatively, for a fourth case, referring to FIG. 15A, an upper one of the memory chips 251 may have the second type of micro-bumps or micro-pads 34 to be bonded to the second type of micro-bumps or micro-pads 570 of a lower one of the memory chips 251. For example, the second type of micro-bumps or micro-pads 34 of the upper one of the memory chips 251 may have the solder caps 33 to be bonded onto the solder caps 33 of the second type of micro-bumps or micro-pads 570 of the lower one of the memory chips 251 into multiple bonded metal contacts 158 between the upper and lower ones of the memory chips 251. Each of the second type of micro-bumps or micro-pads 34 of the upper one of the memory chips 251 may have the copper layer 32 having a thickness greater than that of the copper layer 32 of each of the second type of micro-bumps or micro-pads 570 of the lower one of the memory chips 251.

(223) Referring to FIG. 15A, each of the through silicon vias (TSVs) 157 of the topmost one of the memory chips 251 may have its sidewall and backside enclosed by its semiconductor substrate 2. The bottommost one of the memory chips 251 may provide the micro-bumps or micro-pads 34 on its bottom surface to be bonded to the micro bumps or micro-pads 570 on a top surface of the control chip 688 into multiple bonded metal contacts 158 between the control chip 688 and the bottommost one of the memory chips 251. The specification of the bonded metal contacts 158 between the control chip 688 and the bottommost one of the memory chips 251 and the process for forming the same may be referred to the specification of those between the upper and lower ones of the memory chips 251 as above illustrated in FIGS. 15A, 16A and 16B and the above-mentioned process for forming the same.

(224) Referring to FIG. 15A, the through silicon vias (TSVs) 157 in the memory chips 251, which are aligned in a vertical direction, may couple to each other or one another through the bonded metal contacts 158 therebetween aligned in the vertical direction and with the through silicon vias (TSVs) 157 therein in the vertical direction. Each of the memory chips 251 and control chip 688 may include multiple interconnects 696 each provided by the interconnection metal layers 6 of its first interconnection scheme 560 and/or the interconnection metal layers 27 of its second interconnection scheme 588 to connect one or more of its through silicon vias (TSVs) 157 to one or more of the bonded metal contacts 158 at its bottom surface. An underfill 694, e.g., a polymer layer, may be provided between each neighboring two of the memory chips 251 to enclose the bonded metal contacts 158 therebetween and between the bottommost one of the memory chips 251 and the control chip 688 to enclose the bonded metal contacts 158 therebetween. A molding compound 695, e.g. a polymer, may be formed around the memory chips 251 and over the control chip 688, wherein the topmost one of the memory chips 251 may have a top surface coplanar with a top surface of the molding compound 695.

(225) Referring to FIG. 15A, for the first type of memory module 159, each of its memory chips 251 may have a data bit-width, equal to or greater than 64, 128, 256, 512, 1024, 2048, 4096, 8K, or 16K, with external circuits of the first type of memory module 159 via its micro-bumps or micro-pads 34. The first type of memory module 159 may include multiple vertical interconnects 699 each composed of one of the through silicon vias (TSVs) 157 in each of the memory chips 251 of the first type of memory module 159, wherein for each of the vertical interconnects 699 of the first type of memory module 159, its through silicon vias (TSVs) 157 in the memory chips 251 of the first type of memory module 159 are aligned with each other or one another and are connected to one or more transistors of the semiconductor devices 4 of the memory chips 251 of the first type of memory module 159. Each of the memory chips 251 and control chip 688 may be provided with one or more small I/O circuits, each having driving capability, loading, output capacitance or input capacitance between 0.05 pF and 2 pF, or 0.05 pF and 1 pF, or smaller than 2 pF or 1 pF, coupling to one of the vertical interconnects 699 of the first type of memory module 159. alternatively each of the small input/output (I/O) circuits may have an I/O power efficiency smaller than 0.5 pico-Joules per bit, per switch or per voltage swing, or between 0.01 and 0.5 pico-Joules per bit, per switch or per voltage swing,

(226) Referring to FIG. 15A, the control chip 688 may be configured to control data access to the memory chips 251. The control chip 688 may be used for buffering and controlling the memory chips 251. The control chip 688 may include the through silicon vias (TSVs) 157 in its semiconductor substrate 2, each aligned with and connected to one or more of its micro-bumps or micro-pads 34 on its bottom surface.

(227) Alternatively, FIG. 15C is a schematically cross-sectional view showing a first type of memory module in accordance with another embodiment of the present application. Referring to FIG. 15C, the first type of memory module 159 may have a structure similar to that as illustrated in FIG. 15A. For an element indicated by the same reference number shown in FIGS. 15A and 15C, the specification of the element as seen in FIG. 15C may be referred to that of the element as illustrated in FIG. 15A. The difference between the first type of memory modules 159 as seen in FIGS. 15A and 15C is that a direct bonding process may be performed for the first type of memory module 159 as seen in FIG. 15C. FIGS. 16C and 16D are schematically cross-sectional views showing a direct bonding process in accordance with an embodiment of the present application. Referring to FIGS. 15C, 16C and 16D, each of the memory chips 251 and control chip 688 may have the structure as illustrated in FIG. 14F, which may include the through silicon vias (TSVs) 157 in its semiconductor substrate 2 each aligned with its metal pads 6a at its active side. An upper one of the memory chips 251 may join a lower one of the memory chips 251 and control chip 688 by (1) activating a joining surface, i.e., silicon oxide, of the insulating bonding layer 52 at the active side of the upper one of the memory chips 251 and a joining surface, i.e., silicon oxide, of the insulating bonding layer 521 at the backside of the lower one of the memory chips 251 and control chip 688 with nitrogen plasma for increasing hydrophilic property thereof, (2) next rinsing the joining surface of the insulating bonding layer 52 at the active side of the upper one of the memory chips 251 and the joining surface of the insulating bonding layer 521 at the backside of the lower one of the memory chips 251 and control chip 688 with deionized water for water adsorption and cleaning, (3) next placing the upper one of the memory chips 251 onto the lower one of the memory chips 251 and control chip 688 with each of the metal pads 6a at the active side of the upper one of the memory chips 251 in contact with one of the through silicon vias (TSVs) 157 of the lower one of the memory chips 251 and control chip 688 and with the joining surface of the insulating bonding layer 52 at the active side of the upper one of the memory chips 251 in contact with the joining surface of the insulating bonding layer 521 at the backside of the lower one of the memory chips 251 and control chip 688, and (4) next performing a direct bonding process including (a) oxide-to-oxide bonding at a temperature between 100 and 200 degrees Celsius and for a time period between 5 and 20 minutes to bond the joining surface of the insulating bonding layer 52 at the active side of the upper one of the memory chips 251 to the joining surface of the insulating bonding layer 521 at the backside of the lower one of the memory chips 251 and control chip 688 and (b) copper-to-copper bonding at a temperature between 300 and 350 degrees Celsius and for a time period between 10 and 60 minutes to bond the copper layer 24 of each of the metal pads 6a at the active side of the upper one of the memory chips 251 to the copper layer 156 of one of the through silicon vias (TSVs) 157 of the lower one of the memory chips 251 and control chip 688, wherein the oxide-to-oxide bonding may be caused by water desorption from reaction between the joining surface of the insulating bonding layer 52 at the active side of the upper one of the memory chips 251 and the joining surface of the insulating bonding layer 521 at the backside of the lower one of the memory chips 251, and the copper-to-copper bonding may be caused by metal inter-diffusion between the copper layer 24 of the metal pads 6a at the active side of the upper one of the memory chips 251 and the copper layer 156 of the through silicon vias (TSVs) 157 of the lower one of the memory chips 251 and control chip 688.

(228) 2. Second Type of Memory Module

(229) FIGS. 15B and 15D are schematically cross-sectional views showing various second type of memory modules in accordance with an embodiment of the present application. Referring to FIG. 15B, the second type of memory module 159 may have a structure similar to that as illustrated in FIG. 15A. For an element indicated by the same reference number shown in FIGS. 15A and 15B, the specification of the element as seen in FIG. 15B may be referred to that of the element as illustrated in FIG. 15A. Referring to FIG. 15D, the second type of memory module 159 may have a structure similar to that as illustrated in FIG. 15C. For an element indicated by the same reference number shown in FIGS. 15A, 15C and 15D, the specification of the element as seen in FIG. 15D may be referred to that of the element as illustrated in FIG. 15A or 15C. The difference between the first and second types of memory modules 159 is that the second type of memory module 159 may further include multiple dedicated vertical bypasses 698 each composed of one of the through silicon vias (TSVs) 157 in each of the memory chips 251 and control chip 688 of the second type of memory module 159, wherein for each of the dedicated vertical bypasses 698 of the second type of memory module 159, its through silicon vias (TSVs) 157 in the memory chips 251 and control chip 688 of the second type of memory module 159 are aligned with each other or one another and are not connected to any transistor of the memory chips 251 or control chip 688 of the second type of memory module 159.

(230) Process for Fabricating Operation Unit

(231) 1. First Type of Operation Unit for Second Type of Chip-on-chip (COC) Component or Package

(232) FIGS. 17A-17F are schematically cross-sectional views showing a process for fabricating a first type of operation unit in accordance with an embodiment of the present application. Referring to FIG. 17A, a semiconductor wafer 100c may be provided at an active side thereof with the insulating bonding layer 52 and metal pads 6a as illustrated in FIG. 14D, wherein neighboring two of the metal pads 6a of the semiconductor wafer 100c may have a pitch between 3 and 10 micrometers or between 4 and 7 micrometers. Next, referring to FIGS. 17A and 17B, each of first or second type of memory modules 159 may have the same structure as illustrated in FIG. 15C or 15D provided with the insulating bonding layer 52 to be bonded to the insulating bonding layer 52 of the semiconductor wafer 100c and the metal pads 6a, neighboring two of which may have a pitch between 3 and 10 micrometers or between 4 and 7 micrometers, to be bonded to the metal pads 6a of the semiconductor wafer 100c. Each of known-good memory, logic or application-specific-integrated-circuit (ASIC) chips 121 may have the structure as illustrated in FIG. 14E provided at an active side thereof with the insulating bonding layer 52 to be bonded to the insulating bonding layer 52 of the semiconductor wafer 100c and the metal pads 6a, neighboring two of which may have a pitch between 3 and 10 micrometers or between 4 and 7 micrometers, to be bonded to the metal pads 6a of the semiconductor wafer 100c. For example, each of the known-good memory, logic or application-specific-integrated-circuit (ASIC) chips 121 may be (1) an application specific integrated-circuit (ASIC) logic chip, (2) a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip 200 as illustrated in FIG. 9 or dedicated programmable interconnection (DPI) integrated-circuit (IC) chip 410 as illustrated in FIG. 10, (3) a processing and/or computing integrated-circuit (IC) chip, such as graphic-processing-unit (GPU) integrated-circuit (IC) chip, central-processing-unit (CPU) integrated-circuit (IC) chip, tensor-processing-unit (TPU) integrated-circuit (IC) chip, network-processing-unit (NPU) integrated-circuit (IC) chip, application-processing-unit (APU) integrated-circuit (IC) chip, digital-signal-processing (DSP) integrated-circuit (IC) chip, (4) a memory integrated-circuit (IC) chip, such as non-volatile NAND chip, non-volatile NOR flash chip, non-volatile magnetoresistive random-access-memory (MRAM) integrated-circuit (IC) chip, non-volatile resistive random access memory (RRAM) integrated-circuit (IC) chip, non-volatile phase-change random-access-memory (PCM) integrated-circuit (IC) chip, non-volatile ferroelectric-random-access-memory (FRAM) integrated-circuit (IC) chip or high bandwidth dynamic random-access-memory (DRAM) or static random-access-memory (SRAM) memory (HBM) chip, (5) an auxiliary and supporting (AS) integrated-circuit (IC) chip 411 as illustrated in FIG. 11, (6) an IAC IC chip 402 as illustrated in FIG. 12A, (7) a dedicated I/O chip 265 or dedicated control and I/O chip 260 as illustrated in FIGS. 12A and 12B, or (8) a power management integrated-circuit (IC) chip. Multiple second type of vertical-through-via (VTV) connectors 467, each of which may be one as illustrated in any of FIGS. 1B, 1D, 1F, 2B, 2D and 2F, may be provided with the insulating bonding layer 52 to be bonded to the insulating bonding layer 52 of the semiconductor wafer 100c and the vertical through vias (VTVs) 358, neighboring two of which may have a pitch between 3 and 10 micrometers or between 4 and 7 micrometers, to be bonded to the metal pads 6a of the semiconductor wafer 100c.

(233) Referring to FIGS. 17A and 17B, before the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the second type of vertical-through-via (VTV) connectors 467 are bonded to the semiconductor wafer 100c, a joining surface, i.e., silicon oxide, of the insulating bonding layer 52 at the active side of the semiconductor wafer 100c may be activated with nitrogen plasma for increasing a hydrophilic property thereof, and then the joining surface of the insulating bonding layer 52 at the active side of the semiconductor wafer 100c may be rinsed with deionized water for water adsorption and cleaning. Further, a joining surface, i.e., silicon oxide, of the insulating bonding layer 52 at the active side of the control chip 688 of each of the first or second type of memory modules 159, a joining surface, i.e., silicon oxide, of the insulating bonding layer 52 at the active side of each of the known-good memory, logic or ASIC chips 121 and a joining surface, i.e., silicon oxide, of the insulating bonding layer 52 of each of the second type of vertical-through-via (VTV) connectors 467 may be activated with nitrogen plasma for increasing a hydrophilic property thereof, and then the joining surface of the insulating bonding layer 52 at the active side of the control chip 688 of each of the first or second type of memory modules 159, the joining surface of the insulating bonding layer 52 at the active side of each of the known-good memory, logic or ASIC chips 121, and the joining surface of the insulating bonding layer 52 of each of the second type of vertical-through-via (VTV) connectors 467 may be rinsed with deionized water for water adsorption and cleaning.

(234) Next, referring to FIGS. 17A and 17B, the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the second type of vertical-through-via (VTV) connectors 467 may be bonded to the semiconductor wafer 100c by (1) picking up each of the first or second type of memory modules 159 to be placed on the semiconductor wafer 100c with each of the metal pads 6a at the active side of the control chip 688 of each of the first or second type of memory modules 159 in contact with one of the metal pads 6a at the active side of the semiconductor wafer 100c and with the joining surface of the insulating bonding layer 52 at the active side of the control chip 688 of each of the first or second type of memory modules 159 in contact with the joining surface of the insulating bonding layer 52 at the active side of the semiconductor wafer 100c, (2) picking up each of the known-good memory, logic or ASIC chips 121 to be placed on the semiconductor wafer 100c with each of the metal pads 6a at the active side of each of the known-good memory, logic or ASIC chips 121 in contact with one of the metal pads 6a at the active side of the semiconductor wafer 100c and with the joining surface of the insulating bonding layer 52 at the active side of each of the known-good memory, logic or ASIC chips 121 in contact with the joining surface of the insulating bonding layer 52 at the active side of the semiconductor wafer 100c, (3) picking up each of the second type of vertical-through-via (VTV) connectors 467 to be placed on the semiconductor wafer 100c with each of the vertical through vias (VTVs) 358 of each of the second type of vertical-through-via (VTV) connectors 467 in contact with one of the metal pads 6a at the active side of the semiconductor wafer 100c and with the joining surface of the insulating bonding layer 52 of each of the second type of vertical-through-via (VTV) connectors 467 in contact with the joining surface of the insulating bonding layer 52 at the active side of the semiconductor wafer 100c, and (4) next performing a direct bonding process including (a) oxide-to-oxide bonding at a temperature between 100 and 200 degrees Celsius and for a time period between 5 and 20 minutes to bond the joining surface of the insulating bonding layer 52 at the active side of the control chip 688 of each of the first or second type of memory modules 159, the joining surface of the insulating bonding layer 52 at the active side of each of the known-good memory, logic or ASIC chips 121 and the joining surface of the insulating bonding layer 52 of each of the second type of vertical-through-via (VTV) connectors 467 to the joining surface of the insulating bonding layer 52 at the active side of the semiconductor wafer 100c and (b) copper-to-copper bonding at a temperature between 300 and 350 degrees Celsius and for a time period between 10 and 60 minutes to bond the copper layer 24 of each of the metal pads 6a at the active side of the control chip 688 of each of the first or second type of memory modules 159 to the copper layer 24 of one of the metal pads 6a at the active side of the semiconductor wafer 100c, to bond the copper layer 24 of each of the metal pads 6a at the active side of each of the known-good memory, logic or ASIC chips 121 to the copper layer 24 of one of the metal pads 6a at the active side of the semiconductor wafer 100c and to bond the copper layer 24 of each of the vertical through vias (VTVs) 358 of each of the second type of vertical-through-via (VTV) connectors 467 to the copper layer 24 of one of the metal pads 6a at the active side of the semiconductor wafer 100c. The oxide-to-oxide bonding may be caused by water desorption from reaction between the joining surface of the insulating bonding layer 52 at the active side of the control chip 688 of each of the first or second type of memory modules 159 and the joining surface of the insulating bonding layer 52 at the active side of the semiconductor wafer 100c, between the joining surface of the insulating bonding layer 52 at the active side of each of the known-good memory, logic or ASIC chips 121 and the joining surface of the insulating bonding layer 52 at the active side of the semiconductor wafer 100c and between the joining surface of the insulating bonding layer 52 of each of the second type of vertical-through-via (VTV) connectors 467 and the joining surface of the insulating bonding layer 52 at the active side of the semiconductor wafer 100c. The copper-to-copper bonding may be caused by metal inter-diffusion between the copper layer 24 of the metal pads 6a at the active side of the control chip 688 of each of the first or second type of memory modules 159 and the copper layer 24 of the metal pads 6a at the active side of the semiconductor wafer 100c, between the copper layer 24 of the metal pads 6a at the active side of each of the known-good memory, logic or ASIC chips 121 and the copper layer 24 of the metal pads 6a at the active side of the semiconductor wafer 100c and between the copper layer 24 of the vertical through vias (VTVs) 358 of each of the second type of vertical-through-via (VTV) connectors 467 and the copper layer 24 of the metal pads 6a at the active side of the semiconductor wafer 100c.

(235) Next, referring to FIG. 17C, a polymer layer 565, e.g., resin or compound, may be applied to fill a gap between each neighboring two of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the second type of vertical-through-via (VTV) connectors 467 and to cover a backside of each of the first or second type of memory modules 159, a backside of each of the known-good memory, logic or ASIC chips 121 and a backside of each of the second type of vertical-through-via (VTV) connectors 467 by methods, for example, spin-on coating, screen-printing, dispensing or molding. The polymer layer 565 may be, for example, polyimide, BenzoCycloButene (BCB), parylene, parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer, or silicone. The polymer layer 565 may be, for example, photosensitive polyimide/PBO PIMEL™ supplied by Asahi Kasei Corporation, Japan, or epoxy-based molding compounds, resins or sealants provided by Nagase ChemteX Corporation, Japan. The polymer layer 565 may be cured or cross-linked at a temperature higher than or equal to 50, 70, 90, 100, 125, 150, 175, 200, 225, 250, 275 or 300 degrees Celsius.

(236) Next, referring to FIG. 17D, a chemical mechanical polishing (CMP), polishing or grinding process may be applied to remove a top portion of the polymer layer 565, a top portion of each of the first or second type of memory modules 159, a top portion of each of the known-good memory, logic or ASIC chips 121 and a top portion of each of the second type of vertical-through-via (VTV) connectors 467, to planarize a top surface of the polymer layer 565, a top surface of each of the first or second type of memory modules 159, a top surface of each of the known-good memory, logic or ASIC chips 121 and a top surface of each of the second type of vertical-through-via (VTV) connectors 467 and to expose a backside of each of the vertical through vias (VTVs) 358 of each of the second type of vertical-through-via (VTV) connectors 467, a backside of the copper layer 156 of each of the through silicon vias (TSVs) 157 of the topmost one of the memory chips 251 of each of the first or second type of memory modules 159 and a backside of the copper layer 156 of each of the through silicon vias (TSVs) 157 of each of the known-good memory, logic or ASIC chips 121.

(237) For each of the through silicon vias (TSVs) 157 of the topmost one of the memory chips 251 of said each of the first or second type of memory modules 159 and the through silicon vias (TSVs) 157 of said each of the known-good memory, logic or ASIC chips 121, its insulating lining layer 153, adhesion layer 154 and seed layer 155 at its backside may be removed to expose a backside of its copper layer 156, which may be coplanar with a backside of said each of the first or second type of memory modules 159, a backside of said each of the known-good memory, logic or ASIC chips 121 and a top surface of the polymer layer 565, and its insulating lining layer 153, adhesion layer 154 and seed layer 155 at a sidewall of its copper layer 156 may be left. For each of the vertical through vias (VTVs) 358 of said each of the second type of vertical-through-via (VTV) connectors 467, if made of one or more of the through silicon vias (TSVs) 157 as illustrated in one of FIGS. 1B, 1D, 1E, 2B, 2D and 2E, its insulating lining layer 153, adhesion layer 154 and seed layer 155 at its backside may be removed to expose a backside of its copper layer 156, which may be coplanar with a backside of said each of the second type of vertical-through-via (VTV) connectors 467 and a top surface of the polymer layer 565, and its insulating lining layer 153, adhesion layer 154 and seed layer 155 at a sidewall of its copper layer 156 may be left.

(238) Next, referring to FIG. 17E, an insulating dielectric layer 93 may be formed on the top surface of the polymer layer 565, the backside of each of the first or second type of memory modules 159, the backside of each of the known-good memory, logic or ASIC chips 121 and the backside of each of the second type of vertical-through-via (VTV) connectors 467. Each opening in the insulating dielectric layer 93 may be vertically over the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of the topmost one of the memory chips 251 of one of the first or second type of memory modules 159, the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of one of the known-good memory, logic or ASIC chips 121 or the backside of one of the vertical through vias (VTVs) 358 of one of the second type of vertical-through-via (VTV) connectors 467. The insulating dielectric layer 93 may be a layer of polymer, such as polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer or silicone, having a thickness between 3 and 30 micrometers or between 5 and 15 micrometers.

(239) Next, referring to FIG. 17E, each micro-bump or micro-pad 197, which may be of one of the first through fourth types having the same specifications as the first through fourth types of micro-bumps or micro-pads 34 as illustrated in FIG. 1A, 1C or 1E respectively, may be formed on the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of the topmost one of the memory chips 251 of one of the first or second type of memory modules 159, the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of one of the known-good memory, logic or ASIC chips 121 or the backside of one of the vertical through vias (VTVs) 358 of one of the second type of vertical-through-via (VTV) connectors 467. Said each micro-bump or micro-pad 197 may be of the first type, including (1) an adhesion layer 26a, such as titanium (Ti) or titanium nitride (TiN) layer having a thickness between 1 nm and 50 nm, on the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of the topmost one of the memory chips 251 of one of the first or second type of memory modules 159, the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of one of the known-good memory, logic or ASIC chips 121 or the backside of the copper layer 156 of one of the vertical through vias (VTVs) 358 of one of the second type of vertical-through-via (VTV) connectors 467, (2) a seed layer 26b, such as copper, on its adhesion layer 26a and (3) a copper layer 32 having a thickness between 1 μm and 60 μm on its seed layer 26b.

(240) Alternatively, referring to FIG. 17E, said each micro-bump or micro-pad 197 may be of the second type, including the adhesion layer 26a, seed layer 26b and copper layer 32 as mentioned above, and further including, as seen in FIG. 17E, a tin-containing solder cap 33 made of tin or a tin-silver alloy having a thickness between 1 μm and 50 μm on its copper layer 32.

(241) Alternatively, referring to FIG. 17E, said each micro-bump or micro-pad 197 may be of the third type used as a thermal compression bump, including the adhesion layer 26a and seed layer 26b as mentioned above, and further including, as seen in any of 16A, 18A, 28A, 29A, 35A and 36A, a copper layer 37 having a thickness t3 between 2 μm and 20 μm and a largest transverse dimension w3, such as diameter in a circular shape, between 1 μm and 25 μm on its seed layer 26b and a solder cap 38 made of a tin-silver alloy, a tin-gold alloy, a tin-copper alloy, a tin-indium alloy, indium or tin, which has a thickness between 1 μm and 15 μm and a largest transverse dimension, such as diameter in a circular shape, between 1 μm and 15 μm on its copper layer 37. A pitch between neighboring two of the third type of micro-bumps or micro-pads 197 may be between 5 and 30 micrometers or between 10 and 25 micrometers.

(242) Alternatively, referring to FIG. 17E, said each micro-bump or micro-pad 197 may be of the fourth type used as a thermal compression pad, including the adhesion layer 26a and seed layer 26b as mentioned above, and further including, as seen in FIG. 18A, a copper layer 48 having a thickness t2 between 1 μm and 20 μm or between 2 μm and 10 μm and a largest transverse dimension w2, such as diameter in a circular shape, between 5 μm and 50 μm, on its seed layer 26b and a solder cap 49 made of a tin-silver alloy, a tin-gold alloy, a tin-copper alloy, a tin-indium alloy, indium, tin or gold, which has a thickness between 0.1 μm and 5 μm on its copper layer 48. A pitch between neighboring two of the fourth type of micro-bumps or micro-pads 197 may be between 5 and 30 micrometers or between 10 and 25 micrometers.

(243) Next, referring to FIG. 17E, the semiconductor wafer 100c, polymer layer 565 and insulating dielectric layer 93 may be cut or diced to form multiple first type of operation units 190 each for a second type of chip-on-chip (COC) component or package, as shown in FIG. 17F by a laser cutting process or by a mechanical cutting process. At this time, the semiconductor wafer 100c may be cut or diced into multiple semiconductor integrated-circuit (IC) chips 399, each of which may have the same specification as the semiconductor integrated-circuit (IC) chip 100 as illustrated in FIG. 14D and may be (1) an application specific integrated-circuit (ASIC) logic chip, (2) a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip 200 as illustrated in FIG. 9 or dedicated programmable interconnection (DPI) integrated-circuit (IC) chip 410 as illustrated in FIG. 10, (3) a processing and/or computing integrated-circuit (IC) chip, such as graphic-processing-unit (GPU) integrated-circuit (IC) chip, central-processing-unit (CPU) integrated-circuit (IC) chip, tensor-processing-unit (TPU) integrated-circuit (IC) chip, network-processing-unit (NPU) integrated-circuit (IC) chip, application-processing-unit (APU) integrated-circuit (IC) chip, digital-signal-processing (DSP) integrated-circuit (IC) chip, (4) a memory integrated-circuit (IC) chip, such as non-volatile NAND chip, non-volatile NOR flash chip, non-volatile magnetoresistive random-access-memory (MRAM) integrated-circuit (IC) chip, non-volatile resistive random access memory (RRAM) integrated-circuit (IC) chip, non-volatile phase-change random-access-memory (PCM) integrated-circuit (IC) chip, non-volatile ferroelectric-random-access-memory (FRAM) integrated-circuit (IC) chip or high bandwidth dynamic random-access-memory (DRAM) or static random-access-memory (SRAM) memory (HBM) chip, (5) an auxiliary and supporting (AS) integrated-circuit (IC) chip 411 as illustrated in FIG. 11, (6) an IAC IC chip 402 as illustrated in FIG. 12A, (7) a dedicated I/O chip 265 or dedicated control and I/O chip 260 as illustrated in FIGS. 12A and 12B, or (8) a power management integrated-circuit (IC) chip.

(244) Alternatively, FIG. 17G is a schematically cross-sectional view showing a first type of operation unit in accordance with another embodiment of the present application. For an element indicated by the same reference number shown in FIGS. 17A-17G, the specification of the element as seen in FIG. 17G may be referred to that of the element as illustrated in FIGS. 17A-17F. Referring to FIG. 17G, the semiconductor wafer 100c may be provided at an active side thereof with the first, second or fourth type of micro-bumps or micro-pads 34, as illustrated in FIG. 14A, instead of the insulating bonding layer 52 and metal pads 6a. Each of the first or second type of memory modules 159 (only one is shown) formed as illustrated in FIG. 15A or 15B respectively may have the first, second or third type of micro-bumps or micro-pads 34 to be bonded to the first, second or fourth type of micro-bumps or micro-pads 34 preformed at an active side of the semiconductor wafer 100c into multiple bonded metal contacts 563 respectively therebetween. Each of the known-good memory, logic or ASIC chips 121 (only one is shown) may have the structure as illustrated in FIG. 14B provided at an active side thereof with the first, second or third type of micro-bumps or micro-pads 34 to be bonded to the first, second or fourth type of micro-bumps or micro-pads 34 preformed at an active side of the semiconductor wafer 100c into multiple bonded metal contacts 563 respectively therebetween. Each of the first type of vertical-through-via (VTV) connectors 467 as illustrated in any of FIGS. 1A, 1C, 1E, 2A, 2C, 2E, 4A, 4B, 4C, 5A, 5B, 5C and 6 may be provided with the first, second, third, fifth or sixth type of micro-bumps or micro-pads 34 to be bonded to the first, second or fourth type of micro-bumps or micro-pads 34 preformed at the active side of the semiconductor wafer 100c into multiple bonded metal contacts 563 respectively therebetween.

(245) FIGS. 18A and 18B are schematically cross-sectional views showing a process of bonding a thermal compression bump to a thermal compression pad in accordance with an embodiment of the present application. For a first case, referring to FIGS. 17G, 18A and 18B, each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may have the third type of micro-bumps or micro-pads 34 to be bonded to the fourth type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c. For example, the third type of micro-bumps or micro-pads 34 of said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may have the solder caps 38 to be thermally compressed, at a temperature between 240 and 300 degrees Celsius, at a pressure between 0.3 and 3 Mpa and for a time period between 3 and 15 seconds, onto the metal caps 49 of the fourth type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c into multiple bonded metal contacts 563 between said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 and the semiconductor wafer 100c, wherein neighboring two of the bonded metal contacts 563 may have a pitch between 5 and 30 micrometers or 10 and 25 micrometers. Each of the third type of micro-bumps or micro-pads 34 of said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may have the copper layer 37 having the thickness t3 greater than the thickness t2 of the copper layer 48 of each of the fourth type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c and having the largest transverse dimension w3 equal to between 0.7 and 0.1 times of the largest transverse dimension w2 of the copper layer 48 of each of the fourth type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c. Alternatively, each of the third type of micro-bumps or micro-pads 34 of said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may be provided with the copper layer 37 having a cross-sectional area equal to between 0.5 and 0.01 times of the cross-sectional area of the copper layer 48 of each of the fourth type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c.

(246) For example, referring to FIGS. 17G, 18A and 18B, for each of the first or second type of memory modules 159, its third type of micro-bumps or micro-pads 34 may be formed respectively on a front surface of the metal pads 6b provided by the frontmost one of the interconnection metal layers 27 of the second interconnection scheme 588 of its control chip 688 or by, if the second interconnection scheme 588 is not provided for its control chip 688, the frontmost one of the interconnection metal layers 6 of the first interconnection scheme 560 of its control chip 688, wherein each of its third type of micro-bumps or micro-pads 34 may be provided with the copper layer 37 having the thickness t3 greater than the thickness t1 of each of the metal pads 6b of its control chip 688 and having the largest transverse dimension w3 equal to between 0.7 and 0.1 times of the largest transverse dimension w1 of each of the metal pads 6b of its control chip 688; alternatively, each of its third type of micro-bumps or micro-pads 34 may be provided with the copper layer 37 having a cross-sectional area equal to between 0.5 and 0.01 times of the cross-sectional area of each of the metal pads 6b of its control chip 688; each of the metal pads 6b of its control chip 688 may have a thickness t1 between 1 and 10 micrometers or between 2 and 10 micrometers and a largest transverse dimension w1, such as diameter in a circular shape, between 1 μm and 25 μm. For each of the known-good memory, logic or ASIC chips 121, its third type of micro-bumps or micro-pads 34 may be formed respectively on a front surface of the metal pads 6b provided by the frontmost one of the interconnection metal layers 27 of its second interconnection scheme 588 or by, if its second interconnection scheme 588 is not provided, the frontmost one of the interconnection metal layers 6 of its first interconnection scheme 560, wherein each of its third type of micro-bumps or micro-pads 34 may be provided with the copper layer 37 having the thickness t3 greater than the thickness t1 of each of its metal pads 6b and having the largest transverse dimension w3 equal to between 0.7 and 0.1 times of the largest transverse dimension w1 of each of its metal pads 6b; alternatively, each of its third type of micro-bumps or micro-pads 34 may be provided with the copper layer 37 having a cross-sectional area equal to between 0.5 and 0.01 times of the cross-sectional area of each of its metal pads 6b; each of its metal pads 6b may have a thickness t1 between 1 and 10 micrometers or between 2 and 10 micrometers and a largest transverse dimension w1, such as diameter in a circular shape, between 1 μm and 25 μm. A bonded solder between the copper layers 37 and 48 of each of the bonded metal contacts 563 may be mostly kept on a top surface of the copper layer 48 of one of the fourth type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c and extends out of the edge of the copper layer 48 of said one of the fourth type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c less than 0.5 micrometers. Thus, a short between neighboring two of the bonded metal contacts 563 even in a fine-pitched fashion may be avoided.

(247) Alternatively, for a second case, referring to FIG. 17G, each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may have the second type of micro-bumps or micro-pads 34 to be bonded to the first type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c. For example, the second type of micro-bumps or micro-pads 34 of said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may have the solder caps 33 to be bonded onto the copper layer 32 of the first type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c into multiple bonded metal contacts 563 between said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 and the semiconductor wafer 100c. Each of the second type of micro-bumps or micro-pads 34 of said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may have the copper layer 32 having a thickness greater than that of the copper layer 32 of each of the first type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c.

(248) Alternatively, for a third case, referring to FIG. 17G, each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may have the first type of micro-bumps or micro-pads 34 to be bonded to the second type of metal bumps or pillars 34 of the semiconductor wafer 100c. For example, the first type of micro-bumps or micro-pads 34 of said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may have the electroplated metal layer 32, e.g. copper layer, to be bonded onto the solder caps 33 of the second type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c into multiple bonded metal contacts 563 between said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 and the semiconductor wafer 100c. Each of the first type of micro bumps or micro-pads 34 of said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may have the copper layer 32 having a thickness greater than that of the copper layer 32 of each of the second type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c.

(249) Alternatively, for a fourth case, referring to FIG. 17G, each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may have the second type of micro-bumps or micro-pads 34 to be bonded to the second type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c. For example, the second type of micro-bumps or micro-pads 34 of said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may have the solder caps 33 to be bonded onto the solder caps 33 of the second type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c into multiple bonded metal contacts 563 between said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 and the semiconductor wafer 100c. Each of the second type of micro-bumps or micro-pads 34 of said each of the first or second type of memory modules 159, the known-good memory, logic or ASIC chips 121 and the first type of vertical-through-via (VTV) connectors 467 may have the copper layer 32 having a thickness greater than that of the copper layer 32 of each of the second type of micro-bumps or micro-pads 34 of the semiconductor wafer 100c.

(250) Next, referring to FIG. 17G, an underfill 564, such as a layer of polymer or epoxy resins or compounds, may be filled into a gap between each of the first or second type of memory modules 159 and the semiconductor wafer 100c to enclose the bonded metal contacts 563 therebetween, into a gap between each of the known-good memory, logic or ASIC chips 121 and the semiconductor wafer 100c to enclose the bonded metal contacts 563 therebetween and into a gap between each of the first type of vertical-through-via (VTV) connectors 467 and the semiconductor wafer 100c to enclose the bonded metal contacts 563 therebetween. The underfill 564 may be cured at temperature equal to or above 100, 120 or 150 degrees Celsius.

(251) Referring to FIG. 17G, the following process may be referred to the process as illustrated in FIGS. 17C-17F. When the chemical mechanical polishing (CMP), polishing or grinding process as illustrated in FIG. 17D is performed, for each of the vertical through vias (VTVs) 358 of said each of the first type of vertical-through-via (VTV) connectors 467, if made of one or more of the through silicon vias (TSVs) 157 as illustrated in one of FIGS. 1A, 1C, 1E, 2A, 2C and 2E for the first and second alternatives, its insulating lining layer 153, adhesion layer 154 and seed layer 155 at its backside may be removed to expose a backside of its copper layer 156, which may be coplanar with a backside of said each of the first type of vertical-through-via (VTV) connectors 467 and a top surface of the polymer layer 565, and its insulating lining layer 153, adhesion layer 154 and seed layer 155 at a sidewall of its copper layer 156 may be left; for each of the vertical through vias (VTVs) 358 of said each of the first type of vertical-through-via (VTV) connectors 467, if made of one or more of the through glass vias (TGVs) 259 as illustrated in one of FIGS. 4A, 4B, 4C, 5A, 5B and 5C for the third and fourth alternatives, a backside of its copper post 706 may be exposed with being coplanar with a backside of said each of the first type of vertical-through-via (VTV) connectors 467 and the top surface of the polymer layer 565; for each of the vertical through vias (VTVs) 358 of said each of the first type of vertical-through-via (VTV) connectors 467, if made of one or more of the through polymer vias (TPVs) 318 as illustrated in FIG. 6 for the fifth alternative, a backside of its metal pad 336 or copper post 318 may be exposed with being coplanar with a backside of said each of the first type of vertical-through-via (VTV) connectors 467 and the top surface of the polymer layer 565.

(252) Next, referring to FIG. 17G, each of the micro-bumps or micro-pads 197, which may be of one of the first through fourth types having the same specifications as the first through fourth types of micro-bumps or micro-pads 197 as illustrated in FIG. 17E respectively, may include the adhesion layer 26a on the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of the topmost one of the memory chips 251 of one of the first or second type of memory modules 159, the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of one of the known-good memory, logic or ASIC chips 121 or the backside of one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467. Said each micro-bump or micro-pad 197 may be any of the first through fourth types, including (1) the adhesion layer 26a, such as titanium (Ti) or titanium nitride (TiN) layer having a thickness between 1 nm and 50 nm, on the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of the topmost one of the memory chips 251 of one of the first or second type of memory modules 159, the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of one of the known-good memory, logic or ASIC chips 121, the backside of the copper layer 156 of one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 for the first and second alternatives, the backside of the copper post 706 of one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 for the third and fourth alternatives or the backside of the metal pad 336 or copper post 318 of one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 for the fifth alternative.

(253) Next, the semiconductor wafer 100c, polymer layer 565 and insulating dielectric layer 93 may be cut or diced to form multiple first type of operation units 190 each for a second type of chip-on-chip (COC) component or package, as shown in FIG. 17G by a laser cutting process or by a mechanical cutting process. At this time, the semiconductor wafer 100c may be cut or diced into multiple semiconductor integrated-circuit (IC) chips 399, each of which may have the same specification as the semiconductor integrated-circuit (IC) chip 100 as illustrated in FIG. 14A or 14B and may be (1) an application specific integrated-circuit (ASIC) logic chip, (2) a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip 200 as illustrated in FIG. 9 or dedicated programmable interconnection (DPI) integrated-circuit (IC) chip 410 as illustrated in FIG. 10, (3) a processing and/or computing integrated-circuit (IC) chip, such as graphic-processing-unit (GPU) integrated-circuit (IC) chip, central-processing-unit (CPU) integrated-circuit (IC) chip, tensor-processing-unit (TPU) integrated-circuit (IC) chip, network-processing-unit (NPU) integrated-circuit (IC) chip, application-processing-unit (APU) integrated-circuit (IC) chip, digital-signal-processing (DSP) integrated-circuit (IC) chip, (4) a memory integrated-circuit (IC) chip, such as non-volatile NAND chip, non-volatile NOR flash chip, non-volatile magnetoresistive random-access-memory (MRAM) integrated-circuit (IC) chip, non-volatile resistive random access memory (RRAM) integrated-circuit (IC) chip, non-volatile phase-change random-access-memory (PCM) integrated-circuit (IC) chip, non-volatile ferroelectric-random-access-memory (FRAM) integrated-circuit (IC) chip or high bandwidth dynamic random-access-memory (DRAM) or static random-access-memory (SRAM) memory (HBM) chip, (5) an auxiliary and supporting (AS) integrated-circuit (IC) chip 411 as illustrated in FIG. 11, (6) an IAC IC chip 402 as illustrated in FIG. 12A, (7) a dedicated I/O chip 265 or dedicated control and I/O chip 260 as illustrated in FIGS. 12A and 12B, or (8) a power management integrated-circuit (IC) chip.

(254) 2. First Type of Operation Unit for First Type of Chip-on-chip (COC) Component or Package

(255) FIGS. 19A-19G are schematically cross-sectional views showing a process for fabricating a first type of operation unit in accordance with another embodiment of the present application. Referring to FIG. 19A, a semiconductor wafer 100d may be provided at an active side thereof with the insulating bonding layer 52 and metal pads 6a and provided with the through silicon vias (TSVs) 157 in the silicon substrate 2 thereof as illustrated in FIG. 14E, wherein neighboring two of the metal pads 6a of the semiconductor wafer 100d may have a pitch between 3 and 10 micrometers or between 4 and 7 micrometers. Next, referring to FIGS. 19A and 19B, each of first or second type of memory modules 159 may have the same structure as illustrated in FIG. 15B or 15D provided with the insulating bonding layer 52 to be bonded to the insulating bonding layer 52 of the semiconductor wafer 100d and the metal pads 6a, neighboring two of which may have a pitch between 3 and 10 micrometers or between 4 and 7 micrometers, to be bonded to the metal pads 6a of the semiconductor wafer 100d. Each of known-good memory, logic or application-specific-integrated-circuit (ASIC) chips 121 may have the structure as illustrated in FIG. 14D provided at an active side thereof with the insulating bonding layer 52 to be bonded to the insulating bonding layer 52 of the semiconductor wafer 100d and the metal pads 6a, neighboring two of which may have a pitch between 3 and 10 micrometers or between 4 and 7 micrometers, to be bonded to the metal pads 6a of the semiconductor wafer 100d. For example, each of the known-good memory, logic or application-specific-integrated-circuit (ASIC) chips 121 may be (1) an application specific integrated-circuit (ASIC) logic chip, (2) a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip 200 as illustrated in FIG. 9 or dedicated programmable interconnection (DPI) integrated-circuit (IC) chip 410 as illustrated in FIG. 10, (3) a processing and/or computing integrated-circuit (IC) chip, such as graphic-processing-unit (GPU) integrated-circuit (IC) chip, central-processing-unit (CPU) integrated-circuit (IC) chip, tensor-processing-unit (TPU) integrated-circuit (IC) chip, network-processing-unit (NPU) integrated-circuit (IC) chip, application-processing-unit (APU) integrated-circuit (IC) chip, digital-signal-processing (DSP) integrated-circuit (IC) chip, (4) a memory integrated-circuit (IC) chip, such as non-volatile NAND chip, non-volatile NOR flash chip, non-volatile magnetoresistive random-access-memory (MRAM) integrated-circuit (IC) chip, non-volatile resistive random access memory (RRAM) integrated-circuit (IC) chip, non-volatile phase-change random-access-memory (PCM) integrated-circuit (IC) chip, non-volatile ferroelectric-random-access-memory (FRAM) integrated-circuit (IC) chip or high bandwidth dynamic random-access-memory (DRAM) or static random-access-memory (SRAM) memory (HBM) chip, (5) an auxiliary and supporting (AS) integrated-circuit (IC) chip 411 as illustrated in FIG. 11, (6) an IAC IC chip 402 as illustrated in FIG. 12A, (7) a dedicated I/O chip 265 or dedicated control and I/O chip 260 as illustrated in FIGS. 12A and 12B, or (8) a power management integrated-circuit (IC) chip.

(256) Next, referring to FIGS. 19A and 19B, each of the first or second type of memory modules 159 and the known-good memory, logic or ASIC chips 121 may have the insulating bonding layer 52 bonded to the insulating bonding layer 52 of the semiconductor wafer 100d and the metal pads 6a each bonded to one of the metal pads 6a of the semiconductor wafer 100d. The process for joining each of the first or second type of memory modules 159 and the known-good memory, logic or ASIC chips 121 with the semiconductor wafer 100d by providing each of the first or second type of memory modules 159 and the known-good memory, logic or ASIC chips 121 with the insulating bonding layer 52 bonded to the insulating bonding layer 52 of the semiconductor wafer 100d and with the metal pads 6a each bonded to one of the metal pads 6a of the semiconductor wafer 100d may be referred to that for joining each of the first or second type of memory modules 159 and the known-good memory, logic or ASIC chips 121 with the semiconductor wafer 100c as illustrated in FIGS. 17A and 17B.

(257) Next, referring to FIG. 19C, a polymer layer 565, e.g., resin or compound, may be applied to fill a gap between each neighboring two of the first or second type of memory modules 159 and the known-good memory, logic or ASIC chips 121 and to cover a backside of each of the first or second type of memory modules 159 and a backside of each of the known-good memory, logic or ASIC chips 121 by methods, for example, spin-on coating, screen-printing, dispensing or molding. The polymer layer 565 may be, for example, polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer, or silicone. The polymer layer 565 may be, for example, photosensitive polyimide/PBO PIMEL™ supplied by Asahi Kasei Corporation, Japan, or epoxy-based molding compounds, resins or sealants provided by Nagase ChemteX Corporation, Japan. The polymer layer 565 may be cured or cross-linked at a temperature higher than or equal to 50, 70, 90, 100, 125, 150, 175, 200, 225, 250, 275 or 300 degrees Celsius.

(258) Next, referring to FIG. 19D, a chemical mechanical polishing (CMP), polishing or grinding process may be applied to remove a top portion of the polymer layer 565 to planarize a top surface of the polymer layer 565, a top surface of each of the first or second type of memory modules 159 and a top surface of each of the known-good memory, logic or ASIC chips 121 and to expose a backside of the topmost one of the memory chips 251 of each of the first or second type of memory modules 159 and a backside of each of the known-good memory, logic or ASIC chips 121.

(259) Next, referring to FIG. 19E, a chemical mechanical polishing (CMP), polishing or grinding process may be applied to remove a bottom portion of the semiconductor substrate 2 of the semiconductor wafer 100d and to expose a backside of the copper layer 156 of each of the through silicon vias (TSVs) 157 of the semiconductor wafer 100d. For each of the through silicon vias (TSVs) 157 of the semiconductor wafer 100d, its insulating lining layer 153, adhesion layer 154 and seed layer 155 at its backside may be removed to expose a backside of its copper layer 156, which may be coplanar with a backside of the semiconductor substrate 2 of the semiconductor wafer 100d, and its insulating lining layer 153, adhesion layer 154 and seed layer 155 at a sidewall of its copper layer 156 may be left.

(260) Next, referring to FIG. 19F, an insulating dielectric layer 93 may be formed on the backside of the semiconductor substrate 2 of the semiconductor wafer 100d. Each opening in the insulating dielectric layer 93 may be vertically under the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of the semiconductor wafer 100d. The insulating dielectric layer 93 may be a layer of polymer, such as polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer or silicone, having a thickness between 3 and 30 micrometers or between 5 and 15 micrometers.

(261) Next, referring to FIG. 19F, each of the micro-bumps or micro-pads 197, which may be of one of the first through fourth types having the same specifications as the first through fourth types of micro-bumps or micro-pads 197 as illustrated in FIG. 17E respectively, may include the adhesion layer 26a on the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of the semiconductor wafer 100d. Said each micro-bump or micro-pad 197 may be any of the first through fourth types, including (1) the adhesion layer 26a, such as titanium (Ti) or titanium nitride (TiN) layer having a thickness between 1 nm and 50 nm, on the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of the semiconductor wafer 100d.

(262) Next, the semiconductor wafer 100d and polymer layer 565 may be cut or diced to form multiple first type of operation units 190 each for a first type of chip-on-chip (COC) components or package as shown in FIG. 19G by a laser cutting process or by a mechanical cutting process. At this time, the semiconductor wafer 100d may be cut or diced into multiple semiconductor integrated-circuit (IC) chips 399, each of which may have the same specification as the semiconductor integrated-circuit (IC) chip 100 as illustrated in FIG. 14F and may be (1) an application specific integrated-circuit (ASIC) logic chip, (2) a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip 200 as illustrated in FIG. 9 or dedicated programmable interconnection (DPI) integrated-circuit (IC) chip 410 as illustrated in FIG. 10, (3) a processing and/or computing integrated-circuit (IC) chip, such as graphic-processing-unit (GPU) integrated-circuit (IC) chip, central-processing-unit (CPU) integrated-circuit (IC) chip, tensor-processing-unit (TPU) integrated-circuit (IC) chip, network-processing-unit (NPU) integrated-circuit (IC) chip, application-processing-unit (APU) integrated-circuit (IC) chip, digital-signal-processing (DSP) integrated-circuit (IC) chip, (4) a memory integrated-circuit (IC) chip, such as non-volatile NAND chip, non-volatile NOR flash chip, non-volatile magnetoresistive random-access-memory (MRAM) integrated-circuit (IC) chip, non-volatile resistive random access memory (RRAM) integrated-circuit (IC) chip, non-volatile phase-change random-access-memory (PCM) integrated-circuit (IC) chip, non-volatile ferroelectric-random-access-memory (FRAM) integrated-circuit (IC) chip or high bandwidth dynamic random-access-memory (DRAM) or static random-access-memory (SRAM) memory (HBM) chip, (5) an auxiliary and supporting (AS) integrated-circuit (IC) chip 411 as illustrated in FIG. 11, (6) an IAC IC chip 402 as illustrated in FIG. 12A, (7) a dedicated I/O chip 265 or dedicated control and I/O chip 260 as illustrated in FIGS. 12A and 12B, or (8) a power management integrated-circuit (IC) chip.

(263) Alternatively, FIG. 19H is a schematically cross-sectional view showing a first type of operation unit in accordance with another embodiment of the present application. For an element indicated by the same reference number shown in FIGS. 19A-19H, the specification of the element as seen in FIG. 19H may be referred to that of the element as illustrated in FIG. 19A-19G. Referring to FIG. 19H, the semiconductor wafer 100d may be provided at an active side thereof with the first, second or fourth type of micro-bumps or micro-pads 34, as illustrated in FIG. 14B, instead of the insulating bonding layer 52 and metal pads 6a. Each of the first or second type of memory modules 159 (only one is shown) formed as illustrated in FIG. 15A or 15B respectively may have the first, second or third type of micro-bumps or micro-pads 34 to be bonded to the first, second or fourth type of micro-bumps or micro-pads 34 preformed at an active side of the semiconductor wafer 100d into multiple bonded metal contacts 563 respectively therebetween, which may have the same specifications or details as those illustrated in FIGS. 17G, 18A and 18B for the first through fourth cases. Each of the known-good memory, logic or ASIC chips 121 (only one is shown) may have the structure as illustrated in FIG. 14B provided at an active side thereof with the first, second or third type of micro-bumps or micro-pads 34 to be bonded to the first, second or fourth type of micro-bumps or micro-pads 34 preformed at an active side of the semiconductor wafer 100d into multiple bonded metal contacts 563 respectively therebetween, which may have the same specifications or details as those illustrated in FIGS. 17G, 18A and 18B for the first through fourth cases.

(264) Next, referring to FIG. 19H, an underfill 564, such as a layer of polymer or epoxy resins or compounds, may be filled into a gap between each of the first or second type of memory modules 159 and the semiconductor wafer 100d to enclose the bonded metal contacts 563 therebetween and into a gap between each of the known-good memory, logic or ASIC chips 121 and the semiconductor wafer 100c to enclose the bonded metal contacts 563 therebetween. The underfill 564 may be cured at temperature equal to or above 100, 120 or 150 degrees Celsius. The following process may be referred to the process as illustrated in FIGS. 19C-19G.

(265) 3. Second Type of Operation Unit for Second Type of Chip-on-chip (COC) Component or Package

(266) FIGS. 20A and 20B are schematically cross-sectional views showing various second type of operation units in accordance with an embodiment of the present application. The second type of operation unit 190 for the second type of chip-on-chip (COC) component or package as seen in FIG. 20A is similar to the first type of operation unit 190 for the second type of chip-on-chip (COC) component or package as illustrated in FIG. 17F, but the difference between the first and second types of operation units 190 for the second type of chip-on-chip (COC) components or packages as seen in FIGS. 17F and 20A is that the second type of operation unit 190 for the second type of chip-on-chip (COC) component or package as seen in FIG. 20A includes (1) an insulating bonding layer 152 on the top surface of the polymer layer 565, the backside of each of the first or second type of memory modules 159, the backside of each of the known-good memory, logic or ASIC chips 121 and the backside of each of the second type of vertical-through-via (VTV) connectors 467 and (2) multiple metal pads 116 each in one of multiple openings in the insulating bonding layer 152 and on the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of the topmost one of the memory chips 251 of one of the first or second type of memory modules 159, the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of one of the known-good memory, logic or ASIC chips 121 or the backside of the copper layer 156 of one of the vertical through vias (VTVs) 358 of one of the second type of vertical-through-via (VTV) connectors 467 for the first and second alternatives, instead of the insulating dielectric layer 93 and the first through fourth types of micro-bumps or micro-pads 197 as illustrated in FIG. 17F. The second type of operation unit 190 for the second type of chip-on-chip (COC) component or package as seen in FIG. 20B is similar to the first type of operation unit 190 for the second type of chip-on-chip (COC) component or package as illustrated in FIG. 17G, but the difference between the first and second types of operation units 190 for the second type of chip-on-chip (COC) components or packages as seen in FIGS. 17G and 20B is that the second type of operation unit 190 for the second type of chip-on-chip (COC) component or package as seen in FIG. 20B includes (1) an insulating bonding layer 152 on the top surface of the polymer layer 565 and (2) multiple metal pads 116 each in one of multiple openings in the insulating bonding layer 152 and on the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of the topmost one of the memory chips 251 of one of the first or second type of memory modules 159, the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of one of the known-good memory, logic or ASIC chips 121, the backside of the copper layer 156 of one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 for the first and second alternatives, the backside of the copper post 706 of one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 for the third and fourth alternatives or the backside of the metal pad 336 or copper post 318 of one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 for the fifth alternative, instead of the insulating dielectric layer 93 and the first through fourth types of micro-bumps or micro-pads 197 as illustrated in FIG. 17G.

(267) For each of the second type of operation units 190 for the second type of chip-on-chip (COC) components or packages as seen in FIGS. 20A and 20B, its insulating bonding layer 152 may be a silicon-oxide layer having a thickness between 0.1 and 2 μm. Each of its metal pads 116 may include (1) a copper layer 24 having a thickness of between 3 nm and 500 nm in one of the openings in its insulating bonding layer 152, (2) an adhesion layer 18, such as titanium or titanium nitride having a thickness of between 1 nm and 50 nm, at a bottom and sidewall of the copper layer 24 of said each of its metal pads 116 and (3) a seed layer 22, such as copper, between the copper layer 24 and adhesion layer 18 of said each of its metal pads 116, wherein the copper layer 24 of said each of its metal pads 116 may have a top surface substantially coplanar with a top surface of the silicon-oxide layer of its insulating bonding layer 152.

(268) 4. Second Type of Operation Unit for First Type of Chip-on-chip (COC) Component or Package

(269) FIGS. 21A and 21B are schematically cross-sectional views showing various second type of operation units in accordance with another embodiment of the present application. The second type of operation unit 190 for the first type of chip-on-chip (COC) component or package as seen in FIG. 21A is similar to the first type of operation unit 190 for the first type of chip-on-chip (COC) component or package as illustrated in FIG. 19G, but the difference between the first and second types of operation units 190 for the first type of chip-on-chip (COC) components or packages as seen in FIGS. 19G and 21A is that the second type of operation unit 190 for the first type of chip-on-chip (COC) component or package as seen in FIG. 21A includes (1) an insulating bonding layer 152 on the backside of the semiconductor substrate 2 of its semiconductor integrated-circuit (IC) chip 399 and (2) multiple metal pads 116 each in one of multiple openings in the insulating bonding layer 152 and on the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of its semiconductor integrated-circuit (IC) chip 399. The second type of operation unit 190 for the first type of chip-on-chip (COC) component or package as seen in FIG. 21B is similar to the first type of operation unit 190 for the first type of chip-on-chip (COC) component or package as illustrated in FIG. 19H, but the difference between the first and second types of operation units 190 for the first type of chip-on-chip (COC) components or packages as seen in FIGS. 19H and 21B is that the second type of operation unit 190 for the first type of chip-on-chip (COC) component or package as seen in FIG. 21B includes (1) an insulating bonding layer 152 on the backside of the semiconductor substrate 2 of its semiconductor integrated-circuit (IC) chip 399 and (2) multiple metal pads 116 each in one of multiple openings in the insulating bonding layer 152 and on the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 of its semiconductor integrated-circuit (IC) chip 399.

(270) For each of the second type of operation units 190 for the first type of chip-on-chip (COC) components or packages as seen in FIGS. 21A and 21B, its insulating bonding layer 152 may be a silicon-oxide layer having a thickness between 0.1 and 2 μm. Each of its metal pads 116 may include (1) a copper layer 24 having a thickness of between 3 nm and 500 nm in one of the openings in its insulating bonding layer 152, (2) an adhesion layer 18, such as titanium or titanium nitride having a thickness of between 1 nm and 50 nm, at a top and sidewall of the copper layer 24 of said each of its metal pads 116 and (3) a seed layer 22, such as copper, between the copper layer 24 and adhesion layer 18 of said each of its metal pads 116, wherein the copper layer 24 of said each of its metal pads 116 may have a bottom surface substantially coplanar with a bottom surface of the silicon-oxide layer of its insulating bonding layer 152.

(271) 5. Remarks for First and Second Types of Operation Units for First and Second Types of Chip-on-chip (COC) Components or Packages

(272) For each of the first and second type of operation units 190 for the second type of chip-on-chip (COC) components or packages as seen in FIGS. 17F and 20A, its semiconductor integrated-circuit (IC) chip 399 may have the semiconductor devices 4 such as transistors at the active surface of the semiconductor substrate 2 thereof as illustrated in FIG. 14D, and the active surface of the semiconductor substrate 2 of its semiconductor integrated-circuit (IC) chip 399 may face an active surface of the semiconductor substrate 2 of each of its known-good memory, logic ASIC chips 121, wherein said each of its known-good memory, logic or ASIC chips 121 may have the semiconductor devices 4 such as transistors at the active surface of the semiconductor substrate 2 thereof as illustrated in FIG. 14E. For each of the first and second type of operation units 190 for the second type of chip-on-chip (COC) components or packages as seen in FIGS. 17G and 20B, its semiconductor integrated-circuit (IC) chip 399 may have the semiconductor devices 4 such as transistors at the active surface of the semiconductor substrate 2 thereof as illustrated in FIG. 14A or 14B, and the active surface of the semiconductor substrate 2 of its semiconductor integrated-circuit (IC) chip 399 may face an active surface of the semiconductor substrate 2 of each of its known-good memory, logic ASIC chips 121, wherein said each of its known-good memory, logic or ASIC chips 121 may have the semiconductor devices 4 such as transistors at the active surface of the semiconductor substrate 2 thereof as illustrated in FIG. 14B. For each of the first and second type of operation units 190 for the first type of chip-on-chip (COC) components or packages as seen in FIGS. 19G and 21A, its semiconductor integrated-circuit (IC) chip 399 may have the semiconductor devices 4 such as transistors at the active surface of the semiconductor substrate 2 thereof as illustrated in FIG. 14E, and the active surface of the semiconductor substrate 2 of its semiconductor integrated-circuit (IC) chip 399 may face an active surface of the semiconductor substrate 2 of each of its known-good memory, logic ASIC chips 121, wherein said each of its known-good memory, logic or ASIC chips 121 may have the semiconductor devices 4 such as transistors at the active surface of the semiconductor substrate 2 thereof as illustrated in FIG. 14D. For each of the first and second type of operation units 190 for the first type of chip-on-chip (COC) components or packages as seen in FIGS. 19H and 21B, its semiconductor integrated-circuit (IC) chip 399 may have the semiconductor devices 4 such as transistors at the active surface of the semiconductor substrate 2 thereof as illustrated in FIG. 14B, and the active surface of the semiconductor substrate 2 of its semiconductor integrated-circuit (IC) chip 399 may face an active surface of the semiconductor substrate 2 of each of its known-good memory, logic ASIC chips 121, wherein said each of its known-good memory, logic or ASIC chips 121 may have the semiconductor devices 4 such as transistors at the active surface of the semiconductor substrate 2 thereof as illustrated in FIG. 14A or 14B. For each of the first and second type of operation units 190 for the first and second types of chip-on-chip (COC) components or packages as seen in FIGS. 17F, 17G, 19G, 19H, 20A, 20B, 21A and 21B, the active surface of the semiconductor substrate 2 of its semiconductor integrated-circuit (IC) chip 399 may face each of its first or second type of memory modules 159. For each of the first and second types of operation units 190 for the first types of chip-on-chip (COC) components or packages as seen in FIGS. 17F and 20A, the active surface of the semiconductor substrate 2 of its semiconductor integrated-circuit (IC) chip 399 may face each of its second type of vertical-through-via (VTV) connectors 467. For each of the first and second types of operation units 190 for the first types of chip-on-chip (COC) components or packages as seen in FIGS. 17G and 20B, the active surface of the semiconductor substrate 2 of its semiconductor integrated-circuit (IC) chip 399 may face each of its first type of vertical-through-via (VTV) connectors 467.

(273) For each of the first and second type of operation units 190 for the first and second types of chip-on-chip (COC) components or packages as seen in FIGS. 17F, 17G, 19G, 19H, 20A, 20B, 21A and 21B, the control chip 688 of each of its first or second type of memory modules 159 may have multiple small I/O circuits coupling respectively to multiple small I/O circuits of its semiconductor integrated-circuit (IC) chip 399 through the bonded metal pads 6a of the control chip 688 of said each of its second type of memory modules 159 and the bonded metal pads 6a of its semiconductor integrated-circuit (IC) chip 399 as seen in FIG. 17F, 19G, 20A or 21A or through its bonded metal contacts 563 therebetween as seen in FIG. 17G, 19H, 20B or 21B for data transmission therebetween with a data bit width of equal to or greater than 64, 128, 256, 512, 1024, 2048, 4096, 8K, or 16K, wherein each of the small I/O circuits of the control chip 688 of said each of its first or second type of memory modules 159 may have an output capacitance or driving capability or loading, for example, between 0.05 pF and 2 pF or between 0.05 pF and 1 pF, or smaller than 2 pF or 1 pF, and an input capacitance between 0.15 pF and 4 pF or between 0.15 pF and 2 pF, or greater than 0.15 pF; alternatively each of the small input/output (I/O) circuits of the control chip 688 of said each of its first or second type of memory modules 159 may have an I/O power efficiency smaller than 0.5 pico-Joules per bit, per switch or per voltage swing, or between 0.01 and 0.5 pico-Joules per bit, per switch or per voltage swing. Each of its known-good memory, logic or ASIC chips 121 may have multiple small I/O circuits coupling respectively to multiple small I/O circuits of its semiconductor integrated-circuit (IC) chip 399 through the bonded metal pads 6a of said each of its known-good memory, logic or ASIC chips 121 and the bonded metal pads 6a of its semiconductor integrated-circuit (IC) chip 399 as seen in FIG. 17F, 19G, 20A or 21A or through its bonded metal contacts 563 therebetween as seen in FIG. 17G, 19H, 20B or 21B for data transmission therebetween with a data bit width of equal to or greater than 64, 128, 256, 512, 1024, 2048, 4096, 8K, or 16K, wherein each of the small I/O circuits of said each of its known-good memory, logic or ASIC chips 121 may have an output capacitance or driving capability or loading, for example, between 0.05 pF and 2 pF or between 0.05 pF and 1 pF, or smaller than 2 pF or 1 pF, and an input capacitance between 0.15 pF and 4 pF or between 0.15 pF and 2 pF, or greater than 0.15 pF; alternatively each of the small input/output (I/O) circuits of said each of its known-good memory, logic or ASIC chips 121 may have an I/O power efficiency smaller than 0.5 pico-Joules per bit, per switch or per voltage swing, or between 0.01 and 0.5 pico-Joules per bit, per switch or per voltage swing. Each of the small I/O circuits of its semiconductor integrated-circuit (IC) chip 399 may have an output capacitance or driving capability or loading, for example, between 0.05 pF and 2 pF or between 0.05 pF and 1 pF, or smaller than 2 pF or 1 pF, and an input capacitance between 0.15 pF and 4 pF or between 0.15 pF and 2 pF, or greater than 0.15 pF; alternatively each of the small input/output (I/O) circuits of its semiconductor integrated-circuit (IC) chip 399 may have an I/O power efficiency smaller than 0.5 pico-Joules per bit, per switch or per voltage swing, or between 0.01 and 0.5 pico-Joules per bit, per switch or per voltage swing.

(274) Further, for each of the first and second type of operation units 190 for the first and second types of chip-on-chip (COC) components or packages as seen in FIGS. 17F, 17G, 19G, 19H, 20A, 20B, 21A and 21B, the control chip 688 of one of its first or second type of memory modules 159 or one of its known-good memory, logic or ASIC chips 121 may include multiple non-volatile memory cells configured to store a password or key and a cryptography block or circuit configured (1) to encrypt, in accordance with the password or key, CPM data from the memory cells 490 for the look-up tables (LUT) 210 of the programmable logic cells (LC) 2014 of its semiconductor integrated-circuit (IC) chip 399 or the memory cells 362 of the programmable switch cells 379 of its semiconductor integrated-circuit (IC) chip 399 as encrypted CPM data to be passed to its micro-bumps or micro-pads 197 as seen in FIG. 17F, 17G, 19G or 19H or to its metal pads 116 as seen in FIG. 20A, 20B, 21A or 21B, and (2) to decrypt, in accordance with the password or key, encrypted CPM data from its micro-bumps or micro-pads 197 as seen in FIG. 17F, 17G, 19G or 19H or from its metal pads 116 as seen in FIG. 20A, 20B, 21A or 21B as decrypted CPM data to be passed to the memory cells 490 for the look-up tables (LUT) 210 of the programmable logic cells (LC) 2014 of its semiconductor integrated-circuit (IC) chip 399 or the memory cells 362 of the programmable switch cells 379 of its semiconductor integrated-circuit (IC) chip 399. Further, one of its known-good memory, logic or ASIC chips 121 may include a regulating block configured to regulate a voltage of power supply from an input voltage of 12, 5, 3.3 or 2.5 volts to an output voltage of 3.3, 2.5, 1.8, 1.5, 1.35, 1.2, 1.0, 0.75 or 0.5 volts to be delivered to its semiconductor integrated-circuit (IC) chip 399. Further, one of its known-good memory, logic or ASIC chips 121 may include multiple non-volatile memory cells, such as NAND memory cells, NOR memory cells, RARM cells, MRAM cells, FRAM cells or PCM cells, configured to store CPM data to be passed to the memory cells 490 for the look-up tables (LUT) 210 of the programmable logic cells (LC) 2014 of its semiconductor integrated-circuit (IC) chip 399 for programming or configuring the programmable logic cells (LC) 2014 of its semiconductor integrated-circuit (IC) chip 399 or to the memory cells 362 of the programmable switch cells 379 of its semiconductor integrated-circuit (IC) chip 399 for programming or configuring the programmable switch cells 379 of its semiconductor integrated-circuit (IC) chip 399.

(275) Further, for each of the first and second type of operation units 190 for the second type of chip-on-chip (COC) components or packages as seen in FIGS. 17F, 17G, 20A and 20B, its semiconductor integrated-circuit (IC) chip 399 may have a large input/output (I/O) circuit coupling to one of its micro-bumps or micro-pads 197 as seen in FIG. 17F or 17G or one of its metal pads 116 as seen in FIG. 20A or 20B for signal or clock transmission or power supply (Vcc) or ground reference (Vss) delivery through one of the dedicated vertical bypasses 698 in one of its second type of memory module 159 as illustrated in FIGS. 15B and 15D, one of the through silicon vias (TSVs) 157 of one of its known-good memory, logic ASIC chips 121 or one of the vertical through vias (VTVs) 358 of one of its first or second type of vertical-through-via (VTV) connectors 467, wherein said one of the dedicated vertical bypasses 698 is not connected to any transistor in the memory chips 251 and control chip 688 of said one of its second type of memory module 159 and said one of the through silicon vias (TSVs) 157 may not be connected to any transistor in said one of its known-good memory, logic or ASIC chips 121, wherein the large input/output (I/O) circuit may have an output capacitance or driving capability or loading between 2 pF and 100 pF, between 2 pF and 50 pF, between 2 pF and 30 pF, between 2 pF and 20 pF, between 2 pF and 15 pF, between 2 pF and 10 pF, or between 2 pF and 5 pF, or greater than 2 pF, 5 pF, 10 pF, 15 pF or 20 pF, and an input capacitance between 0.15 pF and 4 pF or between 0.15 pF and 2 pF, or greater than 0.15 pF for example; alternatively, the large input/output (I/O) circuit may have an I/O power efficiency greater than 3, 5 or 10 pico-Joules per bit, per switch or per voltage swing. One of the vertical interconnects 699 of its first or second type of memory module 159 as illustrated in FIGS. 15A-15D may couple to one of its micro-bumps or micro-pads 197 as seen in FIG. 17F or 17G or to one of its metal pads 116 as seen in FIG. 20A or 20B and couple to its semiconductor integrated-circuit (IC) chip 399 through one of the metal pads 6a of the control chip 688 of its first or second type of memory module 159 as seen in FIG. 17F or 20A or through one of its bonded metal contacts 563 as seen in FIG. 17G or 20B.

(276) Further, for each of the first and second type of operation units 190 for the first type of chip-on-chip (COC) components or packages as seen in FIGS. 19G, 19H, 21A and 21B, its semiconductor integrated-circuit (IC) chip 399 may have a large input/output (I/O) circuit coupling to one of its micro-bumps or micro-pads 197 as seen in FIG. 19G or 19H or one of its metal pads 116 as seen in FIG. 21A or 21B for signal or clock transmission or power supply (Vcc) or ground reference (Vss) delivery through one of the through silicon vias (TSVs) 157 of its semiconductor integrated-circuit (IC) chip 399, wherein the large input/output (I/O) circuit may have an output capacitance or driving capability or loading between 2 pF and 100 pF, between 2 pF and 50 pF, between 2 pF and 30 pF, between 2 pF and 20 pF, between 2 pF and 15 pF, between 2 pF and 10 pF, or between 2 pF and 5 pF, or greater than 2 pF, 5 pF, 10 pF, 15 pF or 20 pF, and an input capacitance between 0.15 pF and 4 pF or between 0.15 pF and 2 pF, or greater than 0.15 pF for example; alternatively, the large input/output (I/O) circuit may have an I/O power efficiency greater than 3, 5 or 10 pico-Joules per bit, per switch or per voltage swing.

(277) Further, for each of the first and second type of operation units 190 for the first and second types of chip-on-chip (COC) components or packages as seen in FIGS. 17F, 17G, 19G, 19H, 20A, 20B, 21A and 21B, each of the memory chips 251 and control chip 688 of each of its first or second type of memory modules 159 and each of its known-good memory, logic or ASIC chips 121 may be implemented using a semiconductor note or generation less advanced than or equal to, or above or equal to 20 nm, 30 nm, 40 nm, 50 nm, 90 nm, 130 nm, 250 nm, 350 nm or 500 nm. The semiconductor technology node or generation used in each of the memory chips 251 and control chip 688 of each of its first or second type of memory modules 159 and each of its known-good memory, logic or ASIC chips 121 may be 1, 2, 3, 4, 5 or greater than 5 nodes or generations older, more matured or less advanced than that used in its semiconductor integrated-circuit (IC) chip 399. Transistors used in each of the memory chips 251 and control chip 688 of each of its first or second type of memory modules 159 and each of its known-good memory, logic or ASIC chips may be provided with fully depleted silicon-on-insulator (FDSOI) metal-oxide-semiconductor field effect transistors (MOSFETs), partially depleted silicon-on-insulator (PDSOI) MOSFETs or a planar MOSFETs. Transistors used in each of the memory chips 251 and control chip 688 of each of its first or second type of memory modules 159 and each of its known-good memory, logic or ASIC chips 121 may be different from those used in its semiconductor integrated-circuit (IC) chip 399; each of the memory chips 251 and control chip 688 of each of its first or second type of memory modules 159 and each of its known-good memory, logic or ASIC chips 121 may use planar MOSFETs, while its semiconductor integrated-circuit (IC) chip 399 may use fin field effect transistors (FINFETs) or gate-all-around field effect transistors (GAAFETs). A power supply voltage (Vcc) applied in each of the memory chips 251 and control chip 688 of each of its first or second type of memory modules 159 and each of its known-good memory, logic or ASIC chips 121 may be greater than or equal to 1.5, 2.0, 2.5, 3, 3.3, 4, or 5 voltages, while a power supply voltage (Vcc) applied in its semiconductor integrated-circuit (IC) chip 399 may be smaller than or equal to 1.8, 1.5 or 1 voltage. The power supply voltage applied in each of the memory chips 251 and control chip 688 of each of its first or second type of memory modules 159 and each of its known-good memory, logic or ASIC chips 121 may be higher than that applied in its semiconductor integrated-circuit (IC) chip 399. A gate oxide of a field effect transistor (FET) of each of the memory chips 251 and control chip 688 of each of its first or second type of memory modules 159 and a gate oxide of a field effect transistor (FET) of each of its known-good memory, logic or ASIC chips 121 may have a physical thickness greater than or equal to 5 nm, 6 nm, 7.5 nm, 10 nm, 12.5 nm, or 15 nm, while a gate oxide of afield effect transistor (FET) of its semiconductor integrated-circuit (IC) chip 399 may have a physical thickness less than 4.5 nm, 4 nm, 3 nm or 2 nm. The thickness of the gate oxide of the field effect transistor (FET) of each of the memory chips 251 and control chip 688 of each of its first or second type of memory module 159 and the thickness of the gate oxide of the field effect transistor (FET) of each of its known-good memory, logic or ASIC chips 121 may be greater than that of its semiconductor integrated-circuit (IC) chip 399.

(278) First Embodiment for Chip Package Based on Frontside Interconnection Scheme for Logic Drive or Device (FISD)

(279) 1. First Type of Chip Package for First Embodiment

(280) FIGS. 22A-22H are schematically cross-sectional views showing a process for forming a first type of multichip package in accordance with a first embodiment of the present application. Referring to FIG. 22A, a temporary substrate 590 may be provided with a glass or silicon substrate 589 and a sacrificial bonding layer 591 formed on the glass or silicon substrate 589. The sacrificial bonding layer 591 may have the glass or silicon substrate 589 to be easily debonded or released from a structure subsequently formed on the sacrificial bonding layer 591. For example, the sacrificial bonding layer 591 may be a material of light-to-heat conversion (LTHC) that may be deposited on the glass or silicon substrate 589 by printing or spin-on coating and then cured or dried with a thickness of about 1 micrometer or between 0.5 and 2 micrometers. The LTHC material may be a liquid ink containing carbon black and binder in a mixture of solvents.

(281) Next, referring to FIG. 22A, multiple semiconductor integrated-circuit (IC) chips 100, each of which may be (1) an application specific integrated-circuit (ASIC) logic chip, (2) a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip 200 as illustrated in FIG. 9 or dedicated programmable interconnection (DPI) integrated-circuit (IC) chip 410 as illustrated in FIG. 10, (3) a processing and/or computing integrated-circuit (IC) chip, such as graphic-processing-unit (GPU) integrated-circuit (IC) chip, central-processing-unit (CPU) integrated-circuit (IC) chip, tensor-processing-unit (TPU) integrated-circuit (IC) chip, network-processing-unit (NPU) integrated-circuit (IC) chip, application-processing-unit (APU) integrated-circuit (IC) chip, digital-signal-processing (DSP) integrated-circuit (IC) chip, (4) a memory integrated-circuit (IC) chip, such as non-volatile NAND chip, non-volatile NOR flash chip, non-volatile magnetoresistive random-access-memory (MRAM) integrated-circuit (IC) chip, non-volatile resistive random access memory (RRAM) integrated-circuit (IC) chip, non-volatile phase-change random-access-memory (PCM) integrated-circuit (IC) chip, non-volatile ferroelectric-random-access-memory (FRAM) integrated-circuit (IC) chip or high bandwidth dynamic random-access-memory (DRAM) or static random-access-memory (SRAM) memory (HBM) chip, (5) an auxiliary and supporting (AS) integrated-circuit (IC) chip 411 as illustrated in FIG. 11, (6) an IAC IC chip 402 as illustrated in FIG. 12A, (7) a dedicated I/O chip 265 or dedicated control and I/O chip 260 as illustrated in FIGS. 12A and 12B, or (8) a power management integrated-circuit (IC) chip, each may have the same specification as illustrated in FIG. 14A or 14B, provided with the first type of micro-bumps or micro-pads 34. Each of the semiconductor integrated-circuit (IC) chips 100 may further include an insulating dielectric layer 257, such as polymer layer, over its first and/or second interconnection scheme(s) 560 and/or 588, covering a top surface and sidewall of the copper layer 32 of each of its first type of micro-bumps or micro-pads 34, wherein the insulating dielectric layer 257 may be, for example, polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer, or silicone; the insulating dielectric layer 257 may be, for example, photosensitive polyimide/PBO PIMEL™ supplied by Asahi Kasei Corporation, Japan, or epoxy-based molding compounds, resins or sealants provided by Nagase ChemteX Corporation, Japan. Each of the semiconductor integrated-circuit (IC) chips 100 may have a backside attached to the sacrificial bonding layer 591 of the temporary substrate 590.

(282) Further, referring to FIG. 22A, multiple first type of operation units 190, each of which may have the same specification as illustrated in FIG. 17F, 17G, 19G or 19H, each may be provided with the first type of micro-bumps or micro-pads 197. Each of the semiconductor integrated-circuit (IC) chips 100 may further include an insulating dielectric layer 257, such as polymer layer, on its insulating dielectric layer 93, covering a top surface and sidewall of the copper layer 32 of its first type of micro-bumps or micro-pads 197, wherein the insulating dielectric layer 257 may be, for example, polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer, or silicone; the insulating dielectric layer 257 may be, for example, photosensitive polyimide/PBO PIMEL™ supplied by Asahi Kasei Corporation, Japan, or epoxy-based molding compounds, resins or sealants provided by Nagase ChemteX Corporation, Japan. Each of the first type of operation units 190 may have a backside attached to the sacrificial bonding layer 591 of the temporary substrate 590.

(283) Further, referring to FIG. 22A, multiple first type of vertical-through-via (VTV) connectors 467, each of which may have the same specification as illustrated in FIG. 1A, 1C, 1E, 2A, 2C or 2E, each may be provided with the first type of micro-bumps or micro-pads 34. Alternatively, each of the first type of vertical-through-via (VTV) connectors 467 may have the same specification as illustrated in FIG. 4A, 4B, 4C, 5A, 5B or 5C, but its fifth type of micro-bumps or micro-pads 34 is replaced with the first type of micro-bumps or micro-pads 34 as illustrated in FIG. 1A. Alternatively, each of the first type of vertical-through-via (VTV) connectors 467 may have the same specification as illustrated in FIG. 6, but its sixth type of micro-bumps or micro-pads 34 is replaced with the first type of micro-bumps or micro-pads 34 as illustrated in FIG. 1A. Each of the first type of vertical-through-via (VTV) connectors 467 may further include an insulating dielectric layer 257, such as polymer, at a top thereof, covering a top surface and sidewall of the copper layer 32 of its first type of micro-bumps or micro-pads 34, wherein the insulating dielectric layer 257 may be, for example, polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer, or silicone; the insulating dielectric layer 257 may be, for example, photosensitive polyimide/PBO PIMEL™ supplied by Asahi Kasei Corporation, Japan, or epoxy-based molding compounds, resins or sealants provided by Nagase ChemteX Corporation, Japan. Each of the first type of vertical-through-via (VTV) connectors 467 may have a backside attached to the sacrificial bonding layer 591 of the temporary substrate 590.

(284) Next, referring to FIG. 22A, a polymer layer 92, e.g., resin or compound, may be applied to fill a gap between each neighboring two of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 and to cover the insulating dielectric layer 257 of each of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 by methods, for example, spin-on coating, screen-printing, dispensing or molding. The polymer layer 92 may be, for example, polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer, or silicone. The polymer layer 92 may be, for example, photosensitive polyimide/PBO PIMEL™ supplied by Asahi Kasei Corporation, Japan, or epoxy-based molding compounds, resins or sealants provided by Nagase ChemteX Corporation, Japan. The polymer layer 92 may be cured or cross-linked at a temperature higher than or equal to 50, 70, 90, 100, 125, 150, 175, 200, 225, 250, 275 or 300 degrees Celsius.

(285) Next, referring to FIG. 22C, a chemical mechanical polishing (CMP), polishing or grinding process may be applied to remove a top portion of the polymer layer 92 and a top portion of the insulating dielectric layer 257 each of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 and to planarize a top surface of the polymer layer 92, a top surface of the copper layer 32 of each of the first type of micro-bumps or micro-pads 34 of each of the semiconductor integrated-circuit (IC) chips 100, a top surface of the copper layer 32 of each of the first type of micro-bumps or micro-pads 197 of each of the first type of operation units 190 and a top surface of the copper layer 32 of each of the first type of micro-bumps or micro-pads 34 of each of the first type of vertical-through-via (VTV) connectors 467. Thereby, the top surface of the copper layer 32 of each of the first type of micro-bumps or micro-pads 34 of each of the semiconductor integrated-circuit (IC) chips 100, the top surface of the copper layer 32 of each of the first type of micro-bumps or micro-pads 197 of each of the first type of operation units 190 and the top surface of the copper layer 32 of each of the first type of micro-bumps or micro-pads 34 of each of the first type of vertical-through-via (VTV) connectors 467 may be exposed.

(286) Referring to FIG. 22D, a frontside interconnection scheme for a logic drive or device (FISD) 101 may be formed on the polymer layer 92 and over the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467. The frontside interconnection scheme for a logic drive or device (FISD) 101 may include one or more interconnection metal layers 27 coupling to the first type of micro-bumps or micro-pads 34 of each of the semiconductor integrated-circuit (IC) chips 100, the first type of micro-bumps or micro-pads 197 of each of the first type of operation units 190 and the first type of micro-bumps or micro-pads 34 of each of the first type of vertical-through-via (VTV) connectors 467, and one or more polymer layers 42, i.e., insulating dielectric layers, each between neighboring two of its interconnection metal layers 27, between a bottommost one of its interconnection metal layers 27 and a polished planar surface composed of the top surface of the polymer layer 92, the top surface of the copper layer 32 of each of the first type of micro-bumps or micro-pads 34 of each of the semiconductor integrated-circuit (IC) chips 100, the top surface of the copper layer 32 of each of the first type of micro-bumps or micro-pads 197 of each of the first type of operation units 190 and the top surface of the copper layer 32 of each of the first type of micro bumps or micro-pads 34 of each of the first type of vertical-through-via (VTV) connectors 467, or on and above a topmost one of its interconnection metal layers 27, wherein the topmost one of its interconnection metal layers 27 may have multiple metal pads at bottoms of multiple openings 42a in the topmost one of its polymer layers 42. Each of the interconnection metal layers 27 may include (1) a copper layer 40 having lower portions in openings in one of the polymer layers 42 having a thickness of between 0.3 μm and 20 μm and upper portions having a thickness 0.3 μm and 20 μm over said one of the polymer layers 42, (2) an adhesion layer 28a, such as titanium or titanium nitride having a thickness of between 1 nm and 50 nm, at a bottom and sidewall of each of the lower portions of the copper layer 40 and at a bottom of each of the upper portions of the copper layer 40, and (3) a seed layer 28b, such as copper, between the copper layer 40 and the adhesion layer 28a, wherein said each of the upper portions of the copper layer 40 may have a sidewall not covered by the adhesion layer 28a. For the frontside interconnection scheme for a logic drive or device (FISD) 101, each of its interconnection metal layers 27 may have a metal line or trace with a thickness between, for example, 0.3 μm and 40 μm, 0.5 μm and 30 μm, 1 μm and 20 μm, 1 μm and 15 μm, 1 μm and 10 μm, or 0.5 μm to 5 μm, or greater than or equal to 0.3 μm, 0.7 μm, 1 μm, 2 μm, 3 μm, 5 μm, 7 μm or 10 μm and a width between, for example, 0.3 μm and 40 μm, 0.5 μm and 30 μm, 1 μm and 20 μm, 1 μm and 15 μm, 1 μm and 10 μm, or 0.5 μm to 5 μm, or greater than or equal to 0.3 μm, 0.7 μm, 1 μm, 2 μm, 3 μm, 5 μm, 7 μm or 10 μm. Each of its polymer layer 42 may be a layer of polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer or silicone, having a thickness between, for example, 0.3 μm and 50 μm, 0.3 μm and 30 μm, 0.5 μm and 20 μm, 1 μm and 10 μm, or 0.5 μm and 5 μm, or thicker than or equal to 0.3 μm, 0.5 μm, 0.7 μm, 1 μm, 1.5 μm, 2 μm, 3 μm or 5 μm. One of its interconnection metal layers 27 may have two planes used respectively for power and ground planes of a power supply and/or used as a heat dissipater or spreader for the heat dissipation or spreading, wherein each of the two planes may have a thickness, for example, between 5 μm and 50 μm, 5 μm and 30 μm, 5 μm and 20 μm, or 5 μm and 15 μm, or greater than or equal to 5 μm, 10 μm, 20 μm, or 30 μm. The two planes may be layout as interlaced or interleaved shaped structures in a plane or may be layout in a fork shape. For the frontside interconnection scheme for a logic drive or device (FISD) 101, each of its interconnection metal layers 27 may extend horizontally across an edge of each of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467. The topmost one of its interconnection metal layers 27 may be patterned with multiple metal pads at bottoms of multiple respective openings in the topmost one of its polymer layers 42.

(287) Next, the glass or silicon substrate 589 as seen in FIG. 22D may be released from the sacrificial bonding layer 591. For example, in the case that the sacrificial bonding layer 591 is the material of light-to-heat conversion (LTHC) and the substrate 589 is made of glass, a laser light, such as YAG laser having a wavelength of about 1064 nm, an output power between 20 and 50 W and a spot size of 0.3 mm in diameter at a focal point, may be generated to pass from the backside of the glass substrate 589 to the sacrificial bonding layer 591 through the glass substrate 589 to scan the sacrificial bonding layer 591 at a speed of 8.0 m/s, for example, such that the sacrificial bonding layer 591 may be decomposed and thus the glass substrate 589 may be easily released from the sacrificial bonding layer 591. Next, an adhesive peeling tape (not shown) may be attached to a bottom surface of the remainder of the sacrificial bonding layer 591. Next, the adhesive peeling tape may be peeled off to pull the remainder of the sacrificial bonding layer 591 attached to the adhesive peeling tape off such that the backside of each of the semiconductor integrated-circuit (IC) chips 100, the backside of each of the first type of operation units 190, the backside of each of the first type of vertical-through-via (VTV) connectors 467 and a bottom surface of the polymer layer 92 may be exposed as seen in FIG. 22E.

(288) Next, referring to FIG. 22F, a chemical mechanical polishing (CMP), polishing or grinding process may be applied to remove a bottom portion of the polymer layer 92, a bottom portion of each of the semiconductor integrated-circuit (IC) chips 100, a bottom portion of each of the first type of operation units 190 and a bottom portion of each of the first type of vertical-through-via (VTV) connectors 467 and to expose a backside of each of the vertical through vias (VTVs) 358 of each of the first type of vertical-through-via (VTV) connectors 467. For each of the vertical through vias (VTVs) 358 of said each of the first type of vertical-through-via (VTV) connectors 467, if made of one or more of the through silicon vias (TSVs) 157 as illustrated in one of FIGS. 1A, 1C, 1E, 2A, 2C and 2F, its insulating lining layer 153, adhesion layer 154 and seed layer 155 at its backside may be removed to expose a backside of its copper layer 156, which is coplanar with a backside of said each of the first type of vertical-through-via (VTV) connectors 467 and a bottom surface of the polymer layer 92, and its insulating lining layer 153, adhesion layer 154 and seed layer 155 at a sidewall of its copper layer 156 may be left. For each of the vertical through vias (VTVs) 358 of said each of the first type of vertical-through-via (VTV) connectors 467, if made of one or more of the through glass vias (TGVs) 259 as illustrated in one of FIGS. 4A, 4B, 4C, 5A, 5B and 5C, a backside of its copper post 706 may be exposed with being coplanar with a backside of said each of the first type of vertical-through-via (VTV) connectors 467 and the bottom surface of the polymer layer 92; for each of the vertical through vias (VTVs) 358 of said each of the first type of vertical-through-via (VTV) connectors 467, if made of one or more of the through polymer vias (TPVs) 318 as illustrated in FIG. 6 for the fifth alternative, a backside of its metal pad 336 or copper post 318 may be exposed with being coplanar with a backside of said each of the first type of vertical-through-via (VTV) connectors 467 and the bottom surface of the polymer layer 92.

(289) Next, referring to FIG. 22G, a backside interconnection scheme for a logic drive or device (BISD) 79 may be formed on the backside of each of the semiconductor integrated-circuit (IC) chips 100, the backside of each of the first type of operation units 190, the backside of each of the first type of vertical-through-via (VTV) connectors 467 and the bottom surface of the polymer layer 92. The backside interconnection scheme for a logic drive or device (BISD) 79 may include an insulating dielectric layer 93 on the backside of each of the semiconductor integrated-circuit (IC) chips 100, the backside of each of the first type of operation units 190, the backside of each of the first type of vertical-through-via (VTV) connectors 467 and the bottom surface of the polymer layer 92. Each opening in the insulating dielectric layer 93 may be vertically under the backside of one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467. The insulating dielectric layer 93 may be a layer of polymer, such as polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer or silicone, having a thickness between 3 and 30 micrometers or between 5 and 15 micrometers. For said one of the first type of vertical-through-via (VTV) connectors 467, if said one of its vertical through vias (VTVs) 358 is made of one or more of the through silicon vias (TSVs) 157 as illustrated in one of FIGS. 1A, 1C, 1E, 2A, 2C and 2E, said each opening in the insulating dielectric layer 93 may be vertically under the backside of the copper layer 156 of said one or more of its through silicon vias (TSVs) 157. For said one of the first type of vertical-through-via (VTV) connectors 467, if said one of its vertical through vias (VTVs) 358 is made of one or more of the through glass vias (TGVs) 259 as illustrated in one of FIGS. 4A, 4B, 4C, 5A, 5B and 5C, said each opening in the insulating dielectric layer 93 may be vertically under the backside of the copper post 706 of said one or more of its through glass vias (TGVs) 259. For said one of the first type of vertical-through-via (VTV) connectors 467, if said one of its vertical through vias (VTVs) 358 is made of one of the through polymer vias (TPVs) as illustrated in FIG. 6, said each opening in the insulating dielectric layer 93 may be vertically under the backside of the metal pad 336 or copper post 318 of said one of its through polymer vias (TPVs). The backside interconnection scheme for a logic drive or device (BISD) 79 may further include an interconnection metal layer on a bottom surface of its insulating dielectric layer 93, coupling to each of the vertical through vias (VTVs) 358 of each of the first type of vertical-through-via (VTV) connectors 467 through one of the opening in its insulating dielectric layer 93. The interconnection metal layer of the backside interconnection scheme for a logic drive or device (BISD) 79 is patterned with multiple metal pads 583, i.e., metal contacts, each formed on the backside of one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 or formed on the bottom surface of the insulating dielectric layer 93 and vertically under the backside of one of the semiconductor integrated-circuit (IC) chips 100, the backside of one of the first type of operation units 190, the backside of one of the first type of vertical-through-via (VTV) connectors 467 or the bottom surface of the polymer layer 92. Each of the metal pads 583 may be of various types. A first type of metal pad 583 may include (1) an adhesion layer 26a, such as titanium (Ti) or titanium nitride (TiN) layer having a thickness between 1 nm and 50 nm, on the backside of the copper layer 156 of one of the through silicon vias (TSVs) 157 for one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 as illustrated in one of FIGS. 1A, 1C, 1E, 2A, 2C and 2E, the backside of the copper post 706 of one of the through glass vias (TGVs) 259 for one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 as illustrated in one of FIGS. 4A, 4B, 4C, 5A, 5B and 5C or the backside of the metal pad 336 or copper post 318 of one of the through polymer vias (TPVs) for one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 as illustrated in FIG. 6 or on the bottom surface of the insulating dielectric layer 93, (2) a seed layer 26b, such as copper, on its adhesion layer 26a, and (3) a copper layer 32, i.e., copper pad, having a thickness between 1 μm and 60 μm on its seed layer 26b. Alternatively, a second type of metal pad 583 may include the adhesion layer 26a, seed layer 26b and copper layer 32 as mentioned above, and may further include a nickel layer, i.e., nickel pad, having a thickness between 0.5 μm and 10 μm on its copper layer 32. Alternatively, a tin-containing solder bump made of tin or a tin-silver alloy having a thickness between 1 μm and 50 μm may be formed on the copper layer 32 of each of the first type of metal pads 583 or the nickel layer of each of the second type of metal pads 583.

(290) Next, referring to FIG. 22G, multiple metal bumps, pillars or pads 570, i.e., metal contacts, may be formed in an array on the metal pads of the topmost one of the interconnection metal layers 27 of the frontside interconnection scheme for a logic drive or device (FISD) 101 at the bottoms of the respective openings 42a in the topmost one of the polymer layers 42 of the frontside interconnection scheme for a logic drive or device (FISD) 101. Each of the metal bumps, pillars or pads 570 may be of various types. A first type of bump, pillar or pad 570 may include (1) an adhesion layer 26a, such as titanium (Ti) or titanium nitride (TiN) layer having a thickness between 1 nm and 50 nm, on the topmost one of the interconnection metal layers 27 of the frontside interconnection scheme for a logic drive or device (FISD) 101, (2) a seed layer 26b, such as copper, on its adhesion layer 26a and (3) a copper layer 32, i.e., copper pad, having a thickness between 1 μm and 60 μm on its seed layer 26b. Alternatively, a second type of metal bump, pillar or pad 570 may include the adhesion layer 26a, seed layer 26b and copper layer 32 as mentioned above, and may further include a tin-containing solder cap 33, i.e., solder bump, made of tin or a tin-silver alloy having a thickness between 1 μm and 50 μm on its copper layer 32. Alternatively, a third type of metal bump, pillar or pad 570 may include a gold layer, i.e., gold bump, having a thickness between 3 and 15 micrometers over the topmost one of the interconnection metal layers 27 of the frontside interconnection scheme for a logic drive or device (FISD) 101.

(291) Next, referring to FIG. 22G, the polymer layers 42 of the frontside interconnection scheme for a logic drive or device (FISD) 101, the polymer layer 92 and the insulating dielectric layer 93 may be cut or diced to separate multiple individual chip packages 300 as shown in FIG. 22H each for the standard commodity logic drive as illustrated in FIG. 12A by a laser cutting process or by a mechanical cutting process. For the chip package 300 as seen in FIG. 22H, one or more of the interconnection metal layers 27 of its frontside interconnection scheme for a logic drive or device (FISD) 101 may couples each of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 to the other of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467. Each of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190 may couple to one of its metal pads 583 through, in sequence, one or more of the interconnection metal layers 27 of its frontside interconnection scheme for a logic drive or device (FISD) 101 and one of the vertical through vias (VTV) 358 of one of its first type of vertical-through-via (VTV) connectors 467 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals to said each of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467. Each of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 may couple to one or more of its metal bumps, pillars or pads 570 through each of the interconnection metal layers 27 of its frontside interconnection scheme for a logic drive or device (FISD) 101 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals to said each of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467. One of its metal bumps, pillars or pads 570 vertically over each of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190 may couple to one of its metal pads 583 vertically under said each of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190 through, in sequence, each of the interconnection metal layers 27 of its frontside interconnection scheme for a logic drive or device (FISD) 101, one of the vertical through vias (VTVs) 358 of one of its first type of vertical-through-via (VTV) connectors 467 and the interconnection metal layer of its backside interconnection scheme for a logic drive or device (BISD) 79 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals. Each of its metal bumps, pillars or pads 570 having a number of more than 20 may be vertically aligned with one of its metal pads 583 having a number of more than 20. Each of its metal bumps, pillars or pads 570 having a number of more than 50 may be vertically aligned with one of its metal pads 583 having a number of more than 50. Each of the vertical through vias (VTVs) 358 of each of its first type of vertical-through-via (VTV) connectors 467 may have a depth, for example, between 30 μm and 2,000 μm.

(292) For the chip package 300 as seen in FIG. 22H, its metal pads 583 arranged in an array may include multiple dummy pads 583a each not connecting to any of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190 but having mechanical functions for subsequent package-on-package (POP) assembly, formed on the bottom surface of its insulating dielectric layer 93 and vertically under one of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and polymer layer 92. Each of its dummy pads 583a may have no connection to any of the vertical through vias (VTVs) 358 of any of its first type of vertical-through-via (VTV) connectors 467.

(293) Alternatively, FIG. 22I is a schematically cross-sectional view showing a first type of single-chip/unit package in accordance with a first embodiment of the present application. The chip package 300 as seen in FIG. 22I may have a similar structure to that as illustrated in FIG. 22H. For an element indicated by the same reference number shown in FIGS. 22H and 22I, the specification of the element as seen in FIG. 22I may be referred to that of the element as illustrated in FIG. 22H. The difference between the chip packages as illustrated in FIGS. 22H and 22I is that the chip package as seen in FIG. 22I includes only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190 having the same specification as illustrated in FIG. 22A and one or more first type of vertical-through-via (VTV) connectors 467 having the same specification as illustrated in FIG. 22A. For the single-chip/unit package 300 as seen in FIG. 22I, its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190 may couple to one of its metal pads 583 through, in sequence, one or more of the interconnection metal layers 27 of its frontside interconnection scheme for a logic drive or device (FISD) 101 and one of the vertical through vias (VTVs) 358 of one of its first type of vertical-through-via (VTV) connectors 467 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals to its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190. Each of its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190 and its first type of vertical-through-via (VTV) connectors 467 may couple to one or more of its metal bumps, pillars or pads 570 through each of the interconnection metal layers 27 of its frontside interconnection scheme for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals to its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190. One of its metal bumps, pillars or pads 570 vertically over its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190 may couple to one of its metal pads 583 vertically under its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190 through, in sequence, each of the interconnection metal layers 27 of its frontside interconnection scheme for a logic drive or device (FISD) 101, one of the vertical through vias (VTVs) 358 of one of its first type of vertical-through-via (VTV) connectors 467 and the interconnection metal layer of its backside interconnection scheme for a logic drive or device (BISD) 79 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals. Each of its metal bumps, pillars or pads 570 having a number of more than 20 may be vertically aligned with one of its metal pads 583 having a number of more than 20. Alternatively, each of its metal bumps, pillars or pads 570 having a number of more than 50 may be vertically aligned with one of its metal pads 583 having a number of more than 50. For example, its more than twenty first metal contacts, i.e., metal bumps, pillars or pads 570, may be vertically over its only one semiconductor integrated-circuit (IC) chip 100 and its more than twenty second metal contacts, i.e., metal pads 583, may be vertically under its only one semiconductor integrated-circuit (IC) chip 100. Each of the vertical through vias (VTVs) 358 of each of its first type of vertical-through-via (VTV) connector(s) 467 may have a depth, for example, between 30 μm and 2,000 μm.

(294) 2. Second Type of Chip Package for First Embodiment

(295) FIGS. 23A and 23B are schematically cross-sectional views showing a process for forming a second type of multichip package in accordance with a first embodiment of the present application. For an element indicated by the same reference number shown in FIGS. 22A-22H, 23A and 23B, the specification of the element as seen in FIG. 23A or 23B may be referred to that of the element as illustrated in FIGS. 22A-22H. After the structure as seen in FIG. 22F is formed, a backside interconnection scheme for a logic drive or device (BISD) 79 may be formed on the backside of each of the semiconductor integrated-circuit (IC) chips 100, the backside of each of the first type of operation units 190, the backside of each of the first type of vertical-through-via (VTV) connectors 467 and the bottom surface of the polymer layer 92. The backside interconnection scheme for a logic drive or device (BISD) 79 may include one or more interconnection metal layers 27 coupling to each of the vertical through vias (VTVs) 358 of each of the first type of vertical-through-via (VTV) connectors 467 and one or more polymer layers 42, i.e., insulating dielectric layers, each between neighboring two of its interconnection metal layers 27, under the bottommost one of its interconnection metal layers 27 or over the topmost one of its interconnection metal layers 27, wherein an upper one of its interconnection metal layers 27 may couple to a lower one of its interconnection metal layers 27 through an opening in one of its polymer layers 42 between the upper and lower ones of its interconnection metal layers 27. The topmost one of its polymer layers 42 may be between the topmost one of its interconnection metal layers 27 and the backside of each of the semiconductor integrated-circuit (IC) chips 100, between the topmost one of its interconnection metal layers 27 and the backside of each of the first type of operation units 190, between the topmost one of its interconnection metal layers 27 and the backside of each of the first type of vertical-through-via (VTV) connectors 467 and between the topmost one of its interconnection metal layers 27 and the bottom surface of the polymer layer 92, wherein each opening in the topmost one of its polymer layers 42 may be vertically under the backside of one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467. For the backside interconnection scheme for a logic drive or device (BISD) 79, each of its interconnection metal layers 27 may extend horizontally across an edge of each of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467. The bottommost one of its interconnection metal layers 27 may be patterned with multiple metal pads 583 aligned with multiple respective openings in the bottommost one of its polymer layers 42.

(296) Referring to FIG. 23A, for the backside interconnection scheme for a logic drive or device (BISD) 79, each of its polymer layers 42 may be a layer of polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer or silicone, having a thickness between, for example, 0.3 μm and 50 μm, 0.3 μm and 30 μm, 0.5 μm and 20 μm, 1 μm and 10 μm, or 0.5 μm and 5 μm, or thicker than or equal to 0.3 μm, 0.5 μm, 0.7 μm, 1 μm, 1.5 μm, 2 μm, 3 μm or 5 μm. Each of its interconnection metal layers 27 may be provided with multiple metal traces or lines each including (1) a copper layer 40 having one or more upper portions in openings in one of its polymer layers 42 having a thickness between 0.3 μm and 20 μm, and an lower portion having a thickness 0.3 μm and 20 μm under said one of its polymer layers 42, (2) an adhesion layer 28a, such as titanium or titanium nitride having a thickness between 1 nm and 50 nm, at a top and sidewall of each of the one or more upper portions of the copper layer 40 of said each of the metal traces or lines and at a top of the lower portion of the copper layer 40 of said each of the metal traces or lines, and (3) a seed layer 28b, such as copper, between the copper layer 40 and adhesion layer 28a of said each of the metal traces or lines, wherein the lower portion of the copper layer 40 of said each of the metal traces or lines may have a sidewall not covered by the adhesion layer 28a of said each of the metal traces or lines. Each of its interconnection metal layers 27 may provide multiple metal lines or traces with a thickness between, for example, 0.3 μm and 40 μm, 0.5 μm and 30 μm, 1 μm and 20 μm, 1 μm and 15 μm, 1 μm and 10 μm, or 0.5 μm to 5 μm, or thicker than or equal to 0.3 μm, 0.7 μm, 1 μm, 2 μm, 3 μm, 5 μm, 7 μm or 10 μm, and a width between, for example, 0.3 μm and 40 μm, 0.5 μm and 30 μm, 1 μm and 20 μm, 1 μm and 15 μm, 1 μm and 10 μm, or 0.5 μm to 5 μm, or wider than or equal to 0.3 μm, 0.7 μm, 1 μm, 2 μm, 3 μm, 5 μm, 7 μm or 10 μm. Each of its interconnection metal layers 27 may have two planes used respectively for power and ground planes of a power supply and/or used as a heat dissipater or spreader for the heat dissipation or spreading, wherein each of the two planes may have a thickness, for example, between 5 μm and 50 μm, 5 μm and 30 μm, 5 μm and 20 μm, or 5 μm and 15 μm; or thicker than or equal to 5 μm, 10 μm, 20 μm, or 30 μm. The two planes may be layout as interlaced or interleaved shaped structures in a plane or may be layout in a fork shape.

(297) Referring to FIG. 23A, each of the metal pads 583 may be of various types. A first type of metal pad 583 may include (1) an adhesion layer 28a, such as titanium (Ti) or titanium nitride (TiN) layer having a thickness between 1 nm and 50 nm, on a bottom surface of a second bottommost one of the polymer layers 42 of the backside interconnection scheme for a logic drive or device (BISD) 79, (2) a seed layer 28b, such as copper, on a bottom surface of its adhesion layer 28a, and (3) a copper layer 40, i.e., copper pad, having a thickness between 0.3 μm and 20 μm on a bottom surface of its seed layer 28b and at a top of one of the openings in the bottommost one of its polymer layers 42. Alternatively, a second type of metal pad 583 may include the adhesion layer 28a, seed layer 28b and copper layer 40 as mentioned above, and may further include a nickel layer, i.e., nickel pad, having a thickness between 0.5 μm and 10 μm on a bottom surface of its copper layer 32 and in one of the openings in the bottommost one of its polymer layers 42. Alternatively, a tin-containing solder bump made of tin or a tin-silver alloy having a thickness between 1 μm and 50 μm may be formed under the bottom surface of the copper layer 32 of each of the first type of metal pads 583 or a bottom surface of the nickel layer of each of the second type of metal pads 583.

(298) Next, referring to FIG. 23A, metal bumps, pillars or pads 570 may be formed in an array on the metal pads of the topmost one of the interconnection metal layers 27 of the frontside interconnection scheme for a logic drive or device (FISD) 101 at the bottoms of the respective openings 42a in the topmost one of the polymer layers 42 of the frontside interconnection scheme for a logic drive or device (FISD) 101. Each of the metal bumps, pillars or pads 570 may be of one of the first through third types having the same specifications as the first through third types of metal bumps, pillars or pads 570 as illustrated in FIG. 22G, respectively.

(299) Next, referring to FIG. 23A, the polymer layers 42 of the frontside interconnection scheme for a logic drive or device (FISD) 101, the polymer layer 92 and the polymer layers 42 of the backside interconnection scheme for a logic drive or device (BISD) 79 may be cut or diced to separate multiple individual chip packages 300 as shown in FIG. 23B each for the standard commodity logic drive as illustrated in FIG. 12A by a laser cutting process or by a mechanical cutting process. For the chip package 300 as seen in FIG. 23B, each of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190 may couple to one of its metal pads 583 through, in sequence, one or more of the interconnection metal layers 27 of its frontside interconnection scheme for a logic drive or device (FISD) 101, one of the vertical through vias (VTVs) 358 of one of its first type of vertical-through-via (VTV) connectors 467 and each of the interconnection metal layer 27 of its backside interconnection scheme for a logic drive or device (BISD) 79 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals to said each of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190. One of its metal bumps, pillars or pads 570 vertically over each of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190 may couple to one of its metal pads 583 vertically under said each of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190 through, in sequence, each of the interconnection metal layers 27 of its frontside interconnection scheme for a logic drive or device (FISD) 101, one of the vertical through vias (VTVs) 358 of one of its first type of vertical-through-via (VTV) connectors 467 and each of the interconnection metal layers 27 of its backside interconnection scheme for a logic drive or device (BISD) 79 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals. Each of its metal bumps, pillars or pads 570 having a number of more than 20 may be vertically aligned with one of its metal pads 583 having a number of more than 20. Alternatively, each of its metal bumps, pillars or pads 570 having a number of more than 50 may be vertically aligned with one of its metal pads 583 having a number of more than 50. Each of the vertical through vias (VTVs) 358 of each of its first type of vertical-through-via (VTV) connectors 467 may have a depth, for example, between 30 μm and 2,000 μm.

(300) Alternatively, the chip packages 300 may further include multiple dummy chips 409 each arranged between two of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467, between its edge and one of its first type of semiconductor chips 100 or between its edge and one of its first type of vertical-through-via (VTV) connectors 467, as seen in FIGS. 23C and 23D, wherein each of the dummy chips 409 may not provide any electrical function.

(301) FIG. 23C is a schematically top view showing a second type of multichip package in accordance with a first embodiment of the present application, wherein FIG. 23B is a schematically cross-sectional view along a cross-sectional line C-C on FIG. 23C, and FIG. 23D is a schematically cross-sectional view along a cross-sectional line D-D on FIG. 23C. For an element indicated by the same reference number shown in FIGS. 22A-22H and 23A-23D, the specification of the element as seen in FIG. 23C or 23D may be referred to that of the element as illustrated in FIG. 22A-22H, 23A or 23B. For a process for fabricating the chip packages 300, multiple dummy chips 409 may be further provided to have a backside side of each of the dummy chips 409 attached to the sacrificial bonding layer 591 in the step as illustrated in FIG. 22A. Next, in the step as illustrated in FIG. 22B, the polymer layer 92 may be formed further over a frontside of each of the dummy chips 409 and in multiple gaps each between one of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 and one of the dummy chips 409. Next, in the step as illustrated in FIG. 22C, the chemical mechanical polishing (CMP), polishing or grinding process may be performed further to remove a top portion of each of the dummy chips 409 and to planarize the frontside of each of the dummy chips 409 with the top surface of the polymer layer 92. Next, in the step as illustrated in FIG. 22D, the bottommost one of the polymer layers 42 of the frontside interconnection scheme for a logic drive or device (FISD) 101 may be further formed on the frontside of each of the dummy chips 409. Next, in the step as illustrated in FIG. 22E, the temporary substrate (T-sub) 590 as shown in FIG. 22D may be removed further from the backside of each of the dummy chips 409. Next, in the step as illustrated in FIG. 22F, the chemical mechanical polishing (CMP), polishing or grinding process may be applied further to remove a bottom portion of each of the dummy chips 409. Next, in the step as illustrated in FIG. 23A, the topmost one of the polymer layers 42 of the backside interconnection scheme for a logic drive or device (BISD) 79 may be further formed on the backside of each of the dummy chips 409. Next, in the step as illustrated in FIG. 23A, one or more of the metal bumps, pillars or pads 570 may be formed vertically over each of the dummy chips 409. Next, referring to FIG. 23A, the polymer layers 42 of the front side interconnection scheme for a logic drive or device (FISD) 101, the polymer layer 92, one or more of the dummy chips 409 and the polymer layers 42 of the backside interconnection scheme for a logic drive or device (BISD) 79 may be cut or diced to separate the individual chip packages 300 as shown in each of FIGS. 23B-23D by a laser cutting process or by a mechanical cutting process, and thus each of said one or more of the dummy chips 409 may have a sidewall 409a exposed and not covered by the polymer layer 92. For each of the chip packages 300 as seen in FIGS. 23B-23D, when a width or distance Wd1 between neighboring two of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 may range from 500 to 2500 micrometers or from 700 to 1800 micrometers or may be greater than 600, 800, 1200 or 1500 micrometers, one of its dummy chips 409 may be arranged between said neighboring two of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467.

(302) When a width or distance Wd2 between one of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 and its edge may range from 500 to 2500 micrometers or from 700 to 1800 micrometers or may be greater than 600, 800, 1200 or 1500 micrometers, one of its dummy chips 409 may be arranged between said one of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 and its edge. A width or distance Wd3 between one of its dummy chips 409 and its edge may range from 30 to 300 micrometers, from 50 to 200 micrometers or from 80 to 120 micrometers or may be smaller than 300 or 200 micrometers. A width or distance Wd4 between one of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190 and one of its first type of vertical-through-via (VTV) connectors 467 may range from 30 to 300 micrometers, from 50 to 200 micrometers or from 80 to 120 micrometers or may be smaller than 300 or 200 micrometers. A width or distance Wd5 between one of its first type of vertical-through-via (VTV) connectors 467 and one of its dummy chips 409 may range from 30 to 300 micrometers, from 50 to 200 micrometers or from 80 to 120 micrometers or may be smaller than 300 or 200 micrometers. A width or distance Wd6 between one of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190 and one of its dummy chips 409 may range from 30 to 300 micrometers, from 50 to 200 micrometers or from 80 to 120 micrometers or may be smaller than 300 or 200 micrometers.

(303) Alternatively, FIG. 23E is a schematically cross-sectional view showing a second type of single-chip/unit package in accordance with a first embodiment of the present application. The chip package 300 as seen in FIG. 23E may have a similar structure to that as illustrated in FIG. 23B. For an element indicated by the same reference number shown in FIGS. 22A-22I, 23A, 23B and 23E, the specification of the element as seen in FIG. 23E may be referred to that of the element as illustrated in FIG. 22A-22I, 23A or 23B. The difference between the chip packages as illustrated in FIGS. 23B and 23E is that the chip package as seen in FIG. 23E may include only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190 having the same specification as illustrated in FIG. 22A and one or more first type of vertical-through-via (VTV) connectors 467 having the same specification as illustrated in FIG. 22A. For the single-chip/unit package 300 as seen in FIG. 23E, its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190 may couple to one of its metal pads 583 through, in sequence, one or more of the interconnection metal layers 27 of its frontside interconnection scheme for a logic drive or device (FISD) 101, one of the vertical through vias (VTVs) 358 of one of its first type of vertical-through-via (VTV) connectors 467 and each of the interconnection metal layer 27 of its backside interconnection scheme for a logic drive or device (BISD) 79 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals to its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190. One of its metal bumps, pillars or pads 570 vertically over its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190 may couple to one of its metal pads 583 vertically under its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190 through, in sequence, each of the interconnection metal layers 27 of its frontside interconnection scheme for a logic drive or device (FISD) 101, one of the vertical through vias (VTVs) 358 of one of its first type of vertical-through-via (VTV) connectors 467 and each of the interconnection metal layers 27 of its backside interconnection scheme for a logic drive or device (BISD) 79 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals. Each of its metal bumps, pillars or pads 570 having a number of more than 20 may be vertically aligned with one of its metal pads 583 having a number of more than 20. Alternatively, each of its metal bumps, pillars or pads 570 having a number of more than 50 may be vertically aligned with one of its metal pads 583 having a number of more than 50. For example, its more than twenty first metal contacts, i.e., metal bumps, pillars or pads 570, may be vertically over its only one semiconductor integrated-circuit (IC) chip 100 and its more than twenty second metal contacts, i.e., metal pads 583, may be vertically under its only one semiconductor integrated-circuit (IC) chip 100. Each of the vertical through vias (VTVs) 358 of each of its first type of vertical-through-via (VTV) connector(s) 467 may have a depth, for example, between 30 μm and 2,000 μm.

(304) 3. Package-on-package (POP) Assembly for First Type of Chip Packages for First Embodiment

(305) FIGS. 24A and 24B are schematically cross-sectional views showing a process for forming various package-on-package (POP) assemblies for multiple first type of chip packages in accordance with a first embodiment of the present application. Multiple first type of chip packages 300 as illustrated in FIG. 22H may be provided to be stacked together to form a package-on-package (POP) assembly as seen in FIG. 24A.

(306) Referring to FIG. 24A, the temporary substrate (T-Sub) 590 as illustrated in FIG. 22A may be first provided. Next, the bottommost one of the first type of chip packages 300 as illustrated in FIG. 22H or 22I may be flipped to be attached onto the temporary substrate (T-sub) 590, wherein the bottommost one of the first type of chip packages 300 may have the metal bumps, pillars or pads 570 embedded in the sacrificial bonding layer 591 of the temporary substrate (T-Sub) 590. The sacrificial bonding layer 591 may have a top surface in contact with a bottom surface of the bottommost one of the polymer layers 42 of the frontside interconnection scheme for a logic drive or device (FISD) 101 of the bottommost one of the first type of chip packages 300.

(307) Next, referring to FIG. 24A, in a first step, an upper one of the first type of chip packages 300 as illustrated in FIG. 22H may be flipped to have its metal bumps, pillars or pads 570 to be bonded respectively to the metal pads 583 of a lower one of the first type of chip packages 300 as illustrated in FIG. 22H or the tin-containing solder bumps on the metal pads 583 of the lower one of the first type of chip packages 300 as illustrated in FIG. 22H. Alternatively, an upper one of the first type of chip packages 300 as illustrated in FIG. 22I may be flipped to have its metal bumps, pillars or pads 570 to be bonded respectively to the metal pads 583 of a lower one of the first type of chip packages 300 as illustrated in FIG. 22I or the tin-containing solder bumps on the metal pads 583 of the lower one of the first type of chip packages 300 as illustrated in FIG. 22I. For example, for a first case, each of the metal bumps, pillars or pads 570 of the upper one of the first type of chip packages 300 may be of the second type, having the solder cap 33 to be bonded onto the copper layer 32 of one of the first type of metal pads 583 of the lower one of the first type of chip packages 300. For a second case, each of the metal bumps, pillars or pads 570 of the upper one of the first type of chip packages 300 may be of the second type, having the solder cap 33 to be bonded onto the tin-containing solder bumps on one of the metal pads 583 of the lower one of the first type of chip packages 300. For a third case, each of the metal bumps, pillars or pads 570 of the upper one of the first type of chip packages 300 may be of the first type, having the copper layer 32 to be bonded onto the tin-containing solder bump on one of the metal pads 583 of the lower one of the first type of chip packages 300. It is noted that the lower one of the first type of chip packages 300 may have the dummy pads 583a in a first group each coupling to one of the metal bumps, pillars or pads 570 of the upper one of the first type of chip packages 300 at a voltage (Vss) of ground reference and the dummy pads 583a in a second group each coupling to one of the metal bumps, pillars or pads 570 of the upper one of the first type of chip packages 300 without any electrical function.

(308) Next, referring to FIG. 24A, in a second step, an underfill 564 may be filled into a gap between the upper and lower ones of the first type of chip packages 300 to enclose the metal bumps, pillars or pads 570 of the upper one of the first type of chip packages 300.

(309) Next, referring to FIG. 24A, the above first and second steps may be alternately repeated multiple times to stack, one by one, multiple of the first type of chip packages 300 as illustrated in FIG. 22H or 22I having the number greater than or equal to two, such as four or eight.

(310) Next, referring to FIG. 24A, the temporary substrate (T-sub) 590 may be released as illustrated in FIG. 22E from the bottommost one of the first type of chip packages 300 to expose the metal bumps, pillars or pads 570 of the bottommost one of the first type of chip packages 300.

(311) For the package-on-package (POP) assembly as illustrated in FIG. 24A, the interconnection metal layers 27 of the frontside interconnection scheme for a logic drive or device (FISD) 101 of each of its first type of chip packages 300 may have the same circuit layout as those of each of the other(s) of its first type of chip packages 300 and the interconnection metal layer of the backside interconnection scheme for a logic drive or device (BISD) 79 of each of its first type of chip packages 300 may have the same circuit layout as that of each of the other(s) of its first type of chip packages 300. Each of the metal bumps, pillars or pads 570 of each of its first type of chip packages 300 may be vertically aligned with one of the metal pads 583 of said each of its first type of chip packages 300, one of the metal bumps, pillars or pads 570 of each of the other(s) of its first type of chip packages 300 and one of the metal pads 583 of each of the other(s) of its first type of chip packages 300. One of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 of each of its first type of chip packages 300 may be vertically aligned with and couple to one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 of one of the other(s) of its first type of chip packages 300, one of the metal bumps, pillars or pads 570 of each of its first type of chip packages 300 and one of the metal pads 583 of each of its first type of chip packages 300, and may further couple to one or more of the semiconductor integrated-circuit (IC) chips 100 of each of its first type of chip packages 300 and/or one or more of the first type of operation units 190 of each of its first type of chip packages 300, as seen for a first interconnect 301 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals to said one or more of the semiconductor integrated-circuit (IC) chips 100 and/or said one or more of the first type of operation units 190. Alternatively, one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 of each of its first type of chip packages 300 may be vertically aligned with and couple to one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 of each of the other(s) of its first type of chip packages 300, one of the metal bumps, pillars or pads 570 of each of its first type of chip packages 300 and one of the metal pads 583 of each of its first type of chip packages 300, but may not couple to any of the semiconductor integrated-circuit (IC) chips 100 of any of its first type of chip packages 300 and any of the first type of operation units 190 of any of its first type of chip packages 300, as seen for a second interconnect 302 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals. Alternatively, one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 of the lower one of its first type of chip packages 300 may be vertically aligned with and couple to one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 of the upper one of its first type of chip packages 300 and may further couple to one or more of the semiconductor integrated-circuit (IC) chips 100 of each of the lower and upper ones of its first type of chip packages 300 and/or one or more of the first type of operation units 190 of each of the lower and upper ones of its first type of chip packages 300, as seen for a third interconnect 303 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals to said one or more of the semiconductor integrated-circuit (IC) chips 100 and/or said one or more of the first type of operation units 190, wherein the third interconnect 303 may encompass one of the metal pads 583 of the lower one of its first type of chip packages 300 and one of the metal bumps, pillars or pads 570 of the upper one of its first type of chip packages 300 bonded between said one or more of the semiconductor integrated-circuit (IC) chips 100 of the upper and lower ones of its first type of chip packages 300 or between said one or more of the first type of operation units 190 of the upper and lower ones of its first type of chip packages 300, coupling to said one of the vertical through vias (VTVs) 358 of said one of the first type of vertical-through-via (VTV) connectors 467 of the lower one of its first type of chip packages 300 and said one of the vertical through vias (VTVs) 358 of said one of the first type of vertical-through-via (VTV) connectors 467 of the upper one of its first type of chip packages 300 and coupling to said one or more of the semiconductor integrated-circuit (IC) chips 100 of said each of the lower and upper ones of its first type of chip packages 300 and/or said one or more of the first type of operation units 190 of said each of the lower and upper ones of its first type of chip packages 300.

(312) Alternatively, the interconnection metal layers 27 of the frontside interconnection scheme for a logic drive or device (FISD) 101 of each of its first type of chip packages 300 may have a different circuit layout from those of each of the other(s) of its first type of chip packages 300, as seen in FIG. 24B. For an element indicated by the same reference number shown in FIGS. 24A and 24B, the specification of the element as seen in FIG. 24B may be referred to that of the element as illustrated in FIG. 24A. For the package-on-package (POP) assembly as illustrated in FIG. 24B, one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 of each of its first type of chip packages 300 may be vertically aligned with and couple to one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 of one of the other(s) of its first type of chip packages 300, one of the metal bumps, pillars or pads 570 of each of its first type of chip packages 300 and one of the metal pads 583 of each of its first type of chip packages 300, may couple to one or more of the semiconductor integrated-circuit (IC) chips 100 of the lower one of its first type of chip packages 300 and/or one or more of the first type of operation units 190 of the lower one of its first type of chip packages 300 and may not couple to any of the semiconductor integrated-circuit (IC) chips 100 of the upper one of its first type of chip packages 300 and any of the first type of operation units 190 of the upper one of its first type of chip packages 300, as seen for a fourth interconnect 304 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals to said one or more of the semiconductor integrated-circuit (IC) chips 100 and/or said one or more of the first type of operation units 190. One of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 of the lower one of its first type of chip packages 300, one of the metal pads 583 of the lower one of its first type of chip packages 300 and one of the metal bumps, pillars or pads 570 of the upper one of its first type of chip packages 300 may couple one or more of the semiconductor integrated-circuit (IC) chips 100 of the upper one of its first type of chip packages 300 and/or one or more of the first type of operation units 190 of the upper one of its first type of chip packages 300 to one of the metal bumps, pillars or pads 570 of the lower one of its first type of chip packages 300 but may not couple to any of the semiconductor integrated-circuit (IC) chips 100 of the lower one of its first type of chip packages 300 and any of the first type of operation units 190 of the lower one of its first type of chip packages 300 and to any of the metal pads 583 of the upper one of its first type of chip packages 300, as seen for a fifth interconnect 305 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals to said one or more of the semiconductor integrated-circuit (IC) chips 100 and/or said one or more of the first type of operation units 190. One of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 of the lower one of its first type of chip packages 300, one of the metal pads 583 of the lower one of its first type of chip packages 300 and one of the metal bumps, pillars or pads 570 of the upper one of its first type of chip packages 300 may couple one or more of the semiconductor integrated-circuit (IC) chips 100 of the upper one of its first type of chip packages 300 and/or one or more of the first type of operation units 190 of the upper one of its first type of chip packages 300 to one or more of the semiconductor integrated-circuit (IC) chips 100 of the lower one of its first type of chip packages 300 and/or one or more of the first type of operation units 190 of the lower one of its first type of chip packages 300 but may not couple to any of the metal bumps, pillars or pads 570 of the lower one of its first type of chip packages 300 and any of the metal pads 583 of the upper one of its first type of chip packages 300, as seen for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals to said one or more of the semiconductor integrated-circuit (IC) chips 100 of the upper one of its first type of chip packages 300 and/or said one or more of the first type of operation units 190 of the upper one of its first type of chip packages 300 or to said one or more of the semiconductor integrated-circuit (IC) chips 100 of the lower one of its first type of chip packages 300 and/or said one or more of the first type of operation units 190 of the lower one of its first type of chip packages 300.

(313) 4. Package-on-package (POP) Assembly for Second Type of Chip Packages for First Embodiment

(314) FIG. 25 is a schematically cross-sectional view showing a process for forming a package-on-package (POP) assembly for multiple second type of chip packages in accordance with a first embodiment of the present application. Multiple second type of chip packages 300 as illustrated in FIG. 23B may be provided to be stacked together to form a package-on-package (POP) assembly as seen in FIG. 25.

(315) Referring to FIG. 25, the temporary substrate (T-Sub) 590 as illustrated in FIG. 22A may be first provided. Next, the bottommost one of the second type of chip packages 300 as illustrated in FIG. 23B or 23E may be flipped to be attached onto the temporary substrate (T-sub) 590, wherein the bottommost one of the second type of chip packages 300 may have the metal bumps, pillars or pads 570 embedded in the sacrificial bonding layer 591 of the temporary substrate (T-Sub) 590. The sacrificial bonding layer 591 may have a top surface in contact with a bottom surface of the bottommost one of the polymer layers 42 of the frontside interconnection scheme for a logic drive or device (FISD) 101 of the bottommost one of the second type of chip packages 300.

(316) Next, referring to FIG. 25, in a first step, an upper one of the second type of chip packages 300 as illustrated in FIG. 23B may be flipped to have the metal bumps, pillars or pads 570 to be bonded respectively to the metal pads 583 of a lower one of the second type of chip packages 300 as illustrated in FIG. 23B or the tin-containing solder bumps on the metal pads 583 of the lower one of the second type of chip packages 300 as illustrated in FIG. 23B. Alternatively, an upper one of the second type of chip packages 300 as illustrated in FIG. 23E may be flipped to have the metal bumps, pillars or pads 570 to be bonded respectively to the metal pads 583 of a lower one of the second type of chip packages 300 as illustrated in FIG. 23E or the tin-containing solder bumps on the metal pads 583 of the lower one of the second type of chip packages 300 as illustrated in FIG. 23E. The first step may have the same specification or details as that illustrated in FIG. 24A.

(317) Next, referring to FIG. 25, in a second step, an underfill 564 may be filled into a gap between the upper and lower ones of the second type of chip packages 300 to enclose the metal bumps, pillars or pads 570 of the upper one of the second type of chip packages 300.

(318) Next, referring to FIG. 25, the above first and second steps may be alternately repeated multiple times to stack, one by one, multiple of the second type of chip packages 300 as illustrated in FIG. 23B or 23C having the number greater than or equal to two, such as four or eight.

(319) Next, referring to FIG. 25, the temporary substrate (T-sub) 590 may be released as illustrated in FIG. 22E from the bottommost one of the second type of chip packages 300 to expose the metal bumps, pillars or pads 570 of the bottommost one of the second type of chip packages 300.

(320) For the package-on-package (POP) assembly as illustrated in FIG. 25, the interconnection metal layers 27 of the frontside interconnection scheme for a logic drive or device (FISD) 101 of each of its second type of chip packages 300 may have the same circuit layout as those of each of the other(s) of its second type of chip packages 300 and the interconnection metal layers 27 of the backside interconnection scheme for a logic drive or device (BISD) 79 of each of its second type of chip packages 300 may have the same circuit layout as those of each of the other(s) of its second type of chip packages 300. Each of the metal bumps, pillars or pads 570 of each of its second type of chip packages 300 may be vertically aligned with one of the metal pads 583 of said each of its second type of chip packages 300, one of the metal bumps, pillars or pads 570 of each of the other(s) of its second type of chip packages 300 and one of the metal pads 583 of each of the other(s) of its second type of chip packages 300. One of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 of each of its second type of chip packages 300 may be vertically aligned with and couple to one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 of one of the other(s) of its second type of chip packages 300, one of the metal bumps, pillars or pads 570 of each of its second type of chip packages 300 and one of the metal pads 583 of each of its second type of chip packages 300, but may not couple to any of the semiconductor integrated-circuit (IC) chips 100 of any of its second type of chip packages 300 and any of the first type of operation units 190 of any of its second type of chip packages 300, as seen for a seventh interconnect 307 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals. Alternatively, one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 of the lower one of its second type of chip packages 300 may be vertically aligned with and couple to one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 of the upper one of its second type of chip packages 300 and may further couple to one or more of the semiconductor integrated-circuit (IC) chips 100 of each of the lower and upper ones of its second type of chip packages 300 and/or one or more of the first type of operation units 190 of each of the lower and upper ones of its second type of chip packages 300, as seen for an eighth interconnect 308 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals to said one or more of the semiconductor integrated-circuit (IC) chips 100 and/or said one or more of the first type of operation units 190, wherein the eighth interconnect 308 may encompass one of the metal pads 583 of the lower one of its second type of chip packages 300 and one of the metal bumps, pillars or pads 570 of the upper one of its second type of chip packages 300 bonded between said one or more of the semiconductor integrated-circuit (IC) chips 100 of the upper and lower ones of its second type of chip packages 300 or between said one or more of the first type of operation units 190 of the upper and lower ones of its second type of chip packages 300, coupling to said one of the vertical through vias (VTVs) 358 of said one of the first type of vertical-through-via (VTV) connectors 467 of the lower one of its second type of chip packages 300 and said one of the vertical through vias (VTVs) 358 of said one of the first type of vertical-through-via (VTV) connectors 467 of the upper one of its second type of chip packages 300 and coupling to said one or more of the semiconductor integrated-circuit (IC) chips 100 of said each of the lower and upper ones of its second type of chip packages 300 and/or said one or more of the first type of operation units 190 of said each of the lower and upper ones of its second type of chip packages 300.

(321) Specification for Fan-Out Interconnection Scheme for Logic Drive or Device (FOISD)

(322) FIG. 26 is a schematically cross-sectional view showing a fan-out interconnection scheme in accordance with various embodiments of the present application. Referring to FIG. 26, the temporary substrate (T-Sub) 590 as illustrated in FIG. 22A may be first provided. Next, a fan-out interconnection scheme for a logic drive or device (FOISD) 592 may be formed on the sacrificial bonding layer 591 of the temporary substrate (T-Sub) 590. The fan-out interconnection scheme for a logic drive or device (FOISD) 592 may include one or more interconnection metal layers 27 and one or more polymer layers 42 each between neighboring two of its interconnection metal layers 27, under the bottommost one of its interconnection metal layers 27 or over the topmost one of its interconnection metal layers 27, wherein an upper one of its interconnection metal layers 27 may couple to a lower one of its interconnection metal layers 27 through an opening in one of its polymer layers 42 between the upper and lower ones of its interconnection metal layers 27. The bottommost one of its polymer layers 42 may be between the bottommost one of its interconnection metal layers 27 and the sacrificial bonding layer 591. The topmost one of its interconnection metal layers 27 may have multiple metal pads at bottoms of multiple openings 42a in the topmost one of its polymer layers 42.

(323) Referring to FIG. 26, for the fan-out interconnection scheme for a logic drive or device (FOISD) 592, each of its polymer layers 42 may be a layer of polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer or silicone, having a thickness between, for example, 0.3 μm and 20 μm, 0.5 μm and 10 μm, 1 μm and 5 μm, or 1 μm and 10 μm or thicker than or equal to 0.3 μm, 0.5 μm, 0.7 μm, 1 μm, 1.5 μm, 2 μm or 3 μm. Each of its interconnection metal layers 27 may be provided with multiple metal traces or lines each including (1) a copper layer 40 having one or more lower portions in openings in one of its polymer layers 42 having a thickness between 0.3 μm and 20 μm, and an upper portion having a thickness 0.3 μm and 20 μm over said one of its polymer layers 42, (2) an adhesion layer 28a, such as titanium or titanium nitride having a thickness between 1 nm and 50 nm, at a bottom and sidewall of each of the one or more lower portions of the copper layer 40 of said each of the metal traces or lines and at a bottom of the upper portion of the copper layer 40 of said each of the metal traces or lines, and (3) a seed layer 28b, such as copper, between the copper layer 40 and adhesion layer 28a of said each of the metal traces or lines, wherein the upper portion of the copper layer 40 of said each of the metal traces or lines may have a sidewall not covered by the adhesion layer 28a of said each of the metal traces or lines. Each of its interconnection metal layers 27 may provide multiple metal lines or traces with a thickness between, for example, 0.3 μm and 20 μm, 0.5 μm and 10 μm, 1 μm and 5 μm, 1 μm and 10 μm, or 2 μm and 10 μm, or thicker than or equal to 0.3 μm, 0.5 μm, 0.7 μm, 1 μm, 1.5 μm, 2 μm or 3 μm, and a width between, for example, 0.3 μm and 20 μm, 0.5 μm and 10 μm, 1 μm and 5 μm, 1 μm and 10 μm, or 2 μm and 10 μm, or wider than or equal to 0.3 μm, 0.5 μm, 0.7 μm, 1 μm, 1.5 μm, 2 μm or 3 μm.

(324) Next, referring to FIG. 26. the fan-out interconnection scheme for a logic drive or device (FOISD) may further include multiple micro-bumps or micro-pads 35 on the metal pads of the topmost one of the interconnection metal layers 27 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592. Each of its micro-bumps or micro-pads 35 may be of various types. A first type of micro-bump or micro-pad 35 may include (1) an adhesion layer 26a, such as titanium (Ti) or titanium nitride (TiN) layer having a thickness between 1 nm and 50 nm, on the copper layer 40 of the topmost one of the interconnection metal layers 27 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592, (2) a seed layer 26b, such as copper, on its adhesion layer 26a and (3) a copper layer 32 having a thickness between 1 nm and 60 nm on its seed layer 26b.

(325) Alternatively, referring to FIG. 26, a second type of micro-bump or micro-pad 35 may include the adhesion layer 26a, seed layer 26b and copper layer 32 as mentioned above, and may further include a tin-containing solder cap made of tin or a tin-silver alloy having a thickness between 1 nm and 50 nm on its copper layer 32.

(326) Alternatively, referring to FIG. 26, a third type of micro-bump or micro-pad 35 may be a thermal compression bump, including the adhesion layer 26a and seed layer 26b as mentioned above, and further including, as seen as the third type of micro-bump or micro-pad 34 in any of FIGS. 28A, 29A, 35A and 36A, a copper layer 37 having a thickness t3 between 2 nm and 20 nm and a largest transverse dimension w3, such as diameter in a circular shape, between 1 nm and 25 nm on its seed layer 26b and a solder cap 38 made of a tin-silver alloy, a tin-gold alloy, a tin-copper alloy, a tin-indium alloy, indium or tin, which has a thickness between 1 nm and 15 nm and a largest transverse dimension, such as diameter in a circular shape, between 1 nm and 15 nm on its copper layer 37. A pitch between neighboring two of the third type of micro-bumps or micro-pads 35 may be between 5 and 30 micrometers or between 10 and 25 micrometers.

(327) Alternatively, referring to FIG. 26, a fourth type of micro-bump or micro-pad 35 may be a thermal compression pad, including the adhesion layer 26a and seed layer 26b as mentioned above, and further including, as seen in any of FIGS. 28A, 29A, 35A and 36A, a copper layer 48 having a thickness t2 between 1 nm and 20 nm or between 2 nm and 10 nm and a largest transverse dimension w2, such as diameter in a circular shape, between 5 nm and 50 nm, on its seed layer 26b and a solder cap 49 made of a tin-silver alloy, a tin-gold alloy, a tin-copper alloy, a tin-indium alloy, indium, tin or gold, which has a thickness between 0.1 nm and 5 nm on its copper layer 48. A pitch between neighboring two of the fourth type of micro-bumps or micro-pads 35 may be between 5 and 30 micrometers or between 10 and 25 micrometers.

(328) Second Embodiment for Chip Package Based on Fan-Out Interconnection Scheme for Logic Drive or Device (FOISD)

(329) 1. First Type of Chip Package for Second Embodiment

(330) FIGS. 27A-27G are schematically cross-sectional views showing a process for forming a first type of multichip package in accordance with a second embodiment of the present application. FIGS. 28A and 28B are schematically cross-sectional views showing a process of bonding a thermal compression bump of a semiconductor integrated-circuit chip to a thermal compression pad of a fan-out interconnection scheme for a logic drive or device (FOISD) in accordance with an embodiment of the present application. FIGS. 29A and 29B are schematically cross-sectional views showing a process of bonding a thermal compression bump of a first type of vertical-through-via (VTV) connector to a thermal compression pad of a fan-out interconnection scheme for a logic drive or device (FOISD) in accordance with an embodiment of the present application.

(331) Referring to FIG. 27A, multiple semiconductor integrated-circuit (IC) chips 100, each of which may be (1) an application specific integrated-circuit (ASIC) logic chip, (2) a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip 200 as illustrated in FIG. 9 or dedicated programmable interconnection (DPI) integrated-circuit (IC) chip 410 as illustrated in FIG. 10, (3) a processing and/or computing integrated-circuit (IC) chip, such as graphic-processing-unit (GPU) integrated-circuit (IC) chip, central-processing-unit (CPU) integrated-circuit (IC) chip, tensor-processing-unit (TPU) integrated-circuit (IC) chip, network-processing-unit (NPU) integrated-circuit (IC) chip, application-processing-unit (APU) integrated-circuit (IC) chip, digital-signal-processing (DSP) integrated-circuit (IC) chip, (4) a memory integrated-circuit (IC) chip, such as non-volatile NAND chip, non-volatile NOR flash chip, non-volatile magnetoresistive random-access-memory (MRAM) integrated-circuit (IC) chip, non-volatile resistive random access memory (RRAM) integrated-circuit (IC) chip, non-volatile phase-change random-access-memory (PCM) integrated-circuit (IC) chip, non-volatile ferroelectric-random-access-memory (FRAM) integrated-circuit (IC) chip or high bandwidth dynamic random-access-memory (DRAM) or static random-access-memory (SRAM) memory (HBM) chip, (5) an auxiliary and supporting (AS) integrated-circuit (IC) chip 411 as illustrated in FIG. 11, (6) an IAC IC chip 402 as illustrated in FIG. 12A, (7) a dedicated I/O chip 265 or dedicated control and I/O chip 260 as illustrated in FIGS. 12A and 12B, or (8) a power management integrated-circuit (IC) chip, each may be provided with the first and/or second interconnection scheme(s) 560 and/or 588 and first, second or third type of micro-bumps or micro-pads 34 as illustrated in FIG. 14A or 14B. Each of the semiconductor integrated-circuit (IC) chips 100 may have the same specification as illustrated in FIG. 14A or 14B. Further, referring to FIG. 27A, multiple first type of operation units 190, each of which may have the same specification as illustrated in FIG. 17F, 17G, 19G or 19H, each may be provided with the first, second or third type of micro-bumps or micro-pads 197. Further, multiple first type of vertical-through-via (VTV) connectors 467 each may have the same specification as illustrated in FIG. 1A, 1C, 1E, 2A, 2C or 2E, provided with the first, second or third type of micro-bumps or micro-pads 34, may have the same specification as illustrated in FIG. 4A, 4B, 4C, 5A, 5B or 5C, provided with the fifth type of micro-bumps or micro-pads 34, or may have the same specification as illustrated in FIG. 6, provided with the sixth type of micro-bumps or micro-pads 34. Further, a fan-out interconnection scheme for a logic drive or device (FOISD) 592, which may have the same specification as illustrated in FIG. 26, may be provided with the first, second or fourth type of micro-bumps or micro-pads 35.

(332) For a first case, referring to FIGS. 27A, 27B, 28A, 28B, 29A and 29B, each of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 may have the third type of micro-bumps or micro-pads 34 or 197 to be bonded to the fourth type of micro-bumps or micro-pads 35 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592. For example, the third type of micro-bumps or micro-pads 34 or 197 of said each of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 may have the solder caps 38 to be thermally compressed, at a temperature between 240 and 300 degrees Celsius, at a pressure between 0.3 and 3 Mpa and for a time period between 3 and 15 seconds, onto the metal caps 49 of the fourth type of micro-bumps or micro-pads 35 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592 into multiple bonded contacts 563 therebetween. Each of the third type of micro-bumps or micro-pads 34 or 197 of said each of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 may have the copper layer 37 having the thickness t3 greater than the thickness t2 of the copper layer 48 of each of the fourth type of micro-bumps or micro-pads 35 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592 and having the largest transverse dimension w3 equal to between 0.7 and 0.1 times of the largest transverse dimension w2 of the copper layer 48 of each of the fourth type of micro-bumps or micro-pads 35 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592. Alternatively, each of the third type of micro-bumps or micro-pads 34 or 197 of said each of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 may be provided with the copper layer 37 having a cross-sectional area equal to between 0.5 and 0.01 times of the cross-sectional area of the copper layer 48 of each of the fourth type of micro-bumps or micro-pads 35 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592. A bonded solder between the copper layers 37 and 48 of each of the bonded contacts 563 may be mostly kept on a top surface of the copper layer 48 of one of the fourth type of micro-bumps or micro-pads 35 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592 and extends out of the edge of the copper layer 48 of said one of the fourth type of micro-bumps or micro-pads 35 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592 less than 0.5 micrometers. Thus, a short between neighboring two of the bonded contacts 563 even in a fine-pitched fashion may be avoided.

(333) Referring to FIGS. 27A, 27B, 28A and 28B, for said each of the semiconductor integrated-circuit (IC) chips 100, its third type of micro-bumps or micro-pads 34 may be formed respectively on a front surface of the metal pads 6b provided by the frontmost one of the interconnection metal layers 27 of its second interconnection scheme 588 or by, if the second interconnection scheme 588 is not provided for said each of the semiconductor integrated-circuit (IC) chips 100, the frontmost one of the interconnection metal layers 6 of its first interconnection scheme 560, wherein each of its third type of micro-bumps or micro-pads 34 may be provided with the copper layer 37 having the thickness t3 greater than the thickness t1 of each of its metal pads 6b and having the largest transverse dimension w3 equal to between 0.7 and 0.1 times of the largest transverse dimension w1 of each of its metal pads 6b; alternatively, each of its third type of micro-bumps or micro-pads 34 may be provided with the copper layer 37 having a cross-sectional area equal to between 0.5 and 0.01 times of the cross-sectional area of each of its metal pads 6b; each of its metal pads 6b may have a thickness t1 between 1 and 10 micrometers or between 2 and 10 micrometers and a largest transverse dimension w1, such as diameter in a circular shape, between 1 μm and 25 μm.

(334) Alternatively, for a second case, referring to FIGS. 27A and 27B, each of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 may have the second type of micro-bumps or micro-pads 34 or 197 each having the solder cap 33 to be bonded to the copper layer 32 of one of the first type of micro-bumps or micro-pads 35 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592 into a bonded contact 563 therebetween. Each of the second type of micro-bumps or micro-pads 34 or 197 of said each of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 may have the copper layer 32 having a thickness greater than that of the copper layer 32 of each of the first type of micro-bumps or micro-pads 35 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592.

(335) Alternatively, for a third case, referring to FIGS. 27A and 27B, each of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 may have the first type of micro-bumps or micro-pads 34 or 197 each having the copper layer 32 to be bonded to the solder cap 33 of one of the second type of micro-bumps or micro-pads 35 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592 into a bonded contact 563 therebetween. Each of the first type of micro-bumps or micro-pads 34 or 197 of said each of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 may have the copper layer 32 having a thickness greater than that of the copper layer 32 of each of the second type of micro-bumps or micro-pads 35 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592.

(336) Alternatively, for a fourth case, referring to FIGS. 27A and 27B, each of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 may have the second type of micro-bumps or micro-pads 34 or 197 each having the solder cap 33 to be bonded to the solder cap 33 of one of the second type of micro-bumps or micro-pads 35 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592 into a bonded contact 563 therebetween. Each of the second type of micro-bumps or micro-pads 34 or 197 of said each of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 may have the copper layer 32 having a thickness greater than that of the copper layer 32 of each of the second type of micro-bumps or micro-pads 35 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592.

(337) Alternatively, for a fifth case, referring to FIGS. 27A and 27B, each of the first type of vertical-through-via (VTV) connectors 467 may be flipped with the fifth type of micro-bumps or micro-pads 34 each having the solder layer 719 to be bonded to the copper layer 32 of one of the first type of micro-bumps or micro-pads 35 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592 into a bonded contact 563 therebetween.

(338) Alternatively, for a sixth case, referring to FIGS. 27A and 27B, each of the first type of vertical-through-via (VTV) connectors 467 may be flipped with the fifth type of micro-bumps or micro-pads 34 each having the solder layer 719 to be bonded to the solder cap 33 of one of the second type of micro-bumps or micro-pads 35 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592 into a bonded contact 563 therebetween.

(339) Alternatively, for a seventh case, referring to FIGS. 27A and 27B, each of the first type of vertical-through-via (VTV) connectors 467 may be flipped with the sixth type of micro-bumps or micro-pads 34 each having the solder ball 321 to be bonded to the copper layer 32 of one of the first type of micro-bumps or micro-pads 35 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592 into a bonded contact 563 therebetween.

(340) Alternatively, for an eighth case, referring to FIGS. 27A and 27B, each of the first type of vertical-through-via (VTV) connectors 467 may be flipped with the sixth type of micro-bumps or micro-pads 34 each having the solder ball 321 to be bonded to the solder cap 33 of one of the second type of micro bumps or micro-pads 35 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592 into a bonded contact 563 therebetween.

(341) Next, referring to FIG. 27B, an underfill 564, such as a layer of polymer or epoxy resins or compounds, may be filled into a gap between each of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 and the fan-out interconnection scheme for a logic drive or device (FOISD) 592 to enclose the bonded contacts 563 therebetween. The underfill 564 may be cured at temperature equal to or above 100, 120 or 150 degrees Celsius.

(342) Next, referring to FIG. 27B, a polymer layer 92, e.g., resin or compound, may be applied to fill a gap between each neighboring two of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 and to cover a backside of each of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 by methods, for example, spin-on coating, screen-printing, dispensing or molding. The polymer layer 92 may have the same specification or material as that illustrated in FIG. 22B.

(343) Next, referring to FIG. 27C, a chemical mechanical polishing (CMP), polishing or grinding process may be applied to remove a top portion of the polymer layer 92, a top portion of each of the semiconductor integrated-circuit (IC) chips 100, a top portion of each of the first type of operation units 190 and a top portion of each of the first type of vertical-through-via (VTV) connectors 467 and to expose a backside of each of the vertical through vias (VTVs) 358 of each of the first type of vertical-through-via (VTV) connectors 467. For each of the vertical through vias (VTVs) 358 of said each of the first type of vertical-through-via (VTV) connectors 467, if made of one or more of the through silicon vias (TSVs) 157 as illustrated in one of FIGS. 1A, 1C, 1E, 2A, 2C and 2F, its insulating lining layer 153, adhesion layer 154 and seed layer 155 at its backside may be removed to expose a backside of its copper layer 156, which is coplanar with a backside of said each of the first type of vertical-through-via (VTV) connectors 467 and a top surface of the polymer layer 92, and its insulating lining layer 153, adhesion layer 154 and seed layer 155 at a sidewall of its copper layer 156 may be left. For each of the vertical through vias (VTVs) 358 of said each of the first type of vertical-through-via (VTV) connectors 467, if made of one or more of the through glass vias (TGVs) 259 as illustrated in one of FIGS. 4A, 4B, 4C, 5A, 5B and 5C, a backside of its copper post 706 may be exposed with being coplanar with a backside of said each of the first type of vertical-through-via (VTV) connectors 467 and the top surface of the polymer layer 92; for each of the vertical through vias (VTVs) 358 of said each of the first type of vertical-through-via (VTV) connectors 467, if made of one or more of the through polymer vias (TPVs) 318 as illustrated in FIG. 6 for the fifth alternative, a backside of its metal pad 336 or copper post 318 may be exposed with being coplanar with a backside of said each of the first type of vertical-through-via (VTV) connectors 467 and the top surface of the polymer layer 92.

(344) Next, referring to FIG. 27D, a backside interconnection scheme for a logic drive or device (BISD) 79 may be formed on the backside of each of the semiconductor integrated-circuit (IC) chips 100, the backside of each of the first type of operation units 190, the backside of each of the first type of vertical-through-via (VTV) connectors 467 and the top surface of the polymer layer 92. The backside interconnection scheme for a logic drive or device (BISD) 79 may include an insulating dielectric layer 93 on the backside of each of the semiconductor integrated-circuit (IC) chips 100, the backside of each of the first type of operation units 190, the backside of each of the first type of vertical-through-via (VTV) connectors 467 and the top surface of the polymer layer 92. Each opening in the insulating dielectric layer 93 may be vertically over the backside of one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467. For said one of the first type of vertical-through-via (VTV) connectors 467, if said one of its vertical through vias (VTVs) 358 is made of one or more of the through silicon vias (TSVs) 157 as illustrated in one of FIGS. 1A, 1C, 1E, 2A, 2C and 2E, said each opening in the insulating dielectric layer 93 may be vertically over the backside of the copper layer 156 of said one or more of its through silicon vias (TSVs) 157. For said one of the first type of vertical-through-via (VTV) connectors 467, if said one of its vertical through vias (VTVs) 358 is made of one or more of the through glass vias (TGVs) 259 as illustrated in one of FIGS. 4A, 4B, 4C, 5A, 5B and 5C, said each opening in the insulating dielectric layer 93 may be vertically over the backside of the copper post 706 of said one or more of its through glass vias (TGVs) 259. For said one of the first type of vertical-through-via (VTV) connectors 467, if said one of its vertical through vias (VTVs) 358 is made of one of the through polymer vias (TPVs) as illustrated in FIG. 6, said each opening in the insulating dielectric layer 93 may be vertically over the backside of the metal pad 336 or copper post 318 of said one of its through polymer vias (TPVs). The backside interconnection scheme for a logic drive or device (BISD) 79 may further include an interconnection metal layer on a top surface of its insulating dielectric layer 93, coupling to each of the vertical through vias (VTVs) 358 of each of the first type of vertical-through-via (VTV) connectors 467 through one of the opening in its insulating dielectric layer 93. The interconnection metal layer of the backside interconnection scheme for a logic drive or device (BISD) 79 is patterned with multiple metal pads 583 each formed on the backside of one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467 or formed on the bottom surface of the insulating dielectric layer 93 and vertically under the backside of one of the semiconductor integrated-circuit (IC) chips 100, the backside of one of the first type of operation units 190, the backside of one of the first type of vertical-through-via (VTV) connectors 467 or the bottom surface of the polymer layer 92. The insulating dielectric layer 93 and metal pads 583 may have the same specification or material as those illustrated in FIG. 22G. Alternatively, a tin-containing solder bump made of tin or a tin-silver alloy having a thickness between 1 μm and 50 μm may be formed on each of the metal pads 583 as illustrated in FIG. 22G.

(345) Next, the temporary substrate (T-sub) 590 as seen in FIG. 27D may be released as illustrated in FIGS. 22E and 22E from the fan-out interconnection scheme for a logic drive or device (FOISD) 592 to expose a bottom surface of each metal via 27a of the bottommost one of the interconnection metal layers 27 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592 and a bottom surface of the bottommost one of the polymer layers 42 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592 as seen in FIG. 27E, wherein the bottom surface of each metal via 27a of the bottommost one of the interconnection metal layers 27 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592 may be coplanar with the bottom surface of the bottommost one of the polymer layers 42 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592.

(346) Next, referring to FIG. 27F, the structure as seen in FIG. 27E is flipped to form an insulating dielectric layer 585, such as polymer, on the top surface of the topmost one of the polymer layers 42 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592, wherein each opening in the insulating dielectric layer 585 may be vertically over and expose the top surface of one of the metal via 27a of the topmost one of the interconnection metal layers 27 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592 and then to form multiple metal bumps, pillars or pads 570 in an array on the metal vias 27a of the topmost one of the interconnection metal layers 27 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592 at bottoms of the respective openings in the insulating dielectric layer 585. The insulating dielectric layer 585 may be a layer of polymer, such as polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer or silicone, having a thickness between 3 and 30 micrometers or between 5 and 15 micrometers. Each of the metal bumps, pillars or pads 570 may be of one of the first through third types having the same specifications as the first through third types of metal bumps, pillars or pads 570 as illustrated in FIG. 22G respectively, wherein each of the metal bumps or pillars 570 may be of the first or second type, including the adhesion layer 26a, such as titanium (Ti) or titanium nitride (TiN) layer having a thickness between 1 nm and 50 nm, on one of the metal vias 27a of the topmost one of the interconnection metal layers 27 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592, or of the third type, including the gold layer, i.e., gold bump, having a thickness between 3 and 15 micrometers over one of the metal vias 27a of the topmost one of the interconnection metal layers 27 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592.

(347) Next, the insulating dielectric layer 585, the polymer layers 42 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592, the polymer layer 92 and the insulating dielectric layer 93 may be cut or diced to separate multiple individual chip packages 300 as shown in FIG. 27G each for the standard commodity logic drive as illustrated in FIG. 12A by a laser cutting process or by a mechanical cutting process. For the chip package 300 as seen in FIG. 27G, one or more of the interconnection metal layers 27 of its fan-out interconnection scheme for a logic drive or device (FOISD) 592 may couples each of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 to the other of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals to said each of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467. Each of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190 may couple to one of its metal pads 583 through, in sequence, one or more of the interconnection metal layers 27 of its fan-out interconnection scheme for a logic drive or device (FOISD) 592 and one of the vertical through vias (VTV) 358 of one of its first type of vertical-through-via (VTV) connectors 467 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals to said each of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190. Each of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 may couple to one or more of its metal bumps, pillars or pads 570 through each of the interconnection metal layers 27 of its fan-out interconnection scheme for a logic drive or device (FOISD) 592 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals to said each of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467. One of its metal bumps, pillars or pads 570 vertically over each of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190 may couple to one of its metal pads 583 vertically under said each of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190 through, in sequence, each of the interconnection metal layers 27 of its fan-out interconnection scheme for a logic drive or device (FOISD) 592, one of the vertical through vias (VTVs) 358 of one of its first type of vertical-through-via (VTV) connectors 467 and the interconnection metal layer of its backside interconnection scheme for a logic drive or device (BISD) 79 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals. Each of its metal bumps, pillars or pads 570 having a number of more than 20 may be vertically aligned with one of its metal pads 583 having a number of more than 20. Alternatively, each of its metal bumps, pillars or pads 570 having a number of more than 50 may be vertically aligned with one of its metal pads 583 having a number of more than 50. Each of the vertical through vias (VTVs) 358 of each of its first type of vertical-through-via (VTV) connectors 467 may have a depth, for example, between 30 μm and 2,000 μm.

(348) For the chip package 300 as seen in FIG. 27G, its metal pads 583 arranged in an array may include multiple dummy pads 583a each not connecting to any of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190 but having mechanical functions for subsequent package-on-package (POP) assembly, formed on the bottom surface of its insulating dielectric layer 93 and vertically under one of its semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and polymer layer 92. Each of its dummy pads 583a may have no connection to any of the vertical through vias (VTVs) 358 of any of its first type of vertical-through-via (VTV) connectors 467.

(349) Alternatively, FIG. 27H is a schematically cross-sectional view showing a second type of single-chip/unit package in accordance with a first embodiment of the present application. The chip package 300 as seen in FIG. 27H may have a similar structure to that as illustrated in FIG. 27G. For an element indicated by the same reference number shown in FIGS. 27G and 27H, the specification of the element as seen in FIG. 27H may be referred to that of the element as illustrated in FIG. 27G. The difference between the chip packages as illustrated in FIGS. 27G and 27H is that the chip package as seen in FIG. 27H includes only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190 having the same specification as illustrated in FIG. 27A and one or more first type of vertical-through-via (VTV) connectors 467 having the same specification as illustrated in FIG. 27A. For the single-chip/unit package 300 as seen in FIG. 27H, its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190 may couple to one of its metal pads 583 through, in sequence, one or more of the interconnection metal layers 27 of its fan-out interconnection scheme for a logic drive or device (FOISD) 592 and one of the vertical through vias (VTVs) 358 of one of its first type of vertical-through-via (VTV) connectors 467 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals to its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190. Each of its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190 and its first type of vertical-through-via (VTV) connectors 467 may couple to one or more of its metal bumps, pillars or pads 570 through each of the interconnection metal layers 27 of its fan-out interconnection scheme for a logic drive or device (FOISD) 592 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals to its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190. One of its metal bumps, pillars or pads 570 vertically over its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190 may couple to one of its metal pads 583 vertically under its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190 through, in sequence, each of the interconnection metal layers 27 of its fan-out interconnection scheme for a logic drive or device (FOISD) 592, one of the vertical through vias (VTVs) 358 of one of its first type of vertical-through-via (VTV) connectors 467 and the interconnection metal layer of its backside interconnection scheme for a logic drive or device (BISD) 79 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals to its only one semiconductor integrated-circuit (IC) chip 100 or first type of operation unit 190. Each of its metal bumps, pillars or pads 570 having a number of more than 20 may be vertically aligned with one of its metal pads 583 having a number of more than 20. Alternatively, each of its metal bumps, pillars or pads 570 having a number of more than 50 may be vertically aligned with one of its metal pads 583 having a number of more than 50. For example, its more than twenty first metal contacts, i.e., metal bumps, pillars or pads 570, may be vertically over its only one semiconductor integrated-circuit (IC) chip 100 and its more than twenty second metal contacts, i.e., metal pads 583, may be vertically under its only one semiconductor integrated-circuit (IC) chip 100. Each of the vertical through vias (VTVs) 358 of each of its first type of vertical-through-via (VTV) connector(s) 467 may have a depth, for example, between 30 μm and 2,000 μm.

(350) 2. Second Type of Chip Package for Second Embodiment

(351) FIGS. 30A-30C are schematically cross-sectional views showing a process for forming a second type of multichip package in accordance with a second embodiment of the present application. After the structure as seen in FIG. 27E is formed, the backside interconnection scheme for a logic drive or device (BISD) 79 as illustrated in FIG. 23A may be formed over the backside of each of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467 and on the top surface of the polymer layer 92. The backside interconnection scheme for a logic drive or device (BISD) 79 may include one or more interconnection metal layers 27 coupling to each of the vertical through vias (VTVs) 358 of each of the first type of vertical-through-via (VTV) connectors 467 and one or more polymer layers 42, i.e., insulating dielectric layers, each between neighboring two of its interconnection metal layers 27, under the bottommost one of its interconnection metal layers 27 or over the topmost one of its interconnection metal layers 27, wherein an upper one of its interconnection metal layers 27 may couple to a lower one of its interconnection metal layers 27 through an opening in one of its polymer layers 42 between the upper and lower ones of its interconnection metal layers 27. The bottommost one of its polymer layers 42 may be between the bottommost one of its interconnection metal layers 27 and the backside of each of the semiconductor integrated-circuit (IC) chips 100, between the bottommost one of its interconnection metal layers 27 and the backside of each of the first type of operation units 190, between the bottommost one of its interconnection metal layers 27 and the backside of each of the first type of vertical-through-via (VTV) connectors 467 and between the bottommost one of its interconnection metal layers 27 and the top surface of the polymer layer 92, wherein each opening in the bottommost one of its polymer layers 42 may be vertically over the backside of one of the vertical through vias (VTVs) 358 of one of the first type of vertical-through-via (VTV) connectors 467. For the backside interconnection scheme for a logic drive or device (BISD) 79, each of its interconnection metal layers 27 may extend horizontally across an edge of each of the semiconductor integrated-circuit (IC) chips 100, first type of operation units 190 and first type of vertical-through-via (VTV) connectors 467. The topmost one of its interconnection metal layers 27 may be patterned with multiple metal pads 583 aligned with multiple respective openings in the topmost one of its polymer layers 42.

(352) Referring to FIG. 30A, for the backside interconnection scheme for a logic drive or device (BISD) 79, each of its polymer layers 42 may be a layer of polyimide, BenzoCycloButene (BCB), parylene, polybenzoxazole (PBO), epoxy-based material or compound, photo epoxy SU-8, elastomer or silicone, having a thickness between, for example, 0.3 μm and 50 μm, 0.3 μm and 30 μm, 0.5 μm and 20 μm and 10 or 0.5 μm and 5 or thicker than or equal to 0.3 μm, 0.5 μm, 0.7 μm, 1 μm, 1.5 μm, 2 μm, 3 μm or 5 Each of its interconnection metal layers 27 may be provided with multiple metal traces or lines each including (1) a copper layer 40 having one or more lower portions in openings in one of its polymer layers 42 having a thickness between 0.3 μm and 20 and an upper portion having a thickness 0.3 μm and 20 μm on said one of its polymer layers 42, (2) an adhesion layer 28a, such as titanium or titanium nitride having a thickness between 1 nm and 50 nm, at a bottom and sidewall of each of the one or more lower portions of the copper layer 40 of said each of the metal traces or lines and at a bottom of the upper portion of the copper layer 40 of said each of the metal traces or lines, and (3) a seed layer 28b, such as copper, between the copper layer 40 and adhesion layer 28a of said each of the metal traces or lines, wherein the upper portion of the copper layer 40 of said each of the metal traces or lines may have a sidewall not covered by the adhesion layer 28a of said each of the metal traces or lines. Each of its interconnection metal layers 27 may provide multiple metal lines or traces with a thickness between, for example, 0.3 μm and 40 μm, 0.5 μm and 30 μm, 1 μm and 20 μm and 15 μm and 10 or 0.5 μm to 5 or thicker than or equal to 0.3 μm, 0.7 μm, 2 μm, 3 μm, 5 μm, 7 μm or 10 and a width between, for example, 0.3 μm and 40 μm, 0.5 μm and 30 μm, 1 μm and 20 μm and 15 μm and 10 or 0.5 μm to 5 or wider than or equal to 0.3 μm, 0.7 μm, 2 μm, 3 μm, 5 μm, 7 μm or 10 Each of its interconnection metal layers 27 may have two planes used respectively for power and ground planes of a power supply and/or used as a heat dissipater or spreader for the heat dissipation or spreading, wherein each of the two planes may have a thickness, for example, between 5 μm and 50 μm, 5 μm and 30 μm, 5 μm and 20 μm, or 5 μm and 15 μm; or thicker than or equal to 5 μm, 10 μm, 20 μm, or 30 μm. The two planes may be layout as interlaced or interleaved shaped structures in a plane or may be layout in a fork shape.

(353) Referring to FIG. 30A, each of the metal pads 583 may be of various types. A first type of metal pad 583 may include (1) an adhesion layer 28a, such as titanium (Ti) or titanium nitride (TiN) layer having a thickness between 1 nm and 50 nm, on a top surface of a second topmost one of the polymer layers 42 of the backside interconnection scheme for a logic drive or device (BISD) 79, (2) a seed layer 28b, such as copper, on a top surface of its adhesion layer 28a, and (3) a copper layer 40, i.e., copper pad, having a thickness between 0.3 μm and 20 μm on a top surface of its seed layer 28b and at a bottom of one of the openings in the topmost one of its polymer layers 42. Alternatively, a second type of metal pad 583 may include the adhesion layer 28a, seed layer 28b and copper layer 40 as mentioned above, and may further include a nickel layer, i.e., nickel pad, having a thickness between 0.5 μm and 10 μm on a top surface of its copper layer 32 and in one of the openings in the topmost one of its polymer layers 42. Alternatively, a tin-containing solder bump made of tin or a tin-silver alloy having a thickness between 1 μm and 50 μm may be formed on the top surface of the copper layer 32 of each of the first type of metal pads 583 or a top surface of the nickel layer of each of the second type of metal pads 583.

(354) Next, the structure as seen in FIG. 30A may be flipped as seen in FIG. 30B to form the insulating dielectric layer 585 and the metal bumps, pillars or pads 570. Referring to FIG. 30B, the step for forming the insulating dielectric layer 585 and the metal bumps, pillars or pads 570 may have the same specifications as that illustrated in FIG. 27F. For an element indicated by the same reference number shown in FIGS. 27F and 30B, the specification of the element as seen in FIG. 30B may be referred to that of the element as illustrated in FIG. 27F.

(355) Next, the insulating dielectric layer 585, the polymer layers 42 of the fan-out interconnection scheme for a logic drive or device (FOISD) 592, the polymer layer 92 and the polymer layers 42 of the backside interconnection scheme for a logic drive or device (BISD) 79 may be cut or diced to separate multiple individual chip packages 300 as shown in FIG. 30C each for the standard commodity logic drive as illustrated in FIG. 12A by a laser cutting process or by a mechanical cutting process. For the chip package 300 as seen in FIG. 30C, each of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190 may couple to one of its metal pads 583 through, in sequence, one or more of the interconnection metal layers 27 of its fan-out interconnection scheme for a logic drive or device (FOISD) 592, one of the vertical through vias (VTVs) 358 of one of its first type of vertical-through-via (VTV) connectors 467 and each of the interconnection metal layer 27 of its backside interconnection scheme for a logic drive or device (BISD) 79 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals to said each of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190. One of its metal bumps, pillars or pads 570 vertically over each of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190 may couple to one of its metal pads 583 vertically under said each of its semiconductor integrated-circuit (IC) chips 100 and first type of operation units 190 through, in sequence, each of the interconnection metal layers 27 of its fan-out interconnection scheme for a logic drive or device (FOISD) 592, one of the vertical through vias (VTVs) 358 of one of its first type of vertical-through-via (VTV) connectors 467 and each of the interconnection metal layers 27 of its backside interconnection scheme for a logic drive or device (BISD) 79 for delivery of a voltage of power supply (Vcc), a voltage of ground reference (Vss), clock signals (CLK) or other signals. Each of its metal bumps, pillars or pads 570 having a number of more than 20 may be vertically aligned with one of its metal pads 583 having a number of more than 20. Alternatively, each of its metal bumps, pillars or pads 570 having a number of more than 50 may be vertically aligned with one of its metal pads 583 having a number of more than 50. Each of the vertical through vias (VTVs) 358 of each of its first type of vertical-through-via (VTV) connectors 467 may have a depth, for example, between 30 μm and 2,000 μm.