SiC JUNCTION FIELD EFFECT TRANSISTOR AND SiC COMPLEMENTARY JUNCTION FIELD EFFECT TRANSISTOR

Abstract

A SiC junction field effect transistor includes a SiC substrate, a first conductivity type channel region formed in the principal surface of the SiC substrate, a second conductivity type embedded gate region formed below the channel region on the principal surface side in the SiC substrate, and first conductivity type source region and drain region formed with the channel region interposed therebetween in the principal surface of the SiC substrate.

Claims

1. A SiC junction field effect transistor comprising: a SiC substrate; a first conductivity type channel region formed in a principal surface of the SiC substrate; a second conductivity type embedded gate region formed below the channel region on a principal surface side in the SiC substrate; and first conductivity type source region and drain region formed with the channel region interposed therebetween in the principal surface of the SiC substrate.

2. The SiC junction field effect transistor of claim 1, wherein an impurity density of the channel region is set lower than an impurity density of the embedded gate region.

3. The SiC junction field effect transistor of claim 1, wherein all the channel region, the embedded gate region, the source region, and the drain region are formed of ion-implanted layers.

4. The SiC junction field effect transistor of claim 1, further comprising: a second conductivity type gate contact region at a position apart from the source region and the drain region in the principal surface of the SiC substrate, wherein the embedded gate region extends to immediately below the gate contact region, and is connected to the gate contact region.

5. A SiC complementary junction field effect transistor comprising: a normally-off n-channel junction field effect transistor and a normally-off p-channel junction field effect transistor in a SiC substrate, wherein each of the n-channel junction field effect transistor and the p-channel junction field effect transistor is the SiC junction field effect transistor of claim 1, and the n-channel junction field effect transistor and the p-channel junction field effect transistor are formed apart from each other with electrically insulated from each other in the SiC substrate.

6. A SiC junction field effect transistor comprising: a SiC substrate; a first conductivity type embedded channel region formed apart downward from a principal surface of the SiC substrate; a second conductivity type embedded gate region formed below the embedded channel region; and first conductivity type source region and drain region formed with the embedded channel region interposed therebetween in the principal surface of the SiC substrate.

7. The SiC junction field effect transistor of claim 6, wherein an impurity density of the embedded channel region is set lower than an impurity density of the embedded gate region.

8. The SiC junction field effect transistor of claim 6, wherein all the embedded channel region, the embedded gate region, the source region, and the drain region are formed of ion-implanted layers.

9. The SiC junction field effect transistor of claim 6, further comprising: a second conductivity type gate contact region at a position apart from the source region and the drain region in the principal surface of the SiC substrate, wherein the embedded gate region extends to immediately below the gate contact region, and is connected to the gate contact region.

10. The SiC junction field effect transistor of claim 6, further comprising: a second conductivity type surface gate region above the embedded channel region at a position facing the embedded gate region in the principal surface of the SiC substrate.

11. A SiC complementary junction field effect transistor comprising: a normally-off n-channel junction field effect transistor and a normally-off p-channel junction field effect transistor in a SiC substrate, wherein each of the n-channel junction field effect transistor and the p-channel junction field effect transistor is the SiC junction field effect transistor of claim 6, and the n-channel junction field effect transistor and the p-channel junction field effect transistor are formed apart from each other with electrically insulated from each other in the SiC substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG. 1A shows a schematic plan view of the configuration of a SiC JFET in a first embodiment of the present invention.

[0015] FIG. 1B shows a sectional view taken along IB-IB line in FIG. 1A.

[0016] FIG. 1C shows a sectional view taken along IC-IC line in FIG. 1A.

[0017] FIG. 2A shows graphs obtained by simulation and showing the profile of an impurity density in a depth direction from a channel region surface when a channel region and an embedded gate region are formed by ion implantation in an n-channel JFET in the present embodiment.

[0018] FIG. 2B shows graphs of measurement results, which are obtained using SIMS, of the profile of the impurity density when the channel region and the embedded gate region are formed under ion implantation conditions set as shown in FIG. 2A.

[0019] FIG. 3A shows graphs of measurement results of drain current-drain voltage characteristics of an n-channel SiC JFET.

[0020] FIG. 3B shows graphs of measurement results of drain current-drain voltage characteristics of a p-channel SiC JFET.

[0021] FIG. 4 shows a circuit diagram in a case where an inverter circuit is formed using a SiC complementary JFET which is formed using the SiC JFET.

[0022] FIG. 5 shows a schematic sectional view of the structure of the SiC complementary JFET forming the inverter circuit.

[0023] FIG. 6A shows a schematic sectional view of a modification of the SiC complementary JFET forming the inverter circuit.

[0024] FIG. 6B shows a sectional view taken along VIB-VIB line in FIG. 6A.

[0025] FIG. 7A shows a schematic plan view of the configuration of a SiC JFET in a second embodiment of the present invention.

[0026] FIG. 7B shows a sectional view taken along VIIB-VIIB line in FIG. 7A.

[0027] FIG. 7C shows a sectional view taken along VIIC-VIIC line in FIG. 7A.

[0028] FIG. 8 shows a schematic sectional view of the structure of a SiC complementary JFET forming an inverter circuit.

[0029] FIG. 9A shows a schematic sectional view of another configuration of the SiC complementary JFET forming the inverter circuit.

[0030] FIG. 9B shows a sectional view taken along IXB-IXB line in FIG. 9A.

[0031] FIG. 10A shows a schematic plan view of the configuration of a SiC JFET in a modification of the second embodiment.

[0032] FIG. 10B shows a sectional view taken along XB-XB line in FIG. 10A.

[0033] FIG. 10C shows a sectional view taken along XC-XC line in FIG. 10A.

[0034] FIG. 11 shows a schematic sectional view of the configuration of a SiC JFET of another modification.

[0035] FIG. 12 shows a sectional view of the structure of a SiC JFET disclosed in a specification previously filed by the applicant(s) of the present application.

[0036] FIG. 13A shows graphs obtained by simulation and showing the profile of an impurity density in a depth direction from a gate region surface when an embedded channel region and a gate region are formed by ion implantation in an n-channel JFET shown in FIG. 12.

[0037] FIG. 13B shows graphs of measurement results, which are obtained using SIMS, of the profile of the impurity density when the embedded channel region and the gate region are formed under ion implantation conditions set as shown in FIG. 13A.

DETAILED DESCRIPTION

[0038] The applicant(s) of the present application has disclosed, in the specification of the previously-filed application (Japanese Unexamined Patent Publication No. 2017-212397), the structure of a SiC JFET operating in a normally-off state over a broad gate voltage range. FIG. 12 shows a sectional view of an example of the structure of the SiC JFET disclosed in such a specification. Here, an n-channel JFET will be described, but a p-channel JFET also has a similar structure.

[0039] As shown in FIG. 12, the SiC JFET disclosed in the specification above includes an n-type embedded channel region 111 formed on a principal surface side in a SiC substrate 110, a p.sup.+-type gate region 114 formed above the embedded channel region 111, and n.sup.+-type source region 112 and drain region 113 formed with the gate region 114 interposed therebetween.

[0040] In the case of an n-channel SiC JFET, the threshold voltage V.sub.th of the SiC JFET having the configured described above can be expressed using a model for analyzing a depletion layer at a semiconductor pn junction by Expression (1) below. Note that the threshold voltage V.sub.th of a p-channel SiC JFET can also be expressed by a similar expression.

[00001]$\begin{array}{cc}{V}_{\mathrm{th}}=\frac{\mathrm{kT}}{q}\ln \left(\frac{\mathrm{np}}{n_i^2}\right)-\frac{{\mathrm{qNa}}^2}{2{}_s}& \left(1\right)\end{array}$

[0041] where k is a Boltzmann constant, n is the electron density of the embedded channel region 111, p is the hole density of the gate region 114, n.sub.i is an intrinsic carrier density, q is an electron charge, .sub.s is the dielectric constant of SiC, N is the impurity density of the embedded channel region 111, and a is the thickness of the embedded channel region 111 immediately below the gate region 114.

[0042] As shown in Expression (1), the threshold voltage V.sub.th of the SiC JFET can be controlled by adjustment of the impurity density N and thickness a of the embedded channel region 111 immediately below the gate region 114. Moreover, the impurity density N and thickness a of the embedded channel region 111 are set to predetermined values such that the threshold voltage V.sub.th becomes a positive value, and in this manner, a normally-off SiC JFET can be provided.

[0043] A SiC complementary JFET including the normally-off n-channel SiC JFET and p-channel SiC JFET can be easily manufactured in such a manner that the embedded channel region 111, gate region 114, source region 112, and drain region 113 having different conductivity types are formed in the same SiC substrate 110 by ion implantation.

[0044] FIG. 13A shows graphs obtained by simulation and showing the profile of the impurity density in a depth direction from the surface of the gate region 114 when the n-type embedded channel region 111 and the p.sup.+-type gate region 114 are formed by the ion implantation in the n-channel JFET. Here, the graph indicated by an arrow A shows the profile of the embedded channel region 111, and the graph indicated by an arrow B shows the profile of the gate region 114. In FIG. 13A, a region indicated by an arrow P indicates the embedded channel region 111. Note that simulation software Stopping and Range in Matter (SRIM) for calculating the distribution of implanted ions by a Monte Carlo method was used for the simulation.

[0045] In order to obtain a target threshold voltage V.sub.th, ion implantation conditions (dose amount and acceleration energy) were set such that the impurity density N and thickness a of the embedded channel region 111 are the predetermined values. Here, phosphorus (P) was used as an impurity for the n-type embedded channel region 111, and aluminum (Al) was used as an impurity for the p.sup.+-type gate region 114.

[0046] In the ion implantation, in a case where a dopant such as P or Al is implanted as an ion beam along a particular crystal direction of the SiC substrate, a channeling phenomenon occurs, in which an implanted atom reaches a deeper position as compared to a case where the dopant is not along the crystal direction. This channeling phenomenon influences the profile of the impurity density.

[0047] A method for reducing the influence of the channeling phenomenon includes a method in which the angle of the ion implantation to the SiC substrate is slightly inclined. However, even if such a method is employed, it is difficult for more implanted atoms to reach a position deeper than the peak of the profile of the impurity density.

[0048] FIG. 13B shows graphs of measurement results, which were obtained using secondary ion mass spectrometry (SIMS), of the profile of the impurity density when the embedded channel region 111 and the gate region 114 are formed under the ion implantation conditions set as shown in FIG. 13A. Here, the graph indicated by an arrow A shows the profile of the embedded channel region 111, and the graph indicated by an arrow B shows the profile of the gate region 114. In FIG. 13B, a region indicated by an arrow P indicates the embedded channel region 111.

[0049] As shown in FIG. 13B, the embedded channel region 111 and the gate region 114 are formed so as to expand their ranges to positions deeper than their peaks. Thus, the impurity in such an expanded portion of the high-density gate region 114 enters the low-density embedded channel region 111, and for this reason, the impurity density N of the embedded channel region 111 greatly decreases as compared to a design value while the thickness a of the embedded channel region 111 greatly increases as compared to a design value.

[0050] As described above, actual impurity density N and thickness a of the embedded channel region 111 greatly deviate from the design values, and for this reason, when the structure of the SiC JFET is designed, it is difficult to control the threshold voltage V.sub.th of the SiC JFET as designed.

[0051] The inventor(s) et al. of the present application have devised a structure having no influence of the channeling phenomenon on the profile of the impurity density of the embedded channel region 111 even when the embedded channel region 111 and the gate region 114 are formed by the ion implantation, and have arrived at the present invention.

[0052] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments below. Moreover, changes can be made as necessary without departing from a scope in which the effects of the present invention are produced.

First Embodiment

[0053] FIGS. 1A to 1C show schematic views of the configuration of a SiC JFET in a first embodiment of the present invention, FIG. 1A showing a plan view, FIG. 1B showing a sectional view taken along IB-IB line in FIG. 1A, and FIG. 1C showing a sectional view taken along IC-IC line in FIG. 1A. Here, an n-channel SiC JFET will be described.

[0054] As shown in FIGS. 1A to 1C, the SiC JFET in the present embodiment includes a semi-insulating SiC substrate 10, an n-type (first conductivity type) channel region 11 formed in a principal surface of the semi-insulating SiC substrate 10, a P.sup.+-type (second conductivity type) embedded gate region 14 formed below the channel region 11 on the principal surface side in the semi-insulating SiC substrate 10, and n.sup.+-type (first conductivity type) source region 12 and drain region 13 formed with the channel region 11 interposed therebetween in the principal surface of the semi-insulating SiC substrate 10. Note that in the present embodiment, the principal surface indicates a widest one of surfaces forming the semi-insulating SiC substrate 10.

[0055] Here, the impurity density of the channel region 11 is set lower than the impurity density of the embedded gate region 14. Moreover, all the channel region 11, the embedded gate region 14, the source region 12, and the drain region 13 are formed of ion-implanted layers.

[0056] As shown in FIGS. 1A and 1C, a p.sup.+-type (second conductivity type) gate contact region 15 is formed at a position apart from the source region 12 and the drain region 13 in the principal surface of the semi-insulating SiC substrate 10, and the embedded gate region 14 extends to immediately below the gate contact region 15 and is connected to the gate contact region 15.

[0057] Note that in the n-channel SiC JFET shown in FIGS. 1A to 1C, the semi-insulating SiC substrate 10 is used as a SiC substrate 10, but a SiC substrate 10 having a p-type epitaxial layer on a surface may be used. In this case, the channel region 11, the embedded gate region 14, the source region 12, and the drain region 13 are formed in the p-type epitaxial layer.

[0058] Note that a p-channel SiC JFET can be formed in such a manner that the channel region 11 is changed to a p-type, the embedded gate region 14 is changed to an n.sup.+-type, the source region 12 and the drain region 13 are changed to a p.sup.+-type, and the gate contact region 15 is changed to an n.sup.+-type.

[0059] In the case of the n-channel SiC JFET, the threshold voltage V.sub.th of the SiC JFET in the present embodiment can be expressed by Expression (2) below when the impurity density of the channel region 11 is N.sub.D, the impurity density of the embedded gate region 14 is N.sub.A, and the thickness of the channel region 11 is a:

[00002]$\begin{array}{cc}{V}_{\mathrm{th}}=\frac{\mathrm{kT}}{q}\ln \left(\frac{\mathrm{np}}{n_i^2}\right)-\frac{{\mathrm{qN}}_D{a}^2}{2{}_s}\frac{N_D+N_A}{N_A}& \left(2\right)\end{array}$

[0060] where k is a Boltzmann constant, n is the electron density of the channel region 11, p is the hole density of the embedded gate region 14, n.sub.i is an intrinsic carrier density, q is an electron charge, and .sub.s is the dielectric constant of SiC. Note that the threshold voltage V.sub.th of the p-channel SiC JFET can also be expressed by a similar expression.

[0061] In the SiC JFET in the present embodiment, the P.sup.+-type embedded gate region 14 is formed below the n-type channel region 11. However, since the embedded gate region 14 is formed of the ion-implanted layer, the impurity density N.sub.D of the embedded gate region 14 is difficult to be a high density. For this reason, Expression (2) above is an expression in consideration of a case where a difference between the impurity density N.sub.D of the channel region 11 and the impurity density N.sub.A of the embedded gate region 14 is not so great, and in a case of N.sub.D<<N.sub.A, the threshold voltage Vth can be obtained using Expression (1) above.

[0062] As shown in Expression (2), the threshold voltage V.sub.th of the SiC JFET can be controlled by adjustment of the impurity density N.sub.D and thickness a of the channel region 11 and the impurity density N.sub.A of the embedded gate region 14. Moreover, the impurity density N.sub.D and thickness a of the channel region 11 and the impurity density N.sub.A of the embedded gate region 14 are set to predetermined values such that the threshold voltage V.sub.th becomes a positive value, and in this manner, a normally-off SiC JFET can be provided.

[0063] FIG. 2A shows graphs obtained by simulation and showing the profile of the impurity density in a depth direction from the surface of the channel region 11 when the n-type channel region 11 and the p.sup.+-type embedded gate region 14 are formed by ion implantation in the n-channel JFET. Here, the graph indicated by an arrow A shows the profile of the channel region 11, and the graph indicated by an arrow B shows the profile of the embedded gate region 14. In FIG. 2A, a region indicated by an arrow P indicates the channel region 11. Note that simulation software Stopping and Range in Matter (SRIM) for calculating the distribution of implanted ions by a Monte Carlo method was used for the simulation.

[0064] In order to obtain a target threshold voltage V.sub.th, ion implantation conditions (dose amount and acceleration energy) were set such that the impurity density N.sub.D and thickness a of the channel region 11 and the impurity density N.sub.A of the embedded gate region 14 are the predetermined values. Here, phosphorus (P) was used as an impurity for the n-type channel region 11, and aluminum (Al) was used as an impurity for the p.sup.+-type embedded gate region 14.

[0065] FIG. 2B shows graphs of measurement results, which were obtained using secondary ion mass spectrometry (SIMS), of the profile of the impurity density when the channel region 11 and the embedded gate region 14 are formed under the ion implantation conditions set as shown in FIG. 2A. Here, the graph indicated by an arrow A shows the profile of the channel region 11, and the graph indicated by an arrow B shows the profile of the embedded gate region 14. In FIG. 2B, a region indicated by an arrow P indicates the channel region 11.

[0066] As shown in FIG. 2B, the channel region 11 and the embedded gate region 14 are formed so as to expand their ranges to positions deeper than their peaks, but the profiles of the impurity densities of the channel region 11 and the embedded gate region 14 at positions shallower than their peaks are not changed much from the profiles shown in FIG. 2A. Thus, actual impurity density N.sub.D and thickness a of the channel region 11 and an actual impurity density N.sub.A of the embedded gate region 14 are substantially coincident with design values shown in FIG. 2A. Thus, when the structure of the SiC JFET is designed, the threshold voltage V.sub.th of the SiC JFET can be controlled as designed.

[0067] Note that FIGS. 2A and 2B show a case where the impurity density N.sub.D of the channel region 11 is set lower than the impurity density N.sub.A of the embedded gate region 14, but regardless of a magnitude relationship in the impurity density between these regions, the actual impurity density N.sub.D and thickness a of the channel region 11 and the actual impurity density N.sub.A of the embedded gate region 14 remain substantially coincident with the design values.

[0068] According to the present embodiment, the embedded gate region 14 is formed below the channel region 11 so that even in a case where the channel region 11 and the embedded gate region 14 are formed of the ion-implanted layers, the threshold voltage V.sub.th of the SiC JFET can be controlled as designed without influence of a channeling phenomenon. Thus, a SiC JFET stably operable at a high temperature can be provided. Moreover, since all the channel region 11, the embedded gate region 14, the source region 12, and the drain region 13 are formed of the ion-implanted layers, a complementary JFET can be easily produced in the same SiC substrate 10.

[0069] FIG. 3A shows graphs of measurement results of drain current-drain voltage characteristics when the n-channel SiC JFET having the configuration shown in FIGS. 1A to 1C is produced. Here, the measurement was conducted under a temperature of 300 K. Moreover, each ion-implanted layer was formed under the following conditions, and annealing after ion implantation was performed at 1650 C. Note that ion implantation was performed with an acceleration energy changed in multiple levels (multiple implantation). Moreover, the length of the channel region 11 was 50 m, and the width of the channel region 11 was 100 m.

Channel Region 11

[0070] Impurity: P, Total Dose Amount: 1.5710.sup.13 cm.sup.2, Acceleration Energy: 10-170 keV (multiple implantation)

Embedded Gate Region 14

[0071] Impurity: Al, Total Dose Amount: 2.3010.sup.13 cm.sup.2, Acceleration Energy: 450-520 keV (multiple implantation)

Source Region 12/Drain Region 13

[0072] Impurity: P, Total Dose Amount: 4.2310.sup.15 cm.sup.2, Acceleration Energy: 10-600 keV (multiple implantation)

[0073] In the n-channel SiC JFET produced under the above-described conditions, the impurity density of the channel region 11 was 510.sup.17 cm.sup.3, the impurity density of the embedded gate region 14 was 110.sup.18 cm.sup.3, and the thickness a of the channel region 11 was 281 nm.

[0074] As shown in FIG. 3A, the produced n-channel SiC JFET showed favorable drain current-drain voltage characteristics. Moreover, the threshold voltage V.sub.th had only a difference of 0.1 V from the design value (50.6 V).

[0075] FIG. 3B shows graphs of measurement results of drain current-drain voltage characteristics when the p-channel SiC JFET having the configuration shown in FIGS. 1A to 1C is produced. Here, the measurement was conducted under a temperature of 300 K. Moreover, each ion-implanted layer was formed by multiple implantation under the following conditions, and annealing after ion implantation was performed at 1650 C. The length of the channel region 11 was 50 m, and the width of the channel region 11 was 100 m.

Channel Region 11

[0076] Impurity: Al, Total Dose Amount: 1.610.sup.13 cm.sup.2, Acceleration Energy: 10-220keV (multiple implantation)

Embedded Gate Region 14

[0077] Impurity: P, Total Dose Amount: 210.sup.13 cm.sup.2, Acceleration Energy: 600-650 keV (multiple implantation)

Source Region 12/Drain Region 13

[0078] Impurity: Al, Total Dose Amount: 3.6710.sup.15 cm.sup.2, Acceleration Energy: 10-450 keV (multiple implantation)

[0079] In the p-channel SiC JFET produced under the above-described conditions, the impurity density of the channel region 11 was 510.sup.17 cm.sup.3, the impurity density of the embedded gate region 14 was 110.sup.18 cm.sup.3, and the thickness a of the channel region 11 was 281 nm.

SiC Complementary JFET

[0080] FIG. 4 shows a circuit diagram in an example where an inverter circuit is formed using a SiC complementary JFET which is formed using the SiC JFET in the present embodiment. Here, T.sub.r1 is a normally-off n-channel JFET, and T.sub.r2 is a normally-off p-channel JFET. The gate electrodes G of the n-channel JFET and the p-channel JFET are connected to the input terminal V.sub.in of the inverter circuit. Moreover, the drain electrodes D of the n-channel JFET and the p-channel JFET are connected to the output terminal V.sub.out of the inverter circuit. Further, the source electrode S of the n-channel JFET is connected to the ground, and the source electrode S of the p-channel JFET is connected to a power source (V.sub.DD).

[0081] FIG. 5 shows a schematic sectional view of the structure of the SiC complementary JFET forming this inverter circuit.

[0082] As shown in FIG. 5, a n-type channel region 11 is formed in an n-channel JFET (T.sub.r1) formation region of a semi-insulating SiC substrate 10, and a p-type channel region 11 is formed in a p-channel JFET (T.sub.r2) formation region of the semi-insulating SiC substrate 10. Moreover, a p.sup.+-type embedded gate region 14 is formed immediately below the n-type channel region 11, and n.sup.+-type source region 12 and drain region 13 are formed with the channel region 11 interposed therebetween. Further, an n.sup.+-type embedded gate region 14 is formed immediately below the p-type channel region 11, and p.sup.+-type source region 12 and drain region 13 are formed with the channel region 11 interposed therebetween.

[0083] In the present embodiment, since all the channel region 11, the embedded gate region 14, the source region 12, and the drain region 13 are formed by ion implantation, the complementary JFET can be easily produced in the same SiC substrate 10. Moreover, since the n-channel JFET and the p-channel JFET are formed apart from each other in the semi-insulating SiC substrate 10, the n-channel JFET and the p-channel JFET can be easily electrically separated from each other. In addition, the impurity density N.sub.D and thickness a of the channel region 11 can be set by adjustment of the acceleration energy and the dose amount in the ion implantation, and therefore, a normally-off JFET can be easily formed.

[0084] In the present embodiment, the semi-insulating SiC substrate 10 may have high resistance to such an extent that the n-channel JFET and the p-channel JFET can be electrically separated from each other. For example, a SiC substrate 10 having a resistivity p of 10.sup.9 cm or more can be used.

[0085] FIGS. 6A and 6B show schematic sectional views of a modification of the SiC complementary JFET formed using the SiC JFET in the present embodiment. Here, FIG. 6A is a plan view, and FIG. 6B is a sectional view taken along VIB-VIB line in FIG. 6A.

[0086] The SiC complementary JFET in the present modification is configured such that the n-channel JFET and p-channel JFET of the structure shown in FIGS. 1A to 1C are formed in a p.sup.-type low-concentration epitaxial layer 20 formed on the SiC substrate 10.

[0087] As shown in FIGS. 6A and 6B, in the SiC complementary JFET in the present modification, two n-type well regions 21 apart from each other are formed in the p.sup.-type low-concentration epitaxial layer 20. A p-type well region 22 is further formed in one of the well regions 21, and the n-channel JFET is formed in the p-type well region 22. Moreover, the p-type JFET is formed in the other well region 21. Thus, the n-channel JFET and the p-channel JFET can be electrically separated from each other in such a manner that a reverse bias is applied to a pn junction between the p.sup.-type low-concentration epitaxial layer 20 and the n-type well region 21.

[0088] Note that even in a case where an n.sup.-type low-concentration epitaxial layer is formed on the SiC substrate 10, a SiC complementary JFET having a similar configuration can be formed by changing the conductivity types of the well regions 21, 22.

Second Embodiment

[0089] FIGS. 7A to 7C show schematic views of the configuration of a SiC JFET in a second embodiment of the present invention, FIG. 7A showing a plan view, FIG. 7B showing a sectional view taken along VIIB-VIIB line in FIG. 7A, and FIG. 7C showing a sectional view taken along VIIC-VIIC line in FIG. 7A. Here, an n-channel SiC JFET will be described.

[0090] In the SiC JFET in the first embodiment, the n-type (first conductivity type) channel region 11 is formed in the principal surface of the semi-insulating SiC substrate 10 as shown in FIGS. 1A to 1C. However, in the SiC JFET in the present embodiment, an n-type (first conductivity type) embedded channel region 11 is formed at a position apart downward from the principal surface of a semi-insulating SiC substrate 10 as shown in FIGS. 7A to 7C.

[0091] Note that as in the first embodiment, in the present embodiment, a p.sup.+-type (second conductivity type) embedded gate region 14 is formed below the embedded channel region 11, and n.sup.+-type (first conductivity type) source region 12 and drain region 13 are formed with the embedded channel region 11 interposed therebetween in the principal surface of the semi-insulating SiC substrate 10.

[0092] Moreover, a p.sup.+-type (second conductivity type) gate contact region 15 is formed at a position apart from the source region 12 and the drain region 13 in the principal surface of the semi-insulating SiC substrate 10, and the embedded gate region 14 extends to immediately below the gate contact region 15 and is connected to the gate contact region 15.

[0093] In a case where the channel region 11 is formed in the principal surface of the SiC substrate 10, if there is a charge in the surface of the SiC substrate 10, a depletion layer in the channel region 11 may be unintentionally extended when a voltage is applied to the embedded gate region 14, and for this reason, a threshold voltage V.sub.th cannot be controlled as designed. In the present embodiment, since the embedded channel region 11 is formed at the position apart downward from the principal surface of the SiC substrate 10, variation in the threshold voltage V.sub.th due to influence of the charge in the surface of the SiC substrate 10 can be reduced.

[0094] Here, the depth of the embedded channel region 11 from the principal surface of the SiC substrate 10 may be determined as necessary according to the amount of charge in the surface of the SiC substrate 10. Typically, the embedded channel region 11 may be formed at a position 3 to 500 nm lower than the principal surface of the SiC substrate 10, more preferably 20 to 300 nm lower than the principal surface. If the embedded channel region 11 is formed at a position less than 3 nm lower than the principal surface of the SiC substrate 10, it is difficult to avoid the influence of the charge in the surface of the SiC substrate 10. If the embedded channel region 11 is formed at a position more than 500 nm lower than the principal surface of the SiC substrate 10, the embedded gate region 14 needs to be formed at a deeper position, which leads to an increase in an energy in ion implantation and a cost.

[0095] As in the first embodiment, in the present embodiment, the embedded gate region 14 is formed below the embedded channel region 11, and therefore, even if the embedded channel region 11 and the embedded gate region 14 are formed of ion-implanted layers, the threshold voltage V.sub.th of the SiC JFET can be controlled as designed without influence of a channeling phenomenon. Thus, a SiC JFET stably operable at a high temperature can be provided. Note that the impurity density of the embedded channel region 11 is preferably set lower than the impurity density of the embedded gate region 14.

[0096] All the embedded channel region 11, the embedded gate region 14, the source region 12, and the drain region 13 are preferably formed of the ion-implanted layers. With this configuration, a complementary JFET can be easily produced in the same SiC substrate 10.

[0097] The threshold voltage V.sub.th of the SiC JFET can be controlled by adjustment of the impurity density N.sub.D and thickness a of the embedded channel region 11 and the impurity density N.sub.A of the embedded gate region 14. Moreover, the impurity density N.sub.D and thickness a of the embedded channel region 11 and the impurity density N.sub.A of the embedded gate region 14 are set to predetermined values such that the threshold voltage V.sub.th becomes a positive value, and in this manner, a normally-off SiC JFET can be provided.

[0098] FIG. 8 shows a schematic sectional view of the structure of a SiC complementary JFET formed using the SiC JFET in the present embodiment and forming the inverter circuit shown in FIG. 4.

[0099] As shown in FIG. 8, an n-type embedded channel region 11 is formed in an n-channel JFET (T.sub.r1) formation region of a semi-insulating SiC substrate 10, and a p-type embedded channel region 11 is formed in a p-channel JFET (T.sub.r2) formation region of the semi-insulating SiC substrate 10. Moreover, a p.sup.+-type embedded gate region 14 is formed immediately below the n-type embedded channel region 11, and n.sup.+-type source region 12 and drain region 13 are formed with the embedded channel region 11 interposed therebetween. Further, an n.sup.+-type embedded gate region 14 is formed immediately below a p-type channel region 11, and p.sup.+-type source region 12 and drain region 13 are formed with the channel region 11 interposed therebetween.

[0100] In the present embodiment, since all the embedded channel region 11, the embedded gate region 14, the source region 12, and the drain region 13 are formed by ion implantation, the complementary JFET can be easily produced in the same SiC substrate 10. Moreover, since the n-channel JFET and the p-channel JFET are formed apart from each other in the semi-insulating SiC substrate 10, the n-channel JFET and the p-channel JFET can be easily electrically separated from each other. In addition, the impurity density N.sub.D and thickness a of the channel region 11 can be set by adjustment of an acceleration energy and a dose amount in the ion implantation, and therefore, a normally-off JFET can be easily formed.

[0101] In the present embodiment, the semi-insulating SiC substrate 10 may have high resistance to such an extent that the n-channel JFET and the p-channel JFET can be electrically separated from each other. For example, a SiC substrate 10 having a resistivity p of 10.sup.9 cm or more can be used.

[0102] FIGS. 9A and 9B show schematic sectional views of another configuration of the SiC complementary JFET in the present embodiment, and the n-channel JFET and the p-channel JFET are formed in a p.sup.-type low-concentration epitaxial layer 20 formed on the SiC substrate 10. Here, FIG. 9A is a plan view, and FIG. 9B is a sectional view taken along IXB-IXB line in FIG. 9A.

[0103] As shown in FIGS. 9A and 9B, two n-type well regions 21 apart from each other are formed in the p.sup.-type low-concentration epitaxial layer 20. A p-type well region 22 is further formed in one of the well regions 21, and the n-channel JFET is formed in the well region 22. Moreover, the p-type JFET is formed in the other well region 21. Thus, the n-channel JFET and the p-channel JFET can be electrically separated from each other in such a manner that a reverse bias is applied to a pn junction between the p.sup.-type low-concentration epitaxial layer 20 and the n-type well region 21.

[0104] Note that even in a case where an n.sup.-type low-concentration epitaxial layer is formed on the SiC substrate 10, a SiC complementary JFET having a similar configuration can be formed by changing the conductivity types of the well regions 21, 22.

Modification of Second Embodiment

[0105] FIGS. 10A to 10C show schematic views of a modification of the SiC JFET shown in FIGS. 7A to 7C, FIG. 10A showing a plan view, FIG. 10B showing a sectional view taken along XB-XB line in FIG. 10A, and FIG. 10C showing a sectional view taken along XC-XC line in FIG. 10A. Here, an n-channel SiC JFET will be described.

[0106] The SiC JFET in the present modification is configured such that in the SiC JFET shown in FIGS. 7A to 7C, a p-type (second conductivity type) surface gate region 16 is formed above the embedded channel region 11 at a position facing the p.sup.+-type embedded gate region 14 in the principal surface of the SiC substrate 10. That is, the SiC JFET in the present modification has a double gate structure in which the embedded channel region 11 is sandwiched by the paired embedded gate region 14 and surface gate region 16.

[0107] With this configuration, the depletion layer in the embedded channel region 11 is controlled by the paired embedded gate region 14 and surface gate region 16 formed on both sides of the embedded channel region 11, and therefore, as compared to the single gate structure shown in FIGS. 7A to 7C, a drain current can be increased about twice for the same threshold voltage V.sub.th. Thus, a SiC JFET having a high current drive capability can be provided.

[0108] Note that in the present modification, in order to apply a gate voltage to both the embedded gate region 14 and the surface gate region 16, the surface gate region 16 is preferably connected to the gate contact region 15 via, e.g., wiring. As shown in FIG. 11, in order to connect the surface gate region 16 to the gate contact region 15, the surface gate region 16 may be extended to the gate contact region 15 in the principal surface. Alternatively, the surface gate region 16 may be formed as a gate different from the embedded gate region 14 without connected to the gate contact region 15 via, e.g., wiring, and different gate voltages may be applied to the embedded gate region 14 and the surface gate region 16 to control the depletion layer in the embedded channel region 11.

[0109] Note that in the present modification, the impurity density of the surface gate region 16 is preferably set lower than the impurity density of the embedded gate region 14. Thus, even if the surface gate region 16 is formed of an ion-implanted layer, the threshold voltage V.sub.th of the SiC JFET can be controlled as designed with almost no influence of a channeling phenomenon on the embedded channel region 11.

[0110] The SiC complementary JFET having the structure shown in FIG. 8 or FIGS. 9A and 9B can be formed using the SiC JFET in the present modification.

[0111] The present invention has been described above with reference to the preferred embodiments, but the present invention is not limited to such description and various changes can be made thereto, needless to say.

[0112] For example, in the above-described embodiments, the example where the SiC complementary JFET is applied to the inverter circuit has been described, but the SiC complementary JFET may be applied to other integrated circuits, needless to say.

[0113] The structures of the SiC complementary JFETs shown in FIGS. 6A, 6B, 9A, and 9B can be applied to a SiC JFET alone.

[0114] The SiC JFETs in the above-described embodiments can be applied not only to the normally-off type but also a normally-on type, needless to say.

[0115] In the above-described embodiments, the example where the impurity density N.sub.D of the channel region 11 or the embedded channel region 11 is set lower than the impurity density N.sub.A of the embedded gate region 14 has been described, but both these regions may have a similar density.