METHOD FOR PRODUCING AN ADVANCED SUBSTRATE FOR HYBRID INTEGRATION

Abstract

A method of forming a substrate comprises providing a receiver substrate and a donor substrate successively comprising: a carrier substrate, a sacrificial layer, which can be selectively etched in relation to an active layer, and a silicon oxide layer, which is arranged on the active layer. A cavity is formed in the oxide layer to form a first portion that has a first thickness and a second portion that has a second thickness greater than the first thickness. The cavity is filled with a polycrystalline silicon filling layer to form a second free surface that is continuous and substantially planar. The receiver substrate and the donor substrate are assembled at the second free surface, and the carrier substrate is eliminated while preserving the active layer and the sacrificial layer.

Claims

1. A substrate, comprising: a receiver substrate; an active layer comprising single-crystal semiconductor material; and an electrically insulating silicon oxide layer interposed between the active layer and the receiver substrate; and a polycrystalline silicon layer on the receiver substrate, the polycrystalline silicon layer coated with the electrically insulating silicon oxide layer so as to define a first portion of the electrically insulating layer having a first thickness and interposed between the polycrystalline silicon layer and the active layer, and a second portion of the electrically insulating layer having a second thickness greater than the first thickness, the second portion being located between the receiver substrate and the active layer.

2. The substrate of claim 1, further comprising an additional layer comprising polycrystalline silicon, the additional layer interposed between the receiver substrate and an assembly formed by the electrically insulating layer and the polycrystalline silicon layer.

3. The substrate of claim 2, further comprising an additional electrically insulating layer interposed between the additional layer and the receiver substrate.

4. The substrate of claim 3, wherein the receiver substrate comprises an epitaxially grown and doped layer configured to form microelectronic components in the epitaxially grown layer.

5. The substrate of claim 4, wherein the receiver substrate comprises integrated circuits.

6. The substrate of claim 3, wherein the receiver substrate comprises integrated circuits.

7. The substrate of claim 1, wherein the active layer comprises silicon of silicon-germanium.

8. The substrate of claim 1, wherein a thickness of the active layer is between 5 nm and 500 nm.

9. The substrate of claim 8, wherein the thickness of the active layer is not uniform.

10. The substrate of claim 1, wherein each of the first thickness in the first portion of the electrically insulating layer and the second thickness in the second portion of the electrically insulating layer is between 10 nm and 500 nm.

11. The substrate of claim 1, wherein at least a portion of the polycrystalline silicon layer is configured to function as a trapping layer.

12. The substrate of claim 1, wherein at least a portion of the polycrystalline silicon layer is configured to function as a conductive layer.

13. The substrate of claim 1, wherein at least a first portion of the polycrystalline silicon layer is configured to function as a trapping layer, and at least a second portion of the polycrystalline layer is configured to function as a conductive layer.

14. The substrate of claim 1, further comprising at least one fully depleted silicon on insulator (FDSOI) device on the active layer over the first portion of the electrically insulating layer having the first thickness, and at least one radiofrequency (RF) device on the active layer over the second portion of the electrically insulating layer having the second thickness.

15. The substrate of claim 1, further comprising a sacrificial layer on the active layer, the sacrificial layer comprising a material capable of being selectively etched relative to the active layer.

16. The substrate of claim 1, wherein the active layer comprises an epitaxial layer.

17. A semiconductor substrate structure for hybrid integration, comprising: a substrate; at least one volume of polycrystalline material on the substrate; an electrically insulating layer disposed over the at least one volume of polycrystalline material and the substrate, such that the electrically insulating layer has a first portion having a first thickness and a second portion having a second thickness greater than the first thickness of the first portion; and an active layer disposed on the electrically insulating layer on a side thereof opposite the substrate, the active layer comprising a monocrystalline semiconductor material.

18. The substrate structure of claim 17, further comprising a sacrificial layer on the active layer, the sacrificial layer comprising a material capable of being selectively etched relative to the active layer.

19. The substrate structure of claim 17, wherein at least a first portion of the at least one volume of polycrystalline material is configured to function as a trapping layer, and at least a second portion of the at least one volume of polycrystalline material is configured to function as a conductive layer.

20. The substrate structure of claim 17, further comprising at least one fully depleted silicon on insulator (FDSOI) device on the active layer over the first portion of the electrically insulating layer having the first thickness, and at least one radiofrequency (RF) device on the active layer over the second portion of the electrically insulating layer having the second thickness.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Other features and advantages of the present disclosure will emerge from the detailed description that follows, with reference to the accompanying drawings in which:

[0053] FIGS. 1A to 1F, including 1D′ and 1F′, represent schematic sectional views illustrating steps of a process for producing an advanced substrate according to various embodiments; and

[0054] FIGS. 2 to 4 represent schematic sectional views of advanced substrates according to various embodiments.

[0055] To make the drawings clearer, the various layers have not necessarily been drawn to scale. Reference signs that are identical from one figure to the next have been used to reference elements that are identical or that perform the same function.

DETAILED DESCRIPTION

[0056] For the various embodiments, the same references will be used for elements that are identical, or which perform the same function, for the sake of simplifying the description.

[0057] FIGS. 1A to 1F schematically represent embodiments of a process according to the present disclosure. In order to facilitate the illustration, the respective thicknesses of the various layers are not shown to scale.

[0058] According to one embodiment, the process for producing an advanced substrate 1 comprises a step a) of providing a receiver substrate 20 (cf. FIGS. 1E, 1F and 1F′). The receiver substrate 20 may be made from a semiconductor material or from another material, depending on whether it must solely perform a mechanical carrier function or an electrical function within the final advanced substrate 1. Preferentially, the receiver substrate 20 is silicon based. Moreover, the receiver substrate 20 may comprise one or more functional additional layers, such as a trapping layer, termed “Trap Rich” layer, for example, based on polycrystalline silicon (optionally with a silicon oxide layer interposed between the receiver substrate 20 and the trapping layer), or else such as an epitaxially grown layer made from doped semiconductor material, etc.

[0059] As illustrated in FIG. 1A, this step also comprises a step of providing a donor substrate 10 comprising: [0060] A carrier substrate 11; [0061] An active layer 13 made from a single-crystal semiconductor material; and [0062] A sacrificial layer 12 made from a material that can be selectively etched with respect to the active layer, the sacrificial layer 12 being interposed between the carrier substrate 11 and the active layer 13; [0063] A silicon oxide layer 14 with a free surface 15 and arranged so that the active layer 13 is interposed between the sacrificial layer 12 and the oxide layer 14.

[0064] The carrier substrate 11 may be made from a semiconductor material or another material, given the expected crystal quality of the layers 12 and 13. Preferentially, the carrier substrate 11 is silicon based.

[0065] The active layer 13 is a layer configured to receive microelectronic components. In other words, the components will be formed in the active layer 13. Preferentially, the active layer 13 is made from single-crystal silicon, or from single-crystal silicon-germanium, which may be strained or relaxed.

[0066] According to one embodiment, the active layer 13 is advantageously formed by epitaxy. This is because a layer formed by epitaxy makes it possible to obtain a roughness, a uniformity of thickness and a surface finish of the layer that are optimal, in particular, compatible with the most demanding specifications of processes for producing microelectronic components, such as the process for producing components of FDSOI type.

[0067] Advantageously, the sacrificial layer 12 is also produced by epitaxy, in order to facilitate any epitaxy of the active layer 13. The sacrificial layer may be based on silicon and germanium, when the active layer is based on silicon or silicon-germanium. Moreover, the sacrificial layer 12 may also be based on any material that allows selective etching of the sacrificial layer 12 with respect to the active layer 13 as long as its crystal quality remains compatible with that required for the active layer 13.

[0068] Even more advantageously, the materials of the carrier substrate 11 and of the sacrificial layer 12 are configured so that the material of the carrier substrate 11 is selectively etched relative to the sacrificial layer 12 and so that the sacrificial layer 12 is selectively etched with respect to the active layer 13.

[0069] The oxide layer 14 can be produced by any technique known to those skilled in the art that is compatible with conventional processes in the microelectronics field. Preferentially, the oxide layer 14 is a usual thermal oxide.

[0070] The thickness of the carrier substrate 11 may be about a few hundred μm, typically 775 μm for substrates having a diameter of approximately 300 mm. The thickness of the sacrificial layer 12 depends on the etching solution and/or technique that are used. Those skilled in the art will know how to adjust its thickness so that it can be efficiently and selectively etched, with respect to the active layer 13. Advantageously, its thickness is also adjusted so that the material of the carrier substrate 11 can be selectively etched with respect to the sacrificial layer 12 while at the same time preserving the crystal properties of the active layer 13.

[0071] The thickness of the active layer 13 is preferentially between 5 and 500 nm, and the thickness of the oxide layer 14 is preferentially between 10 and 500 nm.

[0072] As illustrated in FIG. 1B, the process comprises a step b) of forming at least one cavity 30 in the silicon oxide layer 14. The cavity 30 is open, and comprises an opening flush with the free surface 15 of the oxide layer 14. The cavity 30 comprises walls. The walls of the cavity 30 and the opening of the cavity 30 delimit the volume of the cavity 30. Advantageously, the cavity 30 is not a through cavity and does not comprise an opening that is flush with the interface 16 between the oxide layer 14 and the active layer 13, so that the oxide layer 14 comprises a first portion 14a having a non-zero first thickness e1. The first portion 14a is between the cavity 30 and the active layer 13.

[0073] The oxide layer 14 thus comprises a second portion 14b having a second thickness e2 greater than the first thickness e1 of the first portion 14a. The second portion 14b is between the free surface 15 and the active layer 13.

[0074] For the sake of simplifying the figures, two cavities 30 have been shown, but it goes without saying that a donor substrate 10 can comprise in principle a high number of cavities extending parallel to one another. Preferentially, a network of cavities 30 is distributed in the oxide layer 14 so as to delimit several patterns defining the second portions 14b. In other words, each pattern forming the second portion 14b of the oxide layer 14 is delimited by the cavities 30.

[0075] The cavity or the cavity 30 network may be produced by any conventional technique. Advantageously, the cavity 30 can be produced by a succession of photolithography and etching steps, which are known and widely used in the microelectronics field. Thus, an abrupt transition between the various portions of the oxide layers having various thicknesses is advantageously obtained. This also guarantees a uniformity of the thicknesses of the layers, in particular, of the oxide layers.

[0076] After the formation of the cavity 30, the process comprises a step c) intended to form a cavity 30 filling layer. As illustrated in FIGS. 1C, 1D and 1D′, the filling layer 40 is formed so as to completely fill the cavity 30 and form a second free surface 41, which is continuous and substantially planar, and which comprises at least one first surface 43 based on the filling material.

[0077] According to one embodiment, the filling layer 40 covers the silicon oxide layer 14.

[0078] Advantageously, the filling layer 40 is made from polycrystalline silicon. Polycrystalline silicon is a material that is easy to deposit on a silicon oxide layer. In addition, this material offers the possibility of deposition at low temperatures, which makes it compatible with a structure comprising an epitaxially grown, and/or implanted, donor substrate. Finally, the polycrystalline silicon may advantageously serve both as a conductive layer under a future thin buried oxide, defined, for example, in zone 14a, and as a trapping layer (commonly known as layer of “Trap Rich” type) in zone 14b while at the same time being compatible with bonding by molecular adhesion on the receiver substrate 20.

[0079] In addition, it is known that polycrystalline silicon has a better thermal conductivity than a silicon oxide. As a result, the use of a buried silicon oxide-based layer comprising layers of polycrystalline silicon, in combination with a silicon receiver substrate, advantageously makes possible a better dissipation of the heat, from the active zone to and in the receiver substrate.

[0080] Preferentially, step c) comprises a planarization or thinning step, configured to make the second free surface 41 substantially planar. The planarization step may comprise combined actions of mechanical and chemical forces, such as a chemical mechanical polishing process, commonly known as CMP process.

[0081] According to one embodiment illustrated in FIG. 1D, step c), in particular, the planarization step is carried out so as to totally remove the polycrystalline silicon covering the second portion 14b of the oxide layer 14. In other words, step c) comprises the step of planarization or thinning of the filling layer 40 and/or of the oxide layer 14 so that the second free surface 41 also comprises a second silicon oxide surface 44.

[0082] According to another embodiment illustrated in FIG. 1D′, a polycrystalline silicon layer 42 is formed on the second portion 14b of the silicon oxide layer 14 and the filled cavity 30. Preferentially, the layer 42 has a thickness e′ of between 1 and 1000 nm. According to this embodiment, the second free surface 41 formed subsequent to step c) is entirely made from polycrystalline silicon. The layer 42 may be formed, for example, by successively adjusting the thickness of the filling layer 40 formed, then the thickness removed from the filling layer 40, after the step of planarization or thinning of the polycrystalline silicon layer 40.

[0083] As a result, the advanced substrate 1 obtained (cf. an example final substrate obtained, illustrated in FIG. 3), will advantageously comprise a buried insulating layer comprising a thick layer 14b, which has a functional layer (trapping layer, commonly known as layer of “Trap Rich” type) interposed between the receiver substrate 20 and the buried insulating layer 14b and a thin oxide layer 14a. This type of substrate will offer a possibility of efficient co-integration of components of FDSOI type arranged on a thin buried insulator (first portion 14a), and radiofrequency components arranged on a thick buried insulator (second portion 14b and a polycrystalline silicon layer) while at the same time limiting the self-bias and the crosstalk between the components conveyed via the advanced substrate 1, in particular, those induced by the strong electromagnetic radiation of the radiofrequency components. This may be possible by virtue of the functional layer (layer 42) placed “under” the thick silicon oxide portion 14b.

[0084] Moreover, the process also comprises a step d) of assembling the receiver substrate 20 and the donor substrate 10 at the second free surface 41 (cf. FIG. 1E). Advantageously, the assembling step d) is carried out by molecular adhesion. The assembling is advantageously carried out by bringing the second free surface 41 of the donor substrate 10 into direct contact with the receiver substrate 20.

[0085] In one embodiment, an additional electrically insulating layer, preferentially made from silicon oxide, can be formed on the donor substrate 10 and/or on the receiver substrate 20, before the assembling step. Advantageously, the additional layer is formed on the receiver substrate 20 so as not to disrupt the quality of the layers already produced on the donor substrate 10. The additional layer is thus interposed between the receiver substrate 20 and the donor substrate 10 (cf. for example, the final substrate obtained and illustrated in FIG. 4). This layer makes it possible to improve the quality of the assembly by molecular adhesion, in particular, if one of the surfaces brought into contact comprises polycrystalline silicon. The substrate thus formed will be similar to and will have the advantages of a double SOI. It will also make it possible to electrically insulate the receiver substrate 20 from the influences of the potentials applied in the active layer 13 and in the filling layer 40. It thus offers the possibility, for the receiver substrate 20, of itself carrying integrated circuits or a functional layer (layer 61 of FIG. 4). For example, a doped, preferentially epitaxially grown, semiconductive layer that allows the co-integration of additional components on a bulk substrate (receiver substrate 20), such as integrated memories (Embedded DRAM).

[0086] The process also comprises a step e) of removing the carrier substrate 11 after step d), while preserving the active layer 13 and the sacrificial layer 12 to obtain the advanced substrate 1 (cf. FIGS. 1F and 1F′). This removal can be carried out by any conventional technique known to those skilled in the art that is compatible with the processes used in the microelectronics field. By way of example, this removal can be carried out by abrasion or else by chemical etching, or preferentially by introduction of a weakened zone followed by fracturing.

[0087] The process according to the present disclosure is easy to implement and advantageously allows the formation of a “monolithic” substrate, which has a buried electrically insulating layer comprising at least two zones having different thicknesses, while at the same time guaranteeing a match of the electrical behavior between the zones having different thicknesses of the buried oxide layer. Indeed, by virtue of the formation of a cavity in the oxide layer, which has been filled with polycrystalline silicon before assembling the donor and receiver substrates, the advanced substrate obtained benefits from uniformity of the thicknesses of the various portions of the layers, optimal roughness and an abrupt transition between the various portions of the layers having different thicknesses. These characteristics thus make possible a large-scale integration optimized for the production of components of different types on one and the same substrate, in particular, devices of FDSOI type and radiofrequency devices.

[0088] According to one embodiment, the process comprises a step of selectively etching the sacrificial layer 12 with respect to the active layer 13, the latter being preserved on the final advanced substrate 1.

[0089] The selective etching is preferentially wet chemical etching. By way of example, the selective etching of a silicon layer with respect to a sacrificial silicon-germanium layer may be carried out using a TMAH solution. Selective etching of a silicon-germanium layer with respect to a silicon layer may be carried out using an acetic acid solution.

[0090] The selective etching advantageously makes it possible to obtain, in the end, a desired active layer, the thickness and roughness of which are equivalent to the performance of an epitaxially grown substrate, which could not be the case if a single mechanical or chemical mechanical polishing was carried out.

[0091] Advantageously, the step of selectively etching the sacrificial layer 12 with respect to the active layer 13 is carried out just before the process for producing the components on the active layer 13. This is because the sacrificial layer 12 can also act as a passivation layer, thus avoiding the formation of a layer of native oxide on the active layer 13, and also protecting the latter during the substrate storage phase.

[0092] According to one embodiment, the process also comprises the following steps (cf. FIGS. 1A to 1E): [0093] b0) Forming, before step b) and after step a), a weakened zone 50 in the carrier substrate 11, the weakened zone 50 being substantially planar and located in the vicinity of the interface between the sacrificial layer 12 and the carrier substrate 11; [0094] e0) Fracturing the carrier substrate 11 along the weakened zone 50, after step d), and, preferentially, before the selective etching of the sacrificial layer 12 if it is carried out.

[0095] In other words, the removal of the carrier substrate 11 can be carried out by detachment and fracturing of the substrate. Thus, the carrier substrate is not entirely lost and it can advantageously be reused, in particular, in a further cycle of producing another advanced substrate according to the present disclosure.

[0096] The weakened zone 50 and the interface between the sacrificial layer 12 and the carrier substrate 11 delimit a residual layer 51 intended to be transferred onto the sacrificial layer 12 after the fracturing of the carrier substrate 11.

[0097] Preferentially, the materials of the sacrificial layer 12 and of the carrier substrate are chosen so that the residual layer can be selectively etched with respect to the sacrificial layer 12. As illustrated in FIGS. 1F and 1F′, the process advantageously comprises selectively etching the residual layer 51 with respect to the sacrificial layer 12 after the fracturing step e0).

[0098] Advantageously, the filling layer 40 is formed by chemical vapor deposition at a temperature sufficiently low for it to be able to be carried out without having an impact on the weakened zone 50. Preferentially, the filling layer 40 is formed by chemical vapor deposition at a temperature between 150° C. and 250° C.

[0099] According to one embodiment, the weakened zone 50 can be obtained by implantation of at least one type of species selected from the following group: Hydrogen and Helium. The weakening implantation can also be carried out with several species implanted sequentially. Preferentially, the carrier substrate 11 is silicon based.

[0100] The conditions for creating the weakened zone 50 (species implanted, implantation energy and dose) and for fracturing depend on the thicknesses of the layers 12 and 13. Moreover, those skilled in the art will know how to adjust these conditions so as to form a weakened zone 50 in the carrier substrate 11. Moreover, the fracturing step e0) is preferentially carried out by heat treatment at a temperature that may be between 350 and 500° C.

[0101] The linking together of the steps of the process according to the present disclosure advantageously makes it possible to form a weakened zone before the structuring of the buried oxide layer by forming a cavity and then filling it with a semiconductive material. Thus, a substantially planar weakened zone can be easily and conventionally obtained, thus facilitating the fracturing and the detachment. In addition, the depositing of the filling material can be advantageously carried out at low temperatures in order to avoid premature fracturing and/or a detrimental modification of the carrier substrate before the assembling of the donor and receiver substrates.

[0102] Although all the steps of the process according to the present disclosure can been carried out at temperatures not exceeding 500° C., uniform layers having a surface roughness and surface characteristics that are optimal, in particular, compatible with a process for producing components of FDSOI type, are advantageously obtained. The process according to the present disclosure also makes it possible to dispense with the high-temperature finishing steps and to advantageously prevent recrystallization of the polycrystalline silicon layer. As a result, the polycrystalline silicon layer can act as a functional layer, such as a trapping layer (Trap Rich layer) within the final advanced substrate. Finally, the use of such a reduced temperature range would, according to one particular embodiment of the present disclosure, enable the transfer of the donor substrate formed onto a “structured” receiver substrate, comprising functional devices, in the context of a transfer of three-dimensional layers.

[0103] According to one embodiment, the active layer 13 preserved after step e) is locally thinned so as to locally reduce the thickness of the active layer 13. An advanced substrate that has an active layer that has portions with various thicknesses and a buried oxide layer that also has portions with various thicknesses is thus advantageously obtained. The advanced substrate can thus be configured to efficiently produce components having various functionalities.

[0104] Moreover, the needs previously set out may be satisfied while at the same time avoiding the abovementioned drawbacks, by also providing an advanced substrate 1 comprising (cf. FIGS. 2 and 3): [0105] A receiver substrate 20; [0106] An active layer 13 made from single-crystal semiconductor material; and [0107] An electrically insulating silicon oxide layer 14 interposed between the active layer 13 and the receiver substrate 20.

[0108] The substrate also comprises a polycrystalline silicon layer 40 placed on the receiver substrate 20. The polycrystalline silicon layer 40 is coated with the electrically insulating layer 14 so as to define a first portion 14a and a second portion 14b of the electrically insulating layer 14. The first portion 14a has a first thickness e1 and is interposed between the polycrystalline silicon layer 40 and the active layer 13. The second portion 14b of the electrically insulating layer 14 has a second thickness e2 greater than the first thickness e1. The second portion 14b is between the receiver substrate 20 and the active layer 13. Preferentially, the active layer 13 is surmounted by a sacrificial layer 12 that can be selectively etched with respect to the active layer 13, just before the production of the components in the active layer. In other words, the sacrificial layer also acts as a protective layer for the advanced substrate 1.

[0109] According to one embodiment, illustrated in FIG. 3, the advanced substrate comprises an additional layer 42 made from polycrystalline silicon, interposed between the receiver substrate 20 and the assembly formed by the electrically insulating layer 14 and the polycrystalline silicon layer 40.

[0110] According to another embodiment, illustrated in FIG. 4, the advanced substrate 1 comprises, under the layer 42, a second electrically insulating layer 60, for example, a silicon oxide layer placed on the receiver substrate 20. The receiver substrate 20 itself may comprise a functional layer 61, such as a doped epitaxially grown layer, or else may comprise microelectronic devices such as integrated circuits, in the context of a 3D approach.