Methods and apparatus for decoding received uplink transmissions using log-likelihood ratio optimization. In an embodiment, a method includes soft-demapping resource elements based on soft-demapping parameters as part of a process to generate log-likelihood ratios (LLR) values, decoding the LLRs to generate decoded data, and identifying a target performance value. The method also includes determining a performance metric from the decoded data, and performing a machine learning algorithm that dynamically adjusts the soft-demapping parameters to move the performance metric toward the target performance value.

Hard errors are determined for an unsuccessful decoding of codeword bits read from NAND memory cells via a read channel and input to a low-density parity check (LDPC) decoder. A bit error rate (BER) for the hard errors is estimated and BER for the read channel is estimated. Hard error regions are found using a single level cell (SLC) reading of the NAND memory cells. A log likelihood ratio (LLR) mapping of the codeword bits input to the LDPC decoder is changed based on the hard error regions, the hard error BER, and/or the read channel BER.

A decompression apparatus is provided. The decompression apparatus includes a memory configured to store compressed data decompressed and used in neural network processing of an artificial intelligence model, a decoder configured to include a plurality of logic circuits related to a compression method of the compressed data, decompress the compressed data through the plurality of logic circuits based on an input of the compressed data, and output the decompressed data, and a processor configured to obtain data of a neural network processible form from the data output from the decoder.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

A decoding method for low density parity code is provided. The method includes performing an iterative decoding operation for a codeword, wherein a plurality of Log-Likelihood-Ratios correspond respectively to a plurality of data bits of the codeword; determining whether the iterative decoding operation is successful; determining whether a perturbation condition is met if the iterative decoding operation is not successful; performing protect operation for a first Log-Likelihood-Ratio among the Log-Likelihood-Ratios, and performing a perturbation operation for a plurality of second Log-Likelihood-Ratios among the Log-Likelihood-Ratios, wherein the second Log-Likelihood-Ratios are different to the first Log-Likelihood-Ratio; and re-performing the iterative decoding operation for the codeword after finishing the perturbation operation.

A decoding apparatus includes input circuitry configured to receive coded data; and decoding circuitry configured to decode the coded data to obtain decoded data. The coded data are generated by using an encoding process at an encoding apparatus. The encoding process includes: (i) repeatedly collecting first data blocks included in the decoded data to generate at least one second data block; (ii) dividing at least one third data block included in the decoded data into fourth data blocks; (iii) allocating fifth data blocks included in the decoded data to respective sixth data blocks without collecting the first data blocks or dividing the at least one third data block; and (iv) performing an error correcting encoding on the at least one second data block, the fourth data blocks, and the sixth data blocks in accordance with a coding rate selected from a plurality of coding rates to generate parity data.

A processing system is described. The processing system comprises a microprocessor, a memory controller, a resource and a communication system. The microprocessor is configured to send read requests in order to request the transmission of first data, or write requests comprising second data. The memory controller is configured to read third data from a memory. The processing system comprises also a safety monitor circuit comprising an error detection circuit configured to receive data bits and respective Error Correction Code, ECC, bits, wherein the data bits correspond to the first, second or third data. The safety monitor circuit calculates further ECC bits and generates an error signal by comparing the calculated ECC bits with the received ECC bits. A fault collection and error management circuit receives the error signal from the safety monitor circuits. For example the safety monitor circuit comprises a test circuit configured to provide modified data bits and/or modified ECC bits to the error detection circuit as a function of connectivity test control signals, whereby the error detection circuit asserts the error signal as a function of the connectivity test control signals. The processing system comprises also a connectivity test control circuit comprising control registers programmable via the microprocessor, wherein the connectivity test control signals are generated as a function of the content of the control registers.

A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller to store the counted values in each of the plurality of memory cell rows as count data, determines a hammer address associated with at least one of the plurality of memory cell rows, which is intensively accessed more than a predetermined reference number of times, based on the counted values, and performs an internal read-update-write operation. The refresh control circuit receives the hammer address and to perform a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

Techniques are described for wireless communication. One method includes segmenting a payload into a plurality of code blocks; generating, for each code block, a cyclic redundancy check (CRC); encoding each code block and associated CRC in one or more codewords of a plurality of codewords; and transmitting the codewords. The encoding is based at least in part on a low density parity check code (LDPCC) encoding type. Another method includes receiving a plurality of codewords associated with a payload encoded using a LDPCC encoding type; decoding a set of the codewords associated with the first payload and a CRC; and transmitting one of an acknowledgement (ACK) or a non-acknowledgement (NAK) for the set of the codewords.

A transmission device, a transmission method, a reception device, and a reception method for securing good communication quality in data transmission using an LDPC code. The LDPC coding is performed using a parity check matrix with the code length N of 17280 bits and the coding rate r of 13/16 or 14/16. The LDPC code includes information bits and parity bits, and the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits. The information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix for every 360 columns.