INCREASING TRANSISTOR GAIN USING METAMATERIAL ELECTRODES
20230124695 · 2023-04-20
Assignee
Inventors
Cpc classification
H01L29/66462
ELECTRICITY
H01L29/7786
ELECTRICITY
H01L21/2011
ELECTRICITY
International classification
H01L21/20
ELECTRICITY
H01L29/20
ELECTRICITY
H01L29/205
ELECTRICITY
H01L29/423
ELECTRICITY
Abstract
A transistor using patterned metamaterial electrode manipulating electromagnetic waves to achieve matched phase velocity on the input and output ports. A design method is taught wherein the layout of the electrodes can be designed to compensate for the phase-velocity mismatch induced by the transistor's intrinsic properties.
Claims
1. A transistor with an input port and an output port, the transistor having matched phase velocity on the input and output ports.
2. The transistor of claim 1, further comprising: the transistor operating with a wavelength; the transistor including fingers having a finger width greater than one tenth of the wavelength.
3. A transistor electrode compensating for a phase-velocity mismatch induced by the transistor's intrinsic properties.
4. (canceled)
5. An electronic device with modified electrodes that have equal electromagnetic-wave phase velocity.
6. An electronic device for receiving an input electromagnetic wave on an input line including an input phase velocity, comprising: a first wave shifting electrode to increase the input phase velocity to a device phase velocity.
7. The electronic device of claim 6 connected to an output line with a desired output phase velocity, the electronic device comprising: a second wave shifting electrode to decrease the device phase velocity to the desired output phase velocity.
8. An electronic device with a device phase velocity connected to an output line with a desired output phase velocity, the electronic device comprising: a wave shifting electrode to decrease the device phase velocity to the desired output phase velocity.
9. An electronic device with a device phase velocity for receiving an input electromagnetic wave with an input phase velocity on an input line, the electronic device comprising: at least one multiple finger connection, the at least one finger connection using wave shifting electrodes to increase the input phase velocity on the input line to the device phase velocity.
10. An electronic device with a device phase velocity for sending an output electromagnetic wave with a desired output phase velocity on an output line, the electronic device comprising: an output multiple finger connection, the at least one finger connection using wave shifting electrodes to decrease the device phase velocity to the desired output phase velocity.
11. An electronic device with a device phase velocity for receiving an input electromagnetic wave with an input phase velocity on an input line, the electronic device comprising: an input multiple finger connection, the input multiple finger connection using input wave shifting electrodes to increase the input phase velocity on the input line to the device phase velocity; and an output multiple finger connection, the output finger connection using output wave shifting electrodes to decrease the device phase velocity to the desired output phase velocity.
Description
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0021] In the following drawings, which form a part of the specification and which are to be construed in conjunction therewith, and in which like reference numerals have been employed throughout wherever possible to indicate like parts in the various views:
[0022]
[0023]
[0024]
[0025]
[0026]
[0027]
DETAILED DESCRIPTION OF THE INVENTION
[0028] As shown in
[0029] A first embodiment shown in
[0030] Two of the most vital transistor properties for today's applications are the gain and output power that are related directly to the width of the device, especially in FET structures. The device width signifies the direction along the device electrodes, perpendicular to the flow of charges. This dimension is limited by the concept of distributed or wave propagation effects, where the device width is typically kept much smaller than the wavelength of the guided wave. This limitation is more notable when the operating frequency of the device is high and the input reactance (gate to source) and output reactance (drain to source) are significantly different in a common source configuration. The electrodes of such devices will act as transmission lines due to their comparable width to the wavelength. Consequently, the phase velocity at the input, gate electrode, and output, drain electrode, will be different. The phase velocity mismatch will cause a reduction in the amount of gain and output power of the transistor. In order to prevent this from happening, the fabricated device width is limited to less than one-tenth of the propagating wavelength, which makes the effects of the velocity mismatch ignorable. However, as a result, multiple transistor fingers are incorporated in order to obtain more output power. This approach necessitates using numerous interconnects which, in turn, adds more parasitic elements. The added parasitic elements effectively limit the device operating frequency and complicate the matching circuits.
[0031]
[0032] Drain and source conductors: 6 μm×0.12 μm
[0033] Gate stem: 0.1 μm×0.22 μm
[0034] Gate top: 0.45 μm×0.53 μm
[0035] Gate-source spacing: 0.3 μm
[0036] Gate-drain spacing: 1.6 μm
[0037] The 19-element equivalent circuit model for the GaN HEMT device is depicted in
[0038] According to the device structure in
[0039] One of the other outcomes of the small transistor cross-sectional dimensions, with respect to the wavelength of the propagating wave, is that the AlN, AlGaN, GaN, and substrate layers under the electrodes do not have an effect on the solution of the magnetic field. Hence, the electrodes are assumed to be in free space where the relative permittivity of the medium is one. The extraction process starts with solving the 3D Laplace equation for the new structure and finding the self-capacitance on each conductor, where one electrode is excited by a voltage and the charge is then observed on the same electrode. The inductance of the line is derived by using equation (1), where c is the speed of light, C is the per unit width self-capacitance on each conductor, and L denotes the per unit width inductance of the line.
c=1/√{square root over (LC)} (1)
[0040] The presence of conductance parameter is tied to the conductivity of all the layers under the electrodes since the conducting path is through the dielectric or semiconductor materials. This parameter is derived by using equation (2). Based on the doping types and the fact that the mobility of electrons is larger than that of holes, we assume that the conduction in the layers is entirely due to electrons. Hence, n is the carrier concentration, u. denotes the electron mobility, q is the electron charge, and σ shows the conductivity. Similar to obtaining the capacitance, the 3D structure of the device is arranged, without the need to define magnetic walls as the boundary conditions. The mutual conductance is obtained by applying a voltage to one electrode and observing the current on the other two conductors
σ=qμn (2)
[0041] In order to find the resistance or conductor loss of the line, Wheeler's Incremental Inductance rule is used. Since gold and titanium, as the materials used for fabricating the conductors, are lossy metals, the magnetic field penetrates the electrodes, which leads to generation of an internal inductance. To estimate the value of it, first the external inductance of the line is calculated as explained before. Then, all the surfaces of the conductors are recessed by a small amount equal to half the skin depth and the external inductance is calculated for the new case as well. The difference between the two calculated values indicates the internal inductance as explained in equation (3), where δ denotes the skin depth, L.sub.int is the internal inductance, and L.sub.ext signifies the external inductance. Moreover, the current flow within the electrodes causes a surface impedance for which the real and imaginary parts are equal. This relates the resistance of the line to the internal inductance as explained in equation (4), where ω indicates the angular operating frequency.
L.sub.int=L.sub.ext(x)−L.sub.ext(x−δ/2) (3)
R=ωL.sub.int (4)
[0042] Finally, the proposed device is simulated in a common-source configuration using SILVACO. The Y-parameters of the two port equivalent model is obtained over a defined frequency range and the intrinsic parameter values of the device are calculated. Other than the 9 defined elements for the intrinsic part of the model, there are two resistance elements associated with the gate-drain and gate-source current leakage. For the state-of-the-art GaN HEMTs, these elements possess negligibly small values and are not needed to be considered in the model. Furthermore, since the gate length of the device is very small and the operating frequency is high, the proposed relations do not yield an accurate value for gate-drain resistance and this parameter must be optimized to fit the obtained results. The per unit width parameter values for the intrinsic and extrinsic elements are summarized in Table I. An unconditionally stable implicit finite difference numerical method is used for the analysis of the device in different frequency bands and the results show good agreements with the obtained results from fabrication.
TABLE-US-00001 TABLE 1 Extracted parameter values Extrinsic Parameters Intrinsic Parameters L.sub.Se = 2.40 nH/cm C.sub.GDe = 314 fF/cm C.sub.GSi = 8.38 pF/cm L.sub.Ge = 2.58 nH/cm C.sub.GSe = 898 fF/cm R.sub.GSi = 5.56 mΩ .Math. cm L.sub.De = 4.48 nH/cm C.sub.DSe = 572 fF/cm C.sub.GDi = 332 fF/cm R.sub.Se = 60 Ω/cm G.sub.GDe = 0.01 mS/cm R.sub.GDi = 238 mΩ .Math. cm R.sub.Ge = 165 Ω/cm G.sub.GSe = 0.02 mS/cm C.sub.DSi = 21.5 pF/cm R.sub.De = 60 Ω/cm G.sub.DSe = 0.01 mS/cm G.sub.DSi = 1.70 S/cm g.sub.m = 6.10 S/cm
[0043] For an operating frequency of f=60 GHz, the propagating wavelength in free space is equal to 2=5000 μm, that is the speed of light divided by the frequency. However, the speed of the propagating wave in the device is roughly one-third of this value which makes the guided wavelength be equal to λ.sub.s=1667 μs. If the device width is assumed to be 300 μm, this dimension will be comparable to the wavelength of device since it is not smaller than one-tenth of it. Consequently, the wave propagation effects will be pronounced and it is predicted that there will be a phase velocity mismatch in this device. In order to have a point of comparison, the current gain of this device is calculated using equation (5). The value for the current gain at 60 GHz is equal to 3.85 dB. According to the obtained parameter values in Table 1, the phase velocity at the input and output ports of the device must be calculated and two operating modes, namely even and odd, are considered for this purpose.
G.sub.c=20×log(I.sub.out/in) (5)
[0044] For the even or gate mode, the source and drain lines are excited with a negative voltage and a positive voltage is applied to the gate conductor. The per unit width extrinsic capacitance on the gate line is calculated based on the proposed method, which is equal to C.sub.g=1.21×10.sup.−12 F/cm. The intrinsic capacitance associated with this conductor is also added to this value and the resulting C.sub.even=1.04×10.sup.−11 F/cm is obtained. Using the L.sub.g value from Table 1, the phase velocity on the gate line becomes v.sub.p=6.10×10.sup.9 cm/s, which is calculated using equation (6). This equation is similar to equation (1) and both the capacitance and inductance are calculated for one unit width of the device.
v.sub.p=1/√{square root over (LC)} (6)
[0045] To excite the conductors for the odd or drain mode, a positive voltage is applied to the drain electrode and the source is connected to a negative voltage. The capacitance on the drain is obtained (C.sub.d=8.26×10.sup.−13 F/cm) and added to the capacitance value for the intrinsic part of the device related to the drain electrode. The total value equals to C.sub.odd=2.95×10.sup.−12 F/cm. Using the per unit width L.sub.d value from Table 1 and equation (6), the resulting phase velocity on the drain electrode becomes v.sub.d=8.70×10.sup.9 cm/s. Clearly, there is velocity mismatch between the input (gate) and output (drain) conductors of about 43%, which is a reason for lower gain and output power of the device.
[0046] The main contributions of this work can be summarized as follows: (1) To improve the performance of a high-frequency transistor (i.e., increasing output power, gain, cut-off frequency, etc.), the transistor electrodes are designed to provide matched phase velocities on the input and output ports. (2) This phase velocity matching can be accomplished by properly designing the electrodes, with minimal limitations due to the transistor's cross-sectional design. In other words, this work proposes that the layout of the electrodes can be designed to compensate for the phase-velocity mismatch induced by the transistor's intrinsic properties. (3) This work provides an example for realizing this phase-velocity matching using metamaterial concepts, based on which a new set of electrodes are designed. (4) Transistors designed based on this concept may be realized in wider fingers (i.e., longer than one tenth of the wavelength) due to the matched phase velocity. Hence, a much smaller number of wider electrodes can be used to provide certain power and gain. Consequently, the losses, discontinuities inside the device, and possibly the transistor's footprint can be reduced. (5) Typically, metamaterials are arranged in some defined repeating patterns and have properties that the natural materials does not possess, making them capable of manipulating electromagnetic waves.
[0047] In order to match the phase velocity of the output port to the input port, the drain electrode is designed using metamaterial concepts and the above-mentioned procedure is applied to the new device to find the phase velocity on the drain conductor. The new drain capacitance equals C.sub.d=1.39×10.sup.−12 F/cm and when added to the intrinsic capacitance, the resulting value becomes C.sub.even=3.51×10.sup.−12 F/cm. Moreover, the effect of the new design on the inductance is also considered and the drain inductance is obtained (L.sub.d=7.35×10.sup.−9 H/cm). Using the new values obtained for the capacitance and inductance, the phase velocity on the drain conductor becomes v.sub.d=6.22×10.sup.9 cm/s, which is almost identical to the phase velocity on the gate electrode. The current gain of the new transistor with the same width (300 μm) at an operating frequency of 60 GHz is calculated which equals to 8.86 dB. This figure shows a 130% increase in the amount of gain compared to the previous case.
[0048] The modeling procedure utilized for the simulation of the transistor has already been verified with the results obtained from a fabricated GaN HEMT device. This method is comprised of three different simulation tools, namely COMSOL Multiphysics, SILVACO, and a finite-difference time-domain analysis. Correspondingly, the redesigned electrode configurations and the new transistor model are all simulated and compared using this procedure.
[0049]
[0050]
[0051]
[0052] The main parameter that imposes this limitation on the high-frequency operability of the device is the intrinsic gate-source capacitance. It suppresses the velocity of the signal on the gate electrode which results in a mismatch between the drain and gate electrodes. Hence, the solution for matching the velocity of the signals on the input and output ports lies in adjusting the extrinsic parameters on the drain side to reduce the signal velocity. In other words, the optimized electrode design will be a compensation for the imposed limitations by the intrinsic device parameters.
[0053]
[0054] m the foregoing, it will be seen that this invention well adapted to obtain all the ends and objects herein set forth, together with other advantages which are inherent to the structure. It will also be understood that certain features and subcombinations are of utility and may be employed without reference to other features and subcombinations. This is contemplated by and is within the scope of the claims. Many possible embodiments may be made of the invention without departing from the scope thereof. Therefore, it is to be understood that all matter herein set forth or shown in the accompanying drawings is to be interpreted as illustrative and not in a limiting sense. When interpreting the claims of this application, method claims may be recognized by the explicit use of the word ‘method’ in the preamble of the claims and the use of the ‘ing’ tense of the active word. Method claims should not be interpreted to have particular steps in a particular order unless the claim element specifically refers to a previous element, a previous action, or the result of a previous action. Apparatus claims may be recognized by the use of the word ‘apparatus’ in the preamble of the claim and should not be interpreted to have ‘means plus function language’ unless the word ‘means’ is specifically used in the claim element. The words ‘defining,’ having,' or ‘including’ should be interpreted as open ended claim language that allows additional elements or structures. Finally, where the claims recite “a” or “a first” element of the equivalent thereof, such claims should be understood to include incorporation of one or more such elements, neither requiring nor excluding two or more such elements.