Method for Forming an Interconnection Structure

Abstract

A method for forming an interconnection structure for a first transistor and a second transistor is provided, wherein the first transistor includes a horizontally extending first channel portion (112) and the second transistor includes a horizontally extending second (122) channel portion, and wherein the channel portions are stacked above each other on a substrate. The method comprises forming a conductive line (130) extending beside and below the second channel portion, forming, on the conductive line, a first vertical interconnect structure (132) for electrically contacting the first channel portion, and thinning the substrate from the backside to expose the conductive line from below. The method further comprises forming a via hole (146) exposing the second channel portion from below, filling the via hole with a conductive material to form a second vertical interconnect structure (142), and forming a conductive structure (140) on the second vertical interconnect structure. A semiconductor device is also provided.

Claims

1. A method for forming an interconnection structure for a first transistor and a second transistor vertically stacked on a substrate, wherein the first transistor includes a horizontally extending first channel portion and the second transistor includes a horizontally extending second channel portion, and wherein the first channel portion is arranged above the second channel portion, the method comprising: forming, in the substrate, a conductive line extending beside and below the second channel portion; forming, on the conductive line, a first vertical interconnect structure for electrically contacting the first channel portion; thinning the substrate from a backside to expose the conductive line from below; forming a via hole exposing the second channel portion from below; filling the via hole with a conductive material to form a second vertical interconnect structure; and forming a conductive structure on the second vertical interconnect structure.

2. The method according to claim 1, further comprising: forming a bonding layer above the first vertical interconnect structure; bonding a carrier wafer to the bonding layer; and flipping the substrate upside down to allow processing from the backside of the substrate.

3. The method according to claim 1, further comprising: depositing an insulating layer covering the conductive line and the first and second channel portions; etching a trench in the insulating layer to expose the conductive line and the first and second channel portions; forming spacers at sidewalls of the first and second channel portions; and filling the trench with the conductive material forming the first vertical interconnect structure contacting the first channel portion at least partly from above.

4. The method according to claim 3, further comprising: forming a bonding layer above the first vertical interconnect structure; bonding a carrier wafer to the bonding layer; and flipping the substrate upside down to allow processing from the backside of the substrate.

5. The method according to claim 2, further comprising: forming, from the backside, a trench that is aligned with the second channel portion; forming the via hole in a bottom of the trench; and depositing the conductive material to fill the via hole and the trench, thereby forming the second vertical interconnect and the conductive structure.

6. The method according to claim 1, wherein an exposed portion of the conductive line and an exposed portion of the conductive structure are arranged on the same vertical level.

7. The method according to claim 1, further comprising: epitaxially forming a stacked structure comprising alternating layers of a channel material and a sacrificial material; patterning the stacked structure into a fin; and removing the layers of sacrificial material from at least a portion of the fin, wherein the remaining portions of the channel material form the first and second channel portions.

8. The method according to claim 7, further comprising forming a gate structure at least partly enclosing the first and second channel portions.

9. The method according to claim 7, wherein the channel material is formed of Si and the sacrificial material is formed of SiGe.

10. The method according to claim 9, further comprising forming a gate structure at least partly enclosing the first and second channel portions.

11. The method according to claim 1, wherein the substrate comprises an etch stop layer, and wherein forming the conductive line comprises etching down to the etch stop layer.

12. The method according to claim 1, comprising forming, in the substrate, a first and a second conductive line on opposite sides of the second channel portion, wherein the first vertical interconnect structure is arranged to interconnect the second channel portion with each of the first and second conductive lines.

13. A semiconductor device, comprising: a first transistor and a second transistor vertically stacked on a substrate, wherein the first transistor includes a horizontally extending first channel portion and the second transistor includes a horizontally extending second channel portion, and wherein the first channel portion is arranged above the second channel portion; a conductive line arranged in the substrate and extending beside and below the second channel portion; a first vertical interconnect structure arranged on the conductive line and for contacting the first channel portion; a conductive structure arranged below the second channel portion; and a second vertical interconnect structure extending between the second channel portion and the conductive structure.

14. The semiconductor device according to claim 13, wherein a bottom portion of the conductive line and a bottom portion of the conductive structure are arranged at the same vertical level.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0035] The above, as well as additional objects, features and benefits of the present disclosure, will be better understood through the following illustrative and non-limiting detailed description, with reference to the appended drawings. In the drawings like reference numerals will be used for like elements unless stated otherwise.

[0036] FIGS. 1-10 illustrate a method for forming an interconnection structure.

[0037] FIG. 1 shows a representative stacked structure comprising a first channel portion 112 and a second channel portion 122 for a respective transistor device which, during operation, conducts current through the channel portions along a horizontal direction (out of the plane of the figure). The first channel portion 112 and the second channel portion 122 are vertically stacked above a substrate 100, with the first channel portion 112 arranged above the second channel portion 122 as seen along a normal direction from the substrate 100.

[0038] FIG. 2 shows a pair of conductive lines 130 has been formed at a respective side of the first and second channel portions 112, 122.

[0039] FIG. 3 shows the arrangement in FIG. 2 after a trench 152 has been formed in the insulating layer to expose the conductive line 130 and the first and second channel portions 112, 122.

[0040] FIG. 4 shows, spacers 154 formed at sidewalls of the first and second channel portions 112, 122. The conformal insulating material layer may thus cover both lateral and horizontal surfaces in the trench 152.

[0041] FIG. 5 shows spacers 154 formed at sidewalls of the first and second channel portions 112, 122.

[0042] FIG. 6 shows the trench 152 filled with a conductive material forming the first vertical interconnect structure 132. The first vertical interconnect structure 132 may thus extend from the conductive line 130 all the way up to the first channel portion 112. The gate structure 134, at least partly encapsulating the first channel portion 112, may be contacted at least from above by the first vertical interconnect structure 132, and further at portions of the sidewalls of the first channel portion 112 which are not covered by the spacers 154.

[0043] FIG. 7 shows subsequent processing where the back end of line, BEOL, part of the fabrication, metallisation layers 170 may be added above the first channel portion 112 and the first vertical interconnect 132.

[0044] FIG. 8 shows the result of thinning the substrate 100 from the backside, usually down to the etch stop layer 104, followed by a planarizing step (such as CMP) to expose the conductive lines 130 from below.

[0045] FIG. 9 shows that the remaining substrate material has been removed, generally in an etch process utilising an etch selectivity between the substrate material and the surrounding insulating layer 150. As shown, a via hole, or recess 144 is formed, which is aligned with the second channel portion 122.

[0046] FIG. 10 shows a via hole 146 etched through the insulating material to expose the underlying second channel portion 122 and allow it to be contacted by a second vertical interconnect structure.

DETAILED DESCRIPTION OF THE PRESENT DISCLOSURE

[0047] A method for forming an interconnection structure, suitable for instance for a semiconductor device, will now be described with reference to FIGS. 1-10. The method will be described in connection with forming an interconnection structure for a first and a second channel portion of a respective horizontally arranged field-effect transistor, FET, formed from a fin structure. It is however noted that the method may be applicable for forming an interconnection structure for vertically stacked conductive structures in general, such as semiconductor device contacts (for instance source/drain contacts).

[0048] With reference to FIG. 1, a vertical cross section of an intermediate structure or device is shown. The structure may extend laterally or horizontally beyond the illustrated section. The illustrated planes of section extending through the structure are common to all the figures unless stated otherwise. It is noted that the relative dimensions of the shown elements, in particular the relative thickness of the layers, is merely schematic and may, for the purpose of illustrational clarity, differ from a physical structure. Further, it will be appreciated that other features and layers may have been omitted and that only those elements which are relevant for illustrating the present disclosure, as defined in the appended claims, may have been included in the drawings.

[0049] FIG. 1 shows a stacked structure comprising a first channel portion 112 and a second channel portion 122 for a respective transistor device which, during operation, conducts current through the channel portions along a horizontal direction (out of the plane of the figure). The first channel portion 112 and the second channel portion 122 are vertically stacked above a substrate 100, with the first channel portion 112 arranged above the second channel portion 122 as seen along a normal direction from the substrate 100.

[0050] In the present example, the channel portions 112, 122 may be formed from a stacked structure 102 comprising alternating layers of a channel material, forming the respective channel portions 112, 122 and a sacrificial material 106 arranged in between. The layer stack 102 may for instance be formed by epitaxial growth, such as a blanket epitaxy process, and patterned into for instance a fin as illustrated in FIG. 1. The fin may for instance be formed using a sequence of lithography and etching steps, also referred to as a litho-etch sequence. A litho-etch sequence may generally comprise forming a photoresist mask layer on the layer which will be patterned, i.e., “the target layer”. A pattern (e.g. a pattern of openings, trenches or line) may be lithographically defined in the photoresist layer and then transferred into the target layer by etching while using the patterned photoresist layer as an etch mask. The photoresist layer may thereafter be stripped from the target layer.

[0051] The channel material and the sacrificial material may be selected to allow a selective removal of the sacrificial material, for instance by means of a selective etch. The channel material may for example be formed of Si, and the sacrificial material of SiGe. As SiGe and Si can be etched at different etch rates, the contrast in etch rate can be used to release the channel portions 112, 122 by selectively removing the sacrificial layers 106 in between.

[0052] The substrate 100 may for example be a Si substrate, onto which the stacked structure of channel material layers and sacrificial material layers may be formed. For the purpose of the present disclosure the channel material layers may be considered as arranged on the frontside of the substrate, with the first channel portion 112 arranged above the second channel portion 122 which hence is located between the first channel portion 112 and an upper surface of the substrate 100.

[0053] In FIG. 2, a pair of conductive lines 130 has been formed at a respective side of the first and second channel portions 112, 122. While the present figure illustrates two conductive lines 130, it will be appreciated that the present disclosure is also applicable for asymmetric configurations, comprising for instance a single conductive line 130. The conductive line 130 may in some examples be referred to as a buried power rail. The conductive line 130 may be formed in a trench extending in the substrate 100 and, in some examples, along at least a portion of the first and second channel portions 112, 122. The trench may for example be etched down to the etch stop layer 104. As illustrated in the present figure, the conductive lines 130 may be arranged vertically below and laterally beside the first channel portion 112 and usually also the second channel portion 122. Further, the conductive line 130 may at least partly extend also in an insulating layer 150, such as an interlayer dielectric, ILD, arranged above the substrate 100. The conductive line 130 may be formed in two steps, in which a bottom portion of the conductive line 130 is formed in a trench in the substrate 100 and the remaining portion of the conductive line 130 is formed in a trench in the insulating layer 150. Alternatively, the conductive line 130 is formed in a single filling process, in which a trench is formed in the insulating layer 150 and extending all the way into the substrate 100. The conductive line 130 may comprise one or several layers, such as for example a barrier layer 136 arranged between the substrate 100 and the conductive material forming the conductive line 130.

[0054] The insulating layer 150 may be a dielectric layer, such as a layer of silicon oxide or some other conventional low-k dielectric layer. The insulating layer 150 may be deposited by chemical vapour deposition, CVD, as one example.

[0055] The first and second channel portions 112, 122 may comprise, and/or be at least partly encapsulated by, a channel portion interconnect structure 134. The channel portion interconnect structure 134 may for example be arranged at the source/drain portions of the transistor structure or form a gate structure 134 at the respective channel portions 112, 122. The gate structure 134 may comprise one or several gate layers, depending on the type and configuration of the transistor structure of which the channel portions 112, 122 form part. The gate layers may for instance form a gate layer stack including a gate dielectric layer formed by any conventional gate dielectric material such as HfO.sub.2, ZrO.sub.2, Al.sub.2O.sub.3 or some other high-K dielectric material. The gate dielectric material may be deposited as a conformal thin film by any conventional deposition process, for instance by ALD. The gate layers may further comprise at least a first conductive gate layer that is subsequently formed on the gate dielectric layer. The first conductive gate layer may be formed by an effective work function metal (EWF). The first conductive gate layer may for instance be formed by one or more p-type EWF metals such as TiN, TaN, TiTaN or by one or more n-type EWF metals such as Al, TiAl, TiC, or TiAlC, or compound layers such as TiN/TiAl or TiN/TaN/TiAl. The first conductive gate layer may be deposited by any conventional deposition process, for instance by ALD, CVD or PVD. The gate layers may further include a second conductive gate layer, for instance of W, Al, Co, Ni, Ru or an alloy of two or more of said materials, to provide a gate electrode with the desired electrical properties. The second conductive gate layer may be deposited by any conventional deposition process, for instance by CVD or by electro-plating.

[0056] FIG. 3 shows the arrangement in FIG. 2 after a trench 152 has been formed in the insulating layer to expose the conductive line 130 and the first and second channel portions 112, 122. The trench 152 may for example be formed using a litho-etch sequence as mentioned above. In the present example, where a conductive line 130 is arranged on a respective side of the stack of channel portions 112, 122 the trench may be arranged to extend laterally on both sides of the stack of channel portions 112, 122 so as to allow both conductive lines 130 to be exposed at the bottom of the trench 152.

[0057] In FIGS. 4 and 5, spacers 154 have been formed at sidewalls of the first and second channel portions 112, 122. The spacers 154 may for example be formed of an insulating material, for instance oxide, which may be conformally deposited in the trench 152. The conformal insulating material layer, shown in FIG. 4, may thus cover both lateral and horizontal surfaces in the trench 152. To form the spacers 154, the insulating material layer may be subject to anisotropic etching to expose horizontal structures such as top surfaces of the conductive lines 130 in the bottom of the trench 152 as well as a top surface of the first channel portion 112, while leaving insulating spacers 154 on vertical sidewalls of for instance the second channel portion 122. The spacers 154 may thus provide electrical insulation for the second channel portion 122.

[0058] In FIG. 6, the trench 152 has been filled with a conductive material forming the first vertical interconnect structure 132. The first vertical interconnect structure 132 may thus extend from the conductive line 130 all the way up to the first channel portion 112. The gate structure 134, at least partly encapsulating the first channel portion 112, may be contacted at least from above by the first vertical interconnect structure 132, and further at portions of the sidewalls of the first channel portion 112 which are not covered by the spacers 154. Thus, the first vertical interconnect structure 132 provides an electrical interconnection between the first channel portion, or top channel portion 112, and the conductive line 130 (also referred to as top buried power rail). At the same time, the spacers 154 may prevent the second channel portion 122 from being contacted by the first vertical interconnect 132 passing beside the second channel portion 122.

[0059] The conductive line 130 and the first vertical interconnect structure 132 may for instance be formed in a damascene like process, in which a trench (such as trench 152) is filled with a conductive material, for instance tungsten, recessed by for instance chemical-mechanical polishing, and covered by an insulating layer of for example an oxide. The resulting structure is illustrated in FIG. 6.

[0060] In subsequent processing, for instance the back end of line, BEOL, part of the fabrication, metallisation layers 170 may be added above the first channel portion 112 and the first vertical interconnect 132, as illustrated in FIG. 7.

[0061] In order to allow the processing to be continued from below, that is, from the backside, the substrate 100 may be turned upside down and bonded to a carrier wafer 162. In the example of FIG. 7, the substrate 100 is bonded face-down to a carrier wafer 162, usually by means of a bonding layer 160 arranged between the substrate 100 and the carrier wafer 162. The BEOL metallization layer 170 is indicated for exemplary purposes. As further illustrated in FIG. 7, the substrate 100 may be thinned from the backside, usually down to the etch stop layer 104, followed by a planarizing step (such as CMP) to expose the conductive lines 130 from below. The resulting structure is shown in FIG. 8.

[0062] In FIG. 9, the remaining substrate material has been removed, generally in an etch process utilising an etch selectivity between the substrate material and the surrounding insulating layer 150. As illustrated in the present figure a via hole, or recess 144 is formed, which is aligned with the second channel portion 122. The recess 144 may have a shape which in a first lateral direction, between the two conductive lines 130, is defined by the lateral extension of the previously removed substrate material (for instance corresponding to a width of the fin shown in FIG. 1) and in a second lateral direction, parallel to the conductive lines 130, is defined by the lithography process.

[0063] In the bottom of the recess 144 a via hole 146 may be formed, extending down to the gate structure 134 at least partly encapsulating the second channel portion 122. Thus, the via hole 146 may be etched through the insulating material to expose the underlying second channel portion 122 and allow it to be contacted by a second vertical interconnect structure, as shown in FIG. 10. The second vertical interconnect structure 142 may be formed by a conductive material deposited, for example by a damascene-style process, in the via hole 146 and extending up to the recess 144. The recess 144 may in some examples be filled by the same material and in the same processing step as the via hole 146, and in other examples by a separate material and/or process. The filled recess 144 shown in FIG. 10 forms a conductive structure, or second buried power rail, which may be arranged at a similar vertical level as the conductive lines 130 and provide a similar interconnection to the second channel portion 122.

[0064] The resulting interconnection structure shown in FIG. 10 allows for the first channel portion 112 to be electrically connected through (in this example two) conductive lines 130, and the second channel portion 122 to be electrically connected through a conductive structure 140 arranged between the two conductive lines 130. The first vertical interconnect structure 132 may be provided with a cross sectional area which is dimensioned to at least somewhat compensate for the increase in electrical resistance added by the height difference caused by the first channel portion being arranged at a different vertical level than the second channel portion 122.