DEVICE COMPRISING SPACERS INCLUDING A LOCALISED AIRGAP AND ASSOCIATED MANUFACTURING METHODS

Abstract

A semiconductor device made on a substrate including an active region and a non-active region at least partially surrounding the active region, a plurality of gate stacks, a part of each gate stack being on the active region, each gate stack being separated from adjacent gate stacks by a spacer by a distance e, the device being such that, for each gate stack, the part of the gate stack located on the active region has a height h.sub.2, the part of the same gate stack located on the non-active region has a height h.sub.1, and h.sub.2/e=a.sub.2 and h.sub.1/e=a.sub.1<a.sub.lim where a.sub.2 is an aspect ratio such that, upon growth of the spacer material forming the spacers, an airgap is in the spacer, and a.sub.1 is an aspect ratio such that, upon growth of the spacer material forming the spacers, no airgap is in the spacer.

Claims

1. A semiconductor device made on a substrate comprising at least one active region and at least one non-active region at least partially surrounding the at least one active region, a plurality of gate stacks, a part of each gate stack of the plurality of gate stacks being on the at least one active region and a part of said plurality of gate stacks being on the at least one non-active region, each gate stack being separated from at least one of the adjacent gate stacks by a spacer by a distance equal to e, wherein, for each gate stack of the plurality of gate stacks, the part of the gate stack located on the at least one active region has a height h.sub.2, the part of the same gate stack located on the at least one non-active region has a height h.sub.1, and in that h.sub.2/e=a.sub.2 and h.sub.1/e=a.sub.1 where a.sub.2 is an aspect ratio such that, upon growth of the spacer material forming the spacers, an airgap is in said spacer, and a.sub.1 is an aspect ratio such that, upon growth of the spacer material forming the spacers, no airgap is in said spacer.

2. The semiconductor device according to claim 1, wherein a surface of the at least one active region is located in a first plane and a surface of the at least one non-active region is located in a second plane, the first plane being located at a height lower than that of the second plane, a difference in height Δh between the first plane and the second plane being equal to the difference between the height h.sub.2 of the gate stacks on the at least one active region and the height h.sub.1 of the gate stacks on the non-active region.

3. The semiconductor device according to claim 1, wherein the spacers are formed by a layer of spacer material having a thickness t greater than or equal to 0.3×e.

4. The semiconductor device according to claim 1, comprising a plurality of active regions.

5. The semiconductor device according to claim 1, wherein a.sub.2≥1.5 and a.sub.1≤1.

6. The semiconductor device according to claim 1, wherein the height h.sub.1 is between 30 and 50 nm, the height h.sub.2 is between 60 and 100 nm and/or the distance e separating two successive gate stacks is between 20 and 40 nm.

7. The semiconductor device according to claim 1, wherein the spacers are of nitride.

8. A method for manufacturing a semiconductor device from a substrate comprising at least one active region and at least one non-active region at least partially surrounding the active region, a surface of the at least one active region is located in a first plane and a surface of the at least one non-active region is located in a second plane, the first plane being located at a height lower than that of the second plane, the method comprising: forming a plurality of gate stacks parallel to each other, each gate stack being separated from the nearest gate stack(s) by a distance e; depositing a layer of a spacer material so as to form a spacer between each gate stack; depositing a layer of a dielectric material; performing a mechanical-chemical polishing so that, at the end of the mechanical-chemical polishing, the part of the gate stacks located on the active region has a height h.sub.2; a height between the first plane and the second plane being equal to Δh, the height h.sub.2, the difference in height Δh and the distance e separating two gate stacks being chosen so that h.sub.2/e=a.sub.2 and (h.sub.2−Δh)/e=a.sub.1 where a.sub.2 is an aspect ratio such that, upon growth of the spacer material forming the spacers, an airgap forms within said spacer, and a.sub.1 is an aspect ratio such that, upon growth of the spacer material forming the spacers, no airgap forms within said spacer.

9. The method according to claim 8, wherein the mechanical-chemical polishing comprises: a first mechanical-chemical polishing so as to level the layer of dielectric material; a second mechanical-chemical polishing so that, at the end of the second mechanical-chemical polishing, the part of the gate stacks located on the active region has a height h.sub.2.

10. A method for manufacturing a semiconductor device from a substrate comprising at least one active region and at least one non-active region at least partially surrounding the at least one active region, a surface of the at least one active region is located in a first plane and a surface of the at least one non-active region is located in a second plane, the first plane being located at a height lower than that of the second plane, the method comprising: full plate depositing a layer of gate stack; performing a mechanical-chemical polishing so that the layer of gate stacks located on the active region at the end of the mechanical-chemical polishing has a thickness h.sub.2; forming, from the layer of gate stack, a plurality of gate stacks parallel to each other, each gate stack being separated from the nearest gate stack(s) by a distance e; depositing a layer of a spacer material so as to form a spacer between each gate stack; the difference in height between the first plane and the second plane being equal to Δh, the thickness h.sub.2, a difference in height Δh and the distance e separating two gate stacks being chosen so that h.sub.2/e=a.sub.2 and (h.sub.2−Δh)/e=a.sub.1 where a.sub.2 is an aspect ratio such that, upon growth of the spacer material forming the spacers, an airgap forms within said spacer, and a.sub.1 is an aspect ratio such that, upon growth of the spacer material forming the spacers, no airgap forms within said spacer.

11. The method according to claim 10, wherein the spacer material is silicon nitride.

12. The method according to claim 10, wherein a thickness t of spacer material such that t≥0.3×e is deposited in the step of depositing a layer of a spacer material.

13. The method according to claim 10, wherein a.sub.2 1.5 and a.sub.1≤1.

14. The method according to claim 10, wherein the depositing of the spacer material is performed by plasma-enhanced chemical vapour deposition, low-pressure chemical vapour deposition or sub-atmospheric pressure chemical vapour deposition.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0039] The figures are set forth as an indication and in no way as a limitation of the invention.

[0040] FIG. 1A to FIG. 1E illustrate a semiconductor device according to an embodiment of the invention.

[0041] FIG. 2A shows the formation of an airgap in the spacer when the form factor of the structure is sufficiently high.

[0042] The FIG. 2B shows the absence of formation of an airgap in the spacer when the form factor of the structure is not sufficiently high.

[0043] FIG. 3 shows a graphical representation of the form aspects for obtaining an airgap when forming spacers.

[0044] FIG. 4 shows a flow chart of a manufacturing method according to a second aspect of the invention.

[0045] FIG. 5 to FIG. 9B schematically show the steps of a manufacturing method according to a second aspect of the invention.

[0046] FIG. 10 shows a flow chart of a manufacturing method according to a third aspect of the invention.

[0047] FIG. 11A to FIG. 14B schematically show the steps of a manufacturing method according to a third aspect of the invention.

DETAILED DESCRIPTION

[0048] The figures are set forth as an indication and in no way as a limitation of the invention.

[0049] Semiconductor Device with Localised Airgaps

[0050] A first aspect of the invention illustrated in [FIG. 1A] to [FIG. 1E] relates to a semiconductor device DI made on a substrate comprising at least one active region RA and one non-active region RA at least partially surrounding the active region RA. As illustrated in [FIG. 1E], when several active regions RA are present, then the non-active region RN at least partially surrounds said active regions RA.

[0051] By active region RA, it is meant a region which comprises a layer of semiconductor material, for example silicon, capable of forming, together with the gate stacks EG, a channel as well as the transistor sources and drains. By non-active region RN, it is meant a region that does not comprise semiconductor material capable of forming, together with the gate stacks EG, a transistor channel. A non-active region RN (also known as an isolation zone) can for example consist of or comprise an STI (for Shallow Trench Isolation—a well-known feature in the field). In an embodiment, the substrate is an SOI type substrate. In an embodiment, the active region RA is then formed by a layer of silicon and the non-active region RN is then formed by an STI on SOI.

[0052] In addition, as illustrated in [FIG. 1A], the device DI according to an embodiment of the invention comprises a plurality of gate stacks EG, each gate stack EG of the plurality of gate stacks EG being parallel to the other gate stacks EG of the plurality of gate stacks EG. In addition, as illustrated in [FIG. 1B] and [FIG. 1C] (which represent the device DI along section C1 and section C2 respectively), each gate stack EG is separated from the adjacent gate stacks EG by a distance equal to e by means of a spacer ES. In general, as illustrated in [FIG. 1B], a gate stack EG comprises a gate oxide OG (for example silicon oxide), a layer of metal ME on the gate oxide OG (for example titanium nitride) and a layer of polysilicon PS on the layer of metal ME. However, other configurations may be considered.

[0053] Furthermore, as illustrated in [FIG. 1A] to [FIG. 1C], each gate stack EG is disposed such that a part of the stack EG under consideration is on the active region RA. As a result, each gate stack EG is also disposed such that a part of the gate stack EG under consideration is on the non-active region RN.

[0054] In addition, as illustrated in [FIG. 1D] which represents a view of the device along section C3, for each gate stack EG, the part of the gate stack EG under consideration located on the non-active region RN at a first height h.sub.1 and the part of the gate stack EG under consideration located on the active region RA at a second height h.sub.2, the second height h.sub.2 being higher than the first height h.sub.1. In the following, the difference between the second height h.sub.2 and the first height h.sub.1 will be denoted as Δh. In an embodiment, the surface of the active region RA is located in a first plane P1 and the surface of the non-active region RN is located in a second plane P2, the first plane P1 being located at a height lower by Δh than that of the second plane P2.

[0055] Furthermore, in the device DI according to an embodiment of the invention, for each gate stack EG of the plurality of gate stacks EG, the height h.sub.2 of the part of the gate stack EG located on the active region RA and the height h.sub.1 of the part of the same gate stack EG located on the non-active region RA satisfy the relationships h.sub.2/e=a.sub.2 and h.sub.1/e=a.sub.1 where a.sub.2 is an aspect ratio such that, upon growth of the spacer material forming the spacers ES, an airgap is in the spacer ES, and a.sub.1 is an aspect ratio such that, upon growth of the spacer material forming the spacers ES, no airgap is in said spacer ES.

[0056] The notion of a limit aspect ratio is illustrated in [FIG. 2A] and [FIG. 2B]. The structure represented in [FIG. 2A] has an aspect ratio h.sub.1/e equal to the aspect ratio a.sub.2 and an airgap VO therefore forms in the spacers ES. In contrast, the structure represented in [FIG. 2B] has an aspect ratio h.sub.1/e equal to the aspect ratio a.sub.1 and no airgap VO therefore forms in the spacers ES. Thus, in the device DI according to an embodiment of the invention, each spacer ES separating one gate stack EG from the next has, at the active region RA, an airgap VO.

[0057] The aspect ratios a.sub.1 and a.sub.2 can be easily determined experimentally by depositing the material used to form the spacers ES with different values of the aspect ratio and by noting for which values of the aspect ratio an airgap VO is formed during said deposition. A graph illustrating such a determination is illustrated in [FIG. 3]. In this figure, the pairs of values (e, h) corresponding to points located in the upper zone OK enable the formation of an airgap VO. Therefore, a.sub.2 can be chosen among all the aspect ratios associated with the pairs (h, e) located in this upper zone OK. In contrast, the pairs of values (e, h) corresponding to points located in the lower zone KO do not enable the formation of an airgap VO. Therefore, a.sub.1 can be chosen from all the aspect ratios associated with the pairs (h, e) located in this lower zone KO. Thus, the pair (e, h.sub.2) corresponds to a point located in the upper zone OK whereas the pair (e, h.sub.1) corresponds to a point located in the lower zone KO. In an embodiment, the aspect ratio a.sub.2 is equal to 1.5 and/or the aspect ratio a.sub.1 is equal to 1. In an embodiment a.sub.2≥1.5 and a.sub.1≤1, or even a.sub.2≥1.5 and a.sub.1≤0.9.

[0058] In an embodiment, the height h.sub.1 is between 30 and 50 nm (limits included). In an embodiment, the height h.sub.2 is between 60 and 100 nm (limits included). In an embodiment, the distance e separating two successive gate stacks EG is between 20 and 40 nm (limits included).

[0059] In an embodiment, each gate stack EG has a width (measured in the same direction as the distance e) of between 10 and 40 nm (limits included).

[0060] In an embodiment, the spacers ES are formed by a layer of spacer material, for example nitride, having a thickness t greater than or equal to 0.3×e, for example greater than or equal to 0.4×e, or even greater than or equal to 0.5×e. This ensures that sufficient spacer material is deposited to form a spacer ES comprising an airgap VO. In an embodiment, the thickness t of the layer of spacer material is between 15 and 20 nm (limits included).

[0061] In an example embodiment, the thickness of the layer of spacer material is between 15 and 20 nm (limits included), the distance e separating two successive gate stacks is between 20 and 30 nm (limits included), the height h.sub.2 is between 60 and 80 nm and the height h.sub.1 is between 30 and 40 nm. In an embodiment, the spacer material is a nitride, such as a silicon nitride.

[0062] First Manufacturing Method

[0063] A second aspect of the invention illustrated in [FIG. 4] to [FIG. 9B] relates to a method 100 for manufacturing a semiconductor device DI from a substrate (illustrated in [FIG. 5]), for example an SOI substrate, including at least one active region RA and one non-active region RN at least partially surrounding the active region RA. In addition, the surface of the active region RA is located in a first plane P1 and the surface of the non-active region is located in a second plane P2, the first plane P1 being located at a height lower than that of the second plane P2. As illustrated in [FIG. 5], the difference in height between the first plane P1 and the second plane P2 is denoted as Δh in the following.

[0064] As illustrated in [FIG. 6A] and [FIG. 6B], the method 100 comprises a step 1E1 of forming a plurality of gate stacks EG parallel to each other, each gate stack EG having a height h (higher than the height h.sub.2 introduced below) and being separated from the nearest gate stack(s) EG by a distance e.

[0065] In general, as illustrated in [FIG. 6A], a gate stack EG comprises a gate oxide OG (for example silicon oxide), a layer of metal ME on the gate oxide OG (for example titanium nitride) and a layer of polysilicon PS on the layer of metal ME. Also, the plurality of gate stacks EG can for example be obtained by depositing the different layers forming a gate stack EG, the layers being subsequently etched so as to obtain the plurality of gate stacks EG. As these steps are well known in the art, they are not detailed in the following.

[0066] As illustrated in [FIG. 7A] and [FIG. 7B], the method 100 then comprises a step 1E2 of depositing a layer of a spacer material, for example nitride, so as to form a spacer ES between each gate stack ES, the thickness t of the deposited layer for example being greater than or equal to 0.3×e. In addition, the height h of the gate stacks EG during this step 1E2 is such that h/e≥a.sub.2 where a.sub.2 is the previously introduced aspect ratio enabling the formation of airgaps VO. Also, during the deposition of the layer of a spacer material, an airgap VO is formed within the spacers ES between each gate stack EG.

[0067] As illustrated in [FIG. 8A] and [FIG. 8B], the method also comprises a step 1E3 of depositing a layer of a dielectric material OX.

[0068] As illustrated in [FIG. 9A] and [FIG. 9B], the method 100 further comprises a mechanical-chemical polishing step 1E4 such that, at the end of this step 1E4, the part of the gate stacks located on the active region has a height h.sub.2 chosen such that h.sub.2/e=a.sub.2. In an embodiment, this step is performed in two sub-steps: a first mechanical-chemical polishing sub-step so as to level the layer of dielectric material OX and then a second mechanical-chemical polishing sub-step so as to expose the top of the gate stacks EG. Obtaining a height h.sub.2 at the part of the gate stacks EG located on the active region RA implies, given the difference in height between the active region RA and the non-active region RN, that the part of the gate stacks EG at the non-active region RN has a height h.sub.2−Δh=h.sub.1. Furthermore, Δh is chosen such that h.sub.1/e=a.sub.1 where a.sub.1 is the previously introduced aspect ratio and does not enable the formation of airgaps VO.

[0069] Also, the mechanical-chemical polishing step 1E4 is implemented such that the airgaps VO formed in the spacers ES at the non-active region become exposed (cf. [FIG. 9A]) while those formed in the spacers ES at the active region RA remain (cf. [FIG. 9B]—that is, are not exposed).

[0070] In an embodiment, the method 100 then comprises a step of depositing a layer of material so as to fill the airgaps VO thus exposed. This may be a deposition of a passivation layer.

[0071] At the end of this method 100, a device according to the invention is obtained.

[0072] Second Manufacturing Method

[0073] A third aspect of the invention illustrated in [FIG. 10] to [FIG. 13B] relates to a method 200 for manufacturing a semiconductor device DI from a substrate (illustrated in [FIG. 4]) having at least one active region RA and one non-active region RA at least partially surrounding the active region RA. In the method 200 according to a third aspect of the invention (as before), the surface of the active region RA is located in a first plane P1 and the surface of the non-active region RN is located in a second plane P2, the first plane P1 being located at a height lower than that of the second plane P2. In addition, as illustrated in [FIG. 4], the difference in height between the first plane P1 and the second plane P2 is denoted as Δh in the following.

[0074] As illustrated in [FIG. 11A] and [FIG. 11B], the method 200 comprises a step 2E1 of full plate depositing a layer of gate stacks EG. In an embodiment, the layer of gate stack comprises a gate oxide OG (for example, silicon oxide), a layer of metal ME on the gate oxide OG (for example, titanium nitride) and a layer of polysilicon PS on the layer of metal ME.

[0075] As illustrated in [FIG. 12A] and [FIG. 12B], the method 200 comprises a mechanical-chemical polishing step 2E2 such that the layer of gate stacks EG located on the active region RA has, at the end of this step 2E2, a thickness h.sub.2. Obtaining a thickness h.sub.2 implies, given the difference in height between the active region RA and the non-active region RN, that the layer of gate stacks EG at the non-active region RN has a thickness h.sub.2−Δh=h.sub.1.

[0076] As illustrated in [FIG. 13A] and [FIG. 13B], the method 200 comprises a step 2E3 of forming, from the layer of gate stack EG, a plurality of gate stacks EG parallel to each other, each gate stack EG being separated from the nearest gate stack(s) EG by a distance e. Thus, the part of the gate stacks located in the active region RA has a height h.sub.2 while the part of the gate stacks located in the non-active region RN has a height h.sub.1=h.sub.2−Δh. Moreover, h.sub.2 is chosen such that h.sub.2/e=a.sub.2 and Δh is chosen such that h.sub.1/e=a.sub.1 where a.sub.2 is an aspect ratio such that, upon growth of the spacer material forming the spacers ES, an airgap VO forms within said spacer ES, and a.sub.1 is an aspect ratio such that, upon growth of the spacer material forming the spacers ES, no airgap VO forms within said spacer ES.

[0077] As illustrated in [FIG. 14A] and [FIG. 14B], the method comprises a step 2E4 of depositing a layer of a spacer material, for example nitride, so as to form a spacer ES between each gate stack EG. The thickness t of the deposited layer is in an embodiment greater than or equal to 0.3×e. Furthermore, since this deposition step is performed, h.sub.1/e=a.sub.1 and h.sub.2/e=a.sub.2, an airgap VO is formed in each spacer at the part located on the active region RA.

[0078] At the end of this method 200, a device according to the invention is also obtained.