Electrostatic discharge protection devices

Abstract

A semiconductor device for electrostatic discharge (ESD) protection including a source, a gate, a drain having a drain diffusion, and a diffusion region extending from, or located under, the drain diffusion. The source, the gate, the drain and the diffusion region are located in or on a substrate. The diffusion region is laterally spaced from at least one of the gate or the outer edge of the drain diffusion.

Claims

1. A semiconductor device for electrostatic discharge (ESD) protection, comprising: a source; a gate; a drain connection comprising a silicide layer; a drain diffusion fully surrounding laterally and underneath the drain connection, wherein the drain diffusion comprises a resistive region located between an edge of the gate and an edge of the silicide layer of the drain connection; and a diffusion region extending from, or located under, the drain diffusion, the source, the gate, the drain connection and the diffusion region being located in a well region formed in or on a substrate; wherein the diffusion region is laterally spaced from at least one of the gate or an outer edge of the drain diffusion, wherein a doping concentration of the diffusion region is less than a doping concentration of the drain diffusion, and wherein the diffusion region is formed such that a thickness of the diffusion region is more than a thickness of the drain diffusion, and wherein the diffusion region is of a doping polarity opposite to a doping polarity of the drain diffusion, and wherein the diffusion region and the well region comprise a same doping type only.

2. A semiconductor device according to claim 1, wherein the gate forms a ring around the drain connection and the diffusion region.

3. A semiconductor device according to claim 2, wherein the diffusion region is spaced from all sides of the ring.

4. A semiconductor device according to claim 1, wherein the gate comprises an edge towards the diffusion region and the lateral distance between said edge and the diffusion region is between 0.1 m and 0.8 m.

5. A semiconductor device according to claim 1, wherein said drain connection is laterally separated from an edge of the gate towards the drain connection by the resistive region.

6. A semiconductor device according to claim 5, wherein the distance between the edge of the gate and the drain connection is between 2 m and 3 m.

7. A semiconductor device according to claim 1, wherein, at the surface of the device, a silicide blocking layer is formed between the drain connection and the gate.

8. A semiconductor device according to claim 7, wherein the silicide blocking layer forms a ring around the drain connection and the diffusion region.

9. A semiconductor device according to claim 8, wherein the ring overlaps with a portion of the gate towards the drain connection and with an active area adjacent the drain connection.

10. A semiconductor device according to claim 1, wherein the diffusion region is formed under a central portion of the drain diffusion but not under the edges of the drain diffusion.

11. A semiconductor device according to claim 1, further comprising a semiconductor body disposed in or on the substrate, wherein, at the surface of the device, the body is laterally spaced from the source.

12. A semiconductor device according to claim 11, wherein the well region excludes the body.

13. A semiconductor device according to claim 11, further comprising an additional diffusion region extending from, or located under, the body.

14. A semiconductor device according to claim 13, wherein the additional diffusion region is laterally spaced from the diffusion region.

15. A semiconductor device according to claim 13, wherein the diffusion region and the additional diffusion region are contained in the well region formed in or on the substrate.

16. A semiconductor device according to claim 11, further comprising an additional diffusion region extending from the surface of the device towards the substrate and being formed in a region under the body, source and at least a portion of the gate.

17. A semiconductor device according to claim 16, wherein the additional diffusion region is laterally spaced from the diffusion region.

18. A semiconductor device according to claim 16, wherein the diffusion region and the additional diffusion region are contained in the well region formed in or on the substrate.

19. A semiconductor device according to claim 1, wherein the device is arranged to carry a sufficiently large current when a reverse bias voltage is applied to the drain region relative to at least one of the source or gate so as substantially not to cause permanent damage to the device.

20. A semiconductor device according to claim 1, configured such that, in an OFF-state, when a voltage of more than a first breakdown voltage is applied to the device, current conduction occurs in the device.

21. A semiconductor device according to claim 20, wherein permanent damage of the device occurs when a second breakdown voltage, which is higher than the first breakdown voltage, is applied to the device.

22. A semiconductor device according to claim 21, wherein the second breakdown voltage is sufficiently greater than the first breakdown voltage such that substantially uniform current conduction is achieved throughout the device between the first and second breakdown voltages.

23. A semiconductor device according to claim 22, wherein the second breakdown voltage results in a maximum current of about 10 mA/m.

24. An electronic circuit for electrostatic discharge protection, comprising an array of semiconductor devices wherein each semiconductor device is in accordance with claim 1.

25. An electronic circuit according to claim 24, wherein the width of the circuit is about 320 m.

26. A method of manufacturing a semiconductor device according to claim 1, wherein the device is manufactured using CMOS processing steps.

27. A semiconductor device according to claim 1, wherein a doping concentration of the diffusion region is more than a doping concentration of the well region.

28. A semiconductor device according to claim 1, further comprising a source region associated with the source, wherein the well region excludes the source region.

29. A semiconductor device according to claim 28, wherein the source region has an opposing doping type relative to the well region.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) Some embodiments of the invention will now be described by way of example only and with reference to the accompanying drawings, in which:

(2) FIG. 1 shows a simplified ESD protection circuit for an IC chip IO pad (prior art).

(3) FIG. 2 shows a sectional view of an ESD protection transistor (prior art).

(4) FIG. 3 shows a sectional view of an ESD protection transistor (prior art).

(5) FIG. 4 shows a sectional view of an ESD protection transistor according to an embodiment of the present invention.

(6) FIG. 5 shows a sectional view of an ESD protection transistor according to an embodiment of the present invention.

(7) FIG. 6 shows a sectional view of an ESD protection transistor according to an embodiment of the present invention.

(8) FIG. 7 shows a sectional view of an ESD protection transistor according to an embodiment of the present invention.

(9) FIG. 8 shows a plan view of an ESD protection structure according to an embodiment of the present invention.

(10) FIG. 9 shows a plan view of an ESD protection structure according to an embodiment of the present invention.

(11) FIG. 10 shows a plan view of an ESD protection structure according to an embodiment of the present invention.

(12) FIG. 11 shows a plan view of an ESD protection structure according to an embodiment of the present invention.

(13) FIG. 12 shows a plan view of an ESD protection structure according to an embodiment of the present invention.

(14) FIGS. 13A and 13B show typical snapback and leakage curves for an ESD device, measured by TLP (transmission line pulse).

(15) FIG. 14 shows a sectional view of an ESD protection diode according to an embodiment of the present invention.

DETAILED DESCRIPTION

(16) A cross section of a MOSFET according to an embodiment of the invention is shown in FIG. 4. Most features of the transistor, including the transistor channel, are the same as the transistor shown in FIG. 2 and are also the same as any standard NMOS used on the rest of the IC. The same reference signs as in FIG. 2 are used, to denote corresponding features. The MOSFET of FIG. 4 is again provided with a doped p-well 2, in or on which the drain, gate, source and body contacts are formed. The electrical switching behavior of the ESD protection transistor of FIG. 4 will be the same as the rest of the NMOS components on the IC. Off-state current and on-state drive capability are maintained. Also the breakdown voltage of the drain junction immediately at the channel edge, under the gate 9, 13 is the same as a standard NMOS. Within (or under) the region used as an ESD ballast resistor 20 and drain connection a deeply implanted region 16 is provided, which the FIG. 2 prior art does not have. Region 16 is a fairly lightly doped p-type region contained within p-well 2. It is offset from the edge of the gate 9, 13 by a small distance labelled e in FIG. 4. Another way of describing it is by saying that it is offset from an outer edge of the drain diffusion 20, or from an outer edge of the active area associated with the drain.

(17) In experiments by the present inventor, doping levels of about 9e12/cm2 (boron, 200 keV) up to 9e13/cm2 have been used for the p-doped region 16. The net doping of the silicon region is about 1e17 atoms/cm3 up to 5e18 atoms/cm3typically about 1.3e18 atoms/cm3 with a junction diffused depth of about 1 um, although depths of about 2 um, or between 0.1 um and 10 um are also possible.

(18) In experiments by the present inventor, the conditions were adjusted so that the value of e was from about 0.1 um to about 1.4 um, with 0.4 um being a typical value for e.

(19) This extra p-type doping (i.e. region 16) reduces the breakdown voltage of the diode vertically under the drain diffusion, but only within the central regions of the drain junction. It does not (significantly) alter the breakdown voltage at the outer edges of the n+ diffusion 20, which remain at, or close to, their original higher value. Thus ESD surge currents tend to conduct, in one case, into the central part of the drain diode into the p-type region 16 beneath because the conduction starts at the point where breakdown begins, i.e. where the junction has its lowest breakdown voltage. Thus the high current tends to be kept away from the sensitive transistor channel regions, where the transistor is vulnerable, so that the least damage is done. The point of breakdown occurs within a large, robust diode area rather than at transistor edges.

(20) The p-type zone 16 may be created using a standard process implant without the need to add a special ESD implant layer. This may save cost and complexity. The implanting of a p-type implant 17 (see FIG. 8-10) which is already used in the process to suppress the parasitic NMOS field leakage at the outer edges of the active area, under the field oxide 11, could be used to implant within the drain connection zone of the active area to form the drain p-type region 16. Some processes have more than one p-well already, for example if they offer different voltage CMOS on the same IC. In those cases a simple re-use of an existing implant minimizes the additional cost to make the improved ESD protection components.

(21) Due to the diffused depth of the p-type zone 16 the vertical series resistance into the drain diode is reduced. This is an advantage compared to shallow p-type implanted regions. A deeper p-type region is beneficial for lower series resistance because it acts as a vertical sinker diffused connection into the p-substrate.

(22) According to certain embodiments the transistor stripe layout is modified to address the problem of extreme edge structures on the outer periphery. FIG. 9 shows a plan view of the modified transistor design, which should be compared to the transistor layout of FIG. 8. At the outer device periphery the gate layer 9 of FIG. 9 overlaps the active area so that it surrounds the drain connections D. The gate layer 9 is formed as a ring. The silicide block layer 7 is similarly arranged as a concentric ringsee FIGS. 9 and 10. Note that FIGS. 9 and 10 show the same device, but the silicide block layer 7 is shown in the foreground in FIG. 10, whereas in FIG. 9 only its edge is indicated. The silicide block layer 7 overlaps the gate over an outer portion (of the silicide block layer 7) and the drain junction active area over an inner portion (of the silicide block layer 7). This layout style aims to ensure that the breakdown voltage of the diode is uniformly the same for the entire central part 16 and not weaker at the edges.

(23) The stripe layout style as shown in FIG. 9 can be repeated many times and stretched in transistor width to make a suitably large ESD protection designed component.

(24) In FIG. 9, the p-type zone 16 is laterally offset from the ring-shaped gate 9 on all sides.

(25) In FIG. 8, the gate is not formed as a ring but as two stripes. The top and bottom edges (according to the orientation of the device as per FIG. 8) of the p-type zone 16 are again laterally offset from the gate 9. No portion of the gate extends along the remaining two edges of the p-type zone 16. However, at those two remaining edges (and also at the top and bottom edges, i.e. at all edges) the p-type zone 16 is offset from an outer edge of the active area of the device, or from an outer edge of drain diffusion 20.

(26) Relevant portions of the outer edge of the active area of the device are shown in FIGS. 11 and 12, whereby FIG. 11 corresponds to FIG. 8, and FIG. 12 corresponds to FIG. 9. The outer edge of the active area is represented by dashed line 22, at the inside edge of field oxide 11. As described above, ring shaped gate 9 covers the active area outer edge 22 in FIG. 12. In FIG. 11 the gate is provided as two parallel strips, and these do not cover dashed line 22. In both FIGS. 11 and 12 the p-type zone 16 is spaced from (or laterally offset from) the active area outer edge 22.

(27) The capacitance of the transistor is not severely compromised according to embodiments of the invention, because the doping level under the diffused n+ junction 20 remains fairly lightly p-type doped. The capacitance of the junction is dominated by the edges of the diffused part 20 where it meets the active area edge and also the edges where it meets the transistor channel at the gate edges. This is substantially unchanged by the addition of the inset p-type region 16. There is only a very small capacitance increase to the central part of the diode compared to a diode where the p-well 16 is absent. This central capacitance makes only a small contribution to the total capacitance of the junction. Hence the parasitic capacitance of the transistor extrinsic diode is only very slightly more than a standard NMOS. Diode reverse bias leakage is likewise approximately the same as an NMOS without the inset p-type doping 16, because it is dominated by the leakage around the edges of the n+ diffusion 20, with only a small contribution from the internal, middle part of the diode.

(28) Transistor off-state leakage is not (or not significantly) impacted because the extra p-type implant 16 under the drain diffusion 20 is offset from the gate edge so it has no (significant) effect on the transistor channel region.

(29) The ballast resistor is not (or not significantly) impacted because the lightly doped p-type 16 has only a negligible effect on the resistance of the heavily doped n+ diffusion 20. Hence the drive capability of the transistor on-state is not (significantly) changed by the inclusion of the p-type region 16. According to some embodiments, from an electrical circuit point of view, a ballast resistor in the drain is the only difference compared to a standard NMOS design as shown in FIG. 2. The drive current is comparable or equal to the ESD protection structure as shown in FIG. 2, and also comparable to other devices which may be made on the same IC and which do not have a p-type region implanted within the drain n+ diffusion.

(30) Other embodiments are possible. As per FIG. 5, if an extra p-type region 21 is also added to the body connection then this can further reduce the series resistance. The p-type sinker diffusion 21 reduces vertical series resistance of the body connection into the p-substrate. Lower resistances mean lower power dissipation when the ESD current flows and hence less self heatinghence less damage to the device. The maximum current carrying ability of the component can thus be increased.

(31) The additional p-type region 21 may have similar dimensions as p-type region 16 and would also normally be contained within p-well 2.

(32) In some process flows there are no special field suppression implants. In these cases there is one type of p-well (unlike in e.g. FIG. 4, where there is a large p-well 2 and, within that, a smaller p-well 16). FIG. 6 shows how the invention can still be created as a second embodiment. In that case the p-well 2B under the transistor needs to be offset by a small gap from the p-well 2A which is made under the drain n+ diffusion (this gap is labelled as sp1 in FIG. 6). The NMOS will still conduct as normal since the light p-type diffusion 2B will be depleted and inverted by the gate voltage. The inversion channel will still reach the n+ diffusion 20.

(33) In the third embodiment, FIG. 7, the feature of a small gap sp2 between p-well areas 21 and 16 is created and the deeper p-type zone 2 is also present. This embodiment may be useful e.g. in cases where the substrate doping is n-type and needs to be implanted p-type to make a functional NMOS device.

(34) FIGS. 13A and 13B show a typical transmission line pulse, TLP trace for an embodiment of the invention configured as a ggNMOS ESD protection component. TLP is a method of checking ESD equivalent operational IV curves using a fast pulsing technique with pulse times of about 100 ns. FIG. 13A represents the TLP snapback IV trace which is the pulse voltage (x-axis) versus pulse current (y-axis). FIG. 13B represents the leakage measured on the component after each pulse (x axis, log scale), plotted versus the current measured at the pulse (y-axis). The two plots are created so that the two y-axis scales are the same.

(35) Referring to FIG. 13A, the Vt1 point is the voltage where there is the first snapback breakdown in the transistor and it triggers into a conducting state in reverse bias, e.g. when an ESD event happens. Once snapback happens, the voltage drops quickly to the holding voltage, Vh and the device is then in a fully conducting state. Vh is larger than the maximum Vdd power supply voltage, so that the device does not have latchup sensitivity issues in normal circuit use. Above Vh the current increases approximately linearly; the current flows into the device uniformly. There is some heating and power dissipation but no irreversible damage, as can be observed by the straight line, low value, leakage current plot in FIG. 13B. This part of the curve represents the component operating as a (good) ESD protection device. It can conduct away the ESD pulse current in a non-destructive way, whilst maintaining a reasonably low voltage on-chip to protect the other components in the integrated circuit.

(36) A second breakdown is seen at a high current It2 and voltage Vt2, whereby Vt2>Vt1. The ESD protection device then suffers irreversible thermal and electrical damage, e.g. the device starts to melt, burn and fuse, which destroys it. Resistance becomes effectively negative (hence unstable) on the TLP curve. Beyond It2, the leakage suddenly increases on the right hand curve, indicating device damage. This It2, Vt2 point is identified as the maximum limit of operation for the component when used as an ESD protection device. Since an aim of embodiments of the invention is to better protect devices from ESD damage, the current and voltage caused by the ESD needs to be below It2, Vt2 so that the ESD pulse can be discharged without causing any device damage.

(37) Using embodiments of this invention Vt2>Vt1 can be achieved, which is a necessary condition for uniform conduction throughout the device at the point when it fails. This feature helps to maximise the ESD current capability for a given device size (i.e. number of stripes).

(38) It is the maximum ESD current which is approximately correlated with ESD HBM protection strength. Embodiments of this invention can achieve It2 values of about 10 mA/um (equivalent to >8 kV ESD HBM, human body model). Standard component styles which were made using the same CMOS technology, made the same size but without this invention only achieve about half of this ESD robustness.

(39) FIG. 14 shows a sectional view of an alternative embodiment. The ESD protection device of FIG. 14 is provided as a diode. Features of FIG. 14 having the same function as features shown in FIG. 4 carry the same reference number. Features having a similar function as features shown in FIG. 4 carry a reference number which increased by 200 when compared with FIG. 4.

(40) Comparing FIGS. 14 and 4, one will see that the drain has been replaced by the cathode of the diode, and the body contact has been replaced by the anode 205. The cathode is again provided with resistive region 220 (cathode diffusion), under which is formed the p-type region 16. This is offset or laterally spaced from an outer edge of the cathode diffusion, as indicated by distance e.

(41) The outer edges of the diode can be terminated using a polysilicon guard ring 207, which overlaps the cathode diffusion 220. Whilst not essential, the polysilicon ring 207 would normally be connected so as not to be floating.

(42) Labels used in the figures include:

(43) 1Single crystal silicon epitaxial layer; e.g. high quality, lightly doped semiconductor, e.g. p-type

(44) 2Doped p-well_1; e.g. diffused implanted semiconductor, p-type impurity

(45) 3Insulating dielectric material used between semiconductor and metal wiring layer; e.g. silicon dioxide; ILD

(46) 4Insulating dielectric material above and also between metal wiring layer(s); e.g. silicon dioxide; IMD

(47) 5Metal wiring layer; e.g. aluminium metal

(48) 6Conducting silicide layer; e.g. titanium silicide or cobalt silicide

(49) 7Insulating dielectric layer on semiconductor devices; silicide block

(50) 8Insulating dielectric layer(s) on sides of gate conductor; sidewall spacer

(51) 9Gate conductor; e.g. doped polysilicon layer (n-type for NMOS)

(52) 10Contact connection metal through ILD; e.g. tungsten metal plug

(53) 11Insulating dielectric layer; e.g. silicon dioxide; field oxide

(54) 12Doped semiconductor substrate; e.g. p+ doped single crystal silicon wafer

(55) 13Insulating dielectric layer; e.g. silicon dioxide; gate dielectric

(56) 14Shallow diffused heavily doped semiconductor region; e.g. n+ diffusion source and drain junctions of NMOS

(57) 15Shallow diffused heavily doped semiconductor region; e.g. p+ diffusion body connection of NMOS

(58) 16Diffused implanted semiconductor, p-type impurity; doped p-well_2

(59) 17Diffused implanted semiconductor, p-type impurity; field suppression implant

(60) 18Insulating dielectric material used to protect IC, e.g. silicon nitride passivation

(61) 19Deeper diffused heavily doped semiconductor region; e.g. deeper n+ diffusion used as ESD improvement implant

(62) 20Resistive region; e.g. n+ drain diffusion region

(63) 21Deeply implanted region under body connection

(64) 213Thin dielectric region between polysilicon and substrate

(65) It will be appreciated by one skilled in the art that devices according to the present invention do not necessarily have to include all features listed above. Similarly, it is not essential for all devices in the circuit to have the same features and characteristics.

(66) The above description has been made with reference to an IC. It will be apparent that the invention may also find application with discrete devices.

(67) Further, the skilled person will understand that in the preceding description and appended claims, positional terms such as above, overlap, under, lateral, vertical, etc. are made with reference to conceptual illustrations of a transistor, such as those showing standard cross-sectional perspectives and those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a transistor when in an orientation as shown in the accompanying drawings.

(68) As described above, the invention is not limited to transistors but also to suitable diodes. Further, NMOS and PMOS are not the only types of transistors suitable for use in the present invention. More generally, the invention may find application with CMOS, BiCMOS or BJT devices, or any device incorporating a diode.

(69) It will be appreciated that all doping polarities mentioned above could be reversed, the resulting devices still being in accordance with the present invention. In the case of the diode as per FIG. 14, this would normally mean that the anode is in the centre of the device, with an anode diffusion, and the additional lightly doped diffusion 16 would be formed under the anode diffusion.

(70) It will be appreciated that embodiments may provide ESD protection not only by virtue of being, or incorporating a diode, but also by virtue of the resistive elements of the device.

(71) Although the invention has been described in terms of certain embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the invention, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.