Method for forming MOS device passivation layer and MOS device

Abstract

The present invention provides a method of forming a passivation layer of a MOS device, and a MOS device. The method of forming a passivation layer of a MOS device includes: forming a substrate; forming a dielectric on the substrate; patterning the dielectric to expose a part of the substrate; forming a metal on the exposed part of the substrate, and the dielectric; forming a TEOS on the metal; forming a PSG on the TEOS; and forming a silicon nitrogen compound on the PSG. Therefore, the cracks problem of the passivation can be alleviated.

Claims

1. A method of forming a metal oxide semiconductor (MOS) device, comprising: forming a dielectric on a substrate; patterning the dielectric to expose a part of the substrate; forming a metal on the exposed part of the substrate and the dielectric; forming the passivation layer on the MOS device, forming the passivation layer including: forming a tetraethyl orthosilicate (TEOS), a phosphosilicate glass (PSG), and a silicon nitrogen compound on the metal in this order.

2. The method according to claim 1, wherein a thickness of the TEOS is in a range of from 9000 to 11000 angstroms, a thickness of the PSG is in a range from 2700 to 3300 angstroms, the silicon nitrogen compound is SiON or SiN, and a thickness of the SiON is in a range from 2700 to 3300 angstroms.

3. The method according to claim 1, wherein the MOS device is a complementary MOS (CMOS) device or a double-diffusion (DMOS) device.

4. The method according to claim 2, wherein the thickness of the TEOS is 10000 angstroms, the thickness of the PSG is 3000 angstroms, and the thickness of the SiON is 3000 angstroms.

5. The method according to claim 2, wherein the TEOS, the PSG, and the SiON or the TEOS, the PSG, and the SiN are formed by a chemical vapor deposition method.

6. A metal oxide semiconductor (MOS) device, comprising: a substrate; a dielectric formed on a part of the substrate; a metal formed on the substrate and the dielectric; and a passivation layer formed on the metal, comprising: in order, a first layer including a tetraethyl orthosilicate (TEOS); a second layer including a phosphosilicate glass (PSG); and a third layer including a silicon nitrogen compound.

7. The MOS device according to claim 6, wherein a thickness of the TEOS is in a range from 9000 to 11000 angstroms, a thickness of the PSG is in a range from 2700 to 3300 angstroms, the silicon nitrogen compound is SiON or SiN, and a thickness of the SiON is in a range from 2700 to 3300 angstroms.

8. The MOS device according to claim 6, wherein the MOS device is a complementary MOS (CMOS) device or a double-diffusion (DMOS) device.

9. The MOS device according to claim 7, wherein the thickness of the TEOS is 10000 angstroms, the thickness of the PSG is 3000 angstroms, and the thickness of the SiON is 3000 angstroms.

10. The MOS device according to claim 7, wherein the TEOS, the PSG, and the SiON or the TEOS, the PSG, and the SiN are formed by a chemical vapor deposition method.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic view of structure of a DMOS product in accordance with prior art;

(2) FIG. 2 is a flow chart of a method for forming of a MOS device passivation layer according to an exemplary embodiment of the present invention; and

(3) FIG. 3 is a schematic view of structure of the MOS device according to an exemplary embodiment of the present invention.

DETAILED DESCRIPTION

(4) The following clearly describes the preferred embodiments of the present invention with reference to the accompanying drawings. The use of the same reference numbers in different instances in the figures indicate identical elements.

(5) FIG. 2 is a flow chart of a method of forming a passivation layer of a MOS device a according to an exemplary embodiment of the present invention. As shown in the figure, the method includes steps as follows:

(6) S1, a substrate is formed. The substrate can be a mono-crystalline silicon with a crystal orientation of <100> and a resistance of 1525 ohms.

(7) S2, a dielectric is formed on the substrate. The dielectric can be oxide layer, for example, an oxide silicon layer.

(8) S3, the dielectric is patterned to expose a part of the substrate.

(9) S4, a metal is formed on the exposed part of the substrate, and the dielectric. The metal can be aluminum, for example.

(10) S5, a TEOS (tetraethyl orthosilicate) is formed on the metal. Preferably, the thickness of the TEOS is 9000 to 11000 angstroms, and more preferably, the thickness of the TEOS is 10000 angstroms.

(11) S6, a PSG (phosphosilicate glass) is formed on the TEOS. Preferably, the thickness of the PSG is 2700 to 3300 angstroms, and more preferably, the thickness of the PSG is 3000 angstroms.

(12) S7, a silicon nitrogen compound is formed on the PSG. Preferably, the thickness of the silicon nitrogen compound (SiON) is 2700 to 3300 angstroms, and more preferably, the thickness of the silicon nitrogen compound (SiON) is 3000 angstroms. In addition, the SiON can be substituted by SiN.

(13) Preferably, the TEOS, the PSG, and the SiON are formed by a chemical vapor deposition method.

(14) Preferably, above-described MOS device is a CMOS (Complementary Metal Oxide Semiconductor) device or a DMOS device.

(15) FIG. 3 is a schematic view of structure of the MOS device according to an embodiment of the present invention. The silicon nitrogen compound in the process of forming the passivation layer can be SiON or SiN and so on. SiON is illustrated as a silicon nitrogen compound in the following embodiment for example, as shown in the figure, the MOS device includes a substrate 1, a dielectric 2 formed on a part of the substrate 1, a metal 3 formed on the substrate 1 and the dielectric 2, and a passivation layer 4 formed on the metal 3. The passivation layer 4 includes:

(16) a TEOS 41 formed on the metal 3;

(17) a PSG 42 formed on the TEOS 41; and

(18) a SiON 43 formed on the PSG 42.

(19) Preferably, the thickness of the TEOS 41 is 9000 to 11000 angstroms, the thickness of the PSG 42 is 2700 to 3300 angstroms, and the thickness of the SiON 43 is 2700 to 3000 angstroms.

(20) More preferably, the thickness of the TEOS 41 is 10000 angstroms, the thickness of the PSG 42 is 3000 angstroms, and the thickness of the SiON 43 is 3000 angstroms.

(21) Preferably, the TEOS 41, the PSG 42, and the SiON 43 are formed by a chemical vapor deposition method.

(22) Preferably, above-described MOS device is a CMOS device or a DMOS device.

(23) In view of these teachings, a technical person skilled in the art can readily envisage of other embodiments of the present invention, combinations and modifications. Accordingly, when reading combined with the foregoing description and accompanying drawings, the present invention is only defined by the claims.