Semiconductor structure with silicon-on-insulator substrate and the manufacturing method thereof

Abstract

The invention provides a semiconductor structure comprising a silicon-on-insulator (SOI) substrate, which comprises a silicon layer and an insulating layer stacked from bottom to top, a phosphosilicate glass (PGS) on the insulating layer, and a fluorosilicate glass (FSG) on the phosphosilicate glass. The probability of ions infiltrating into the transistor can be reduced and the yield of products can be improved.

Claims

1. A semiconductor structure comprising a silicon-on-insulator (SOI) substrate, comprising: a silicon-on-insulator substrate, which comprises a silicon layer and an insulator layer stacked from bottom to top; a phosphosilicate glass (PGS) located on the insulating layer; and a fluorosilicate glass (FSG) located on the phosphosilicate glass.

2. The semiconductor structure comprising a silicon-on-insulator substrate according to claim 1, wherein a thickness of the phosphosilicate glass is smaller than a thickness of the fluorosilicate glass.

3. The semiconductor structure comprising a silicon-on-insulator substrate according to claim 1, wherein the insulating layer comprises a silicon oxide layer and a silicon oxynitride layer stacked from bottom to top.

4. The semiconductor structure comprising a silicon-on-insulator substrate according to claim 3, wherein the phosphosilicate glass directly contacts the silicon oxynitride layer.

5. The semiconductor structure comprising a silicon-on-insulator substrate according to claim 1, further comprising a transistor located under the silicon layer.

6. The semiconductor structure comprising a silicon-on-insulator substrate according to claim 5, wherein the transistor comprises a source region and a drain region located in the silicon layer, and a gate located under the silicon layer.

7. The semiconductor structure comprising a silicon-on-insulator substrate according to claim 6, further comprising a dielectric layer located under the silicon layer.

8. The semiconductor structure comprising a silicon-on-insulator substrate according to claim 7, further comprising a plurality of contact structures located in the dielectric layer and electrically connecting the source region and the drain region.

9. A method for forming a semiconductor structure including a silicon-on-insulator (SOI) substrate, comprising: providing a silicon-on-insulator substrate, wherein the silicon-on-insulator substrate comprises a silicon layer and an insulating layer stacked from bottom to top; forming a phosphosilicate glass (PGS) on the insulating layer; and forming a fluorosilicate glass (FSG) on the phosphosilicate glass.

10. The method for forming a semiconductor structure including a silicon-on-insulator substrate according to claim 9, wherein a thickness of the phosphosilicate glass is smaller than a thickness of the fluorosilicate glass.

11. The method for forming a semiconductor structure including a silicon-on-insulator substrate according to claim 9, wherein the insulator comprises a silicon oxide layer and a silicon oxynitride layer stacked from bottom to top.

12. The method for forming a semiconductor structure including a silicon-on-insulator substrate according to claim 11, wherein the phosphosilicate glass directly contacts the silicon oxynitride layer.

13. The method for forming a semiconductor structure including a silicon-on-insulator substrate according to claim 9, further comprising forming a transistor under the silicon layer.

14. The method for forming a semiconductor structure including a silicon-on-insulator substrate according to claim 13, wherein the transistor comprises a source region and a drain region located in the silicon layer, and a gate electrode located below the silicon layer.

15. The method for forming a semiconductor structure including a silicon-on-insulator substrate according to claim 14, further comprising forming a dielectric layer under the silicon layer.

16. The method for forming a semiconductor structure including a silicon-on-insulator substrate according to claim 15, further comprising forming a plurality of contact structures located in the dielectric layer and electrically connecting the source region and the drain region.

17. The method for forming a semiconductor structure including a silicon-on-insulator substrate according to claim 9, wherein after the fluorosilicate glass is formed, the method further comprises performing a planarization step to the fluorosilicate glass.

18. The method for forming a semiconductor structure including a silicon-on-insulator substrate according to claim 17, wherein during the planarization step, a plurality of ions are diffused into the fluorosilicate glass from a polishing solution in the planarization step and blocked by the phosphosilicate glass.

19. The method for forming a semiconductor structure including a silicon-on-insulator substrate according to claim 18, wherein the species of the plurality of ions comprise group 1A or group 2A ions.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIGS. 1-2 show a schematic cross-sectional view of a semiconductor structure including a silicon-on-insulator (SOI) substrate according to an embodiment of the present invention.

[0009] FIG. 3 is a schematic cross-sectional view of a semiconductor structure including a silicon-on-insulator (SOI) substrate according to another embodiment of the invention.

DETAILED DESCRIPTION

[0010] To provide a better understanding of the present invention to users skilled in the technology of the present invention, preferred embodiments are detailed as follows. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements to clarify the contents and the effects to be achieved.

[0011] Please note that the figures are only for illustration and the figures may not be to scale. The scale may be further modified according to different design considerations. When referring to the words up or down that describe the relationship between components in the text, it is well known in the art and should be clearly understood that these words refer to relative positions that can be inverted to obtain a similar structure, and these structures should therefore not be precluded from the scope of the claims in the present invention.

[0012] FIG. 1 shows a schematic cross-sectional view of a semiconductor structure including a silicon-on-insulator (SOI) substrate according to an embodiment of the present invention. As shown in FIG. 1, a substrate 10 is provided. The substrate 10 is a silicon-on-insulator (SOI) substrate, which includes a silicon layer 10A located on an insulating layer, the material of the silicon layer 10A is silicon, and the material of the insulating layer is silicon oxide, silicon nitride or silicon oxynitride, for example. In this embodiment, the insulating layer is a composite layer including a silicon oxide layer 10B on a silicon oxynitride layer 10C, but the present invention is not limited to this. Next, a transistor T is formed on the silicon layer 10A, the transistor T includes a gate G, a source region S and a drain region D. More specifically, a well region 12, the source region S, the drain region D and lightly doped drains LDD are formed in the silicon layer 10A by doping, and shallow trench isolation STI is formed outside the source region S and the drain region D. In addition, in this embodiment, if the transistor is an N-type transistor, the source region S, the drain region D and the lightly doped drain LDD are doped with N-type ions, while the well region 12 is doped with P-type ions. But the present invention is not limited thereto. The material of shallow trench isolation STI is, for example, silicon oxide, which is the same as that of silicon oxide layer 10B (the interface between them is indicated by dotted line in FIG. 1).

[0013] On the silicon layer 10A, multi-layer structures can be included, which include multi-layer dielectric layers, and the dielectric layers can also include multiple devices, such as the gate of transistors, contact structures or wire structures. More specifically, the dielectric layer 14, the dielectric layer 16 and the dielectric layer 18 are located on the silicon layer 10A, and the materials of the dielectric layers 14, 16 and 18 are, for example, silicon oxide, silicon nitride, silicon oxynitride, ultra-low dielectric constant material (ULK), low-k material, fluorosilicate glass (FSG), etc. The present invention is not limited to this. Spacers 20 are formed on both sides of the gate G. Both the gate G and the spacer 20 are located in the dielectric layer 14. The material of the gate G may include polysilicon or metal, and the material of the spacer 20 is, for example, silicon oxide, silicon nitride or silicon oxynitride. In addition, the dielectric layer 14 further contains contact structures CT, which electrically connect the source region S and the drain region D. Then, the contact structures CT further connect the metal layer M1, the contact via V1 and the metal layer M2 contained in the upper dielectric layers 16 and 18, and these metal layers and contact vias are used to connect the transistor T to other devices, such as various active or passive devices formed subsequently, or to other chips by means of hybrid bond.

[0014] It is worth noting that other dielectric layers or metal layers and other elements can be continuously formed above the metal layer M2. Most of the transistor structures and other elements described in FIG. 1 are known in the art, so the parts not detailed herein can refer to the conventional transistor structures or related elements, and the details are not repeated here.

[0015] As shown in FIG. 1, the semiconductor structure shown in FIG. 1 is defined as a front surface and a back surface, the front surface is the surface on which the transistor T and the metal layers M1 and M2 are formed, and the back surface is the bottom of the substrate 10, that is, the surface exposed by the silicon oxynitride layer 10C. As mentioned above, in the following steps, the front surface of the semiconductor structure may be connected to other components or connected to other chips by means of hybrid bond. Subsequently, in order to effectively improve the density of the semiconductor structure, the bonded wafer is turned over, that is, some other elements, such as inductor or various metal circuits, are formed on the back of the semiconductor structure.

[0016] As shown in FIG. 2, the semiconductor structure shown in FIG. 1 is inverted (the back surface of the inverted semiconductor structure is upward and the front surface is downward), and a fluorosilicate glass (FSG) 22 is formed on the silicon oxynitride layer 10C. The fluorosilicate glass 22 can be used as the material of the first dielectric layer on the back surface of the semiconductor, that is to say, other elements such as wires can be formed in the fluorosilicate glass 22, which are not shown here for the sake of simplicity. In this embodiment, the fluorosilicate glass 22 is located on the back surface of the SOI substrate 10 of a semiconductor structure, that is, the fluorosilicate glass 22 is in direct contact with the silicon oxynitride layer 10C of the SOI substrate 10. In this embodiment, the thickness of the fluorosilicate glass 22 is about 3500 angstroms, but it is not limited to this.

[0017] It is worth noting that in other embodiments, the SOI substrate may also include a three-layer stacked structure of a silicon layer, an insulating layer and a silicon layer, and after the components on the front surface of the SOI substrate are formed, the SOI substrate is turned over to the back surface, and then the topmost silicon layer after turned (i.e., the original bottom silicon layer) is removed by a planarization step, so that the middle insulating layer (i.e., the silicon oxide layer 10B) is exposed before forming the silicon oxynitride layer 10C. That is to say, the silicon oxynitride layer 10C is formed on the silicon oxide layer 10B after the back surface process, rather than at the beginning. This implementation step is also within the scope of the present invention.

[0018] Next, the back surface component processes are carried out, such as forming components or wires and carrying out planarization steps. However, the applicant found that the planarization step is, for example, chemical mechanical polishing (CMP), in which the polishing solution contains ions that easily penetrate through the fluorosilicate glass 22. For example, the polishing solution used in this example contains potassium ions (K+), which is used as a dispersant in the polishing solution to avoid particle agglomeration, and potassium ions easily penetrate through the fluorosilicate glass 22. It can Be understood that other kinds of polishing solutions can be used in the present invention, and other polishing solutions may contain, for example, 1A group ions: lithium (Li), sodium (Na), potassium (K), rubidium (Rb), cesium (Cs), thulium (Fr) or 2A group ions: beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), radium (Ra), etc. If the first dielectric layer on the back surface of the SOI substrate 10 is the fluorosilicate glass 22, the group 1A ions or the group 2A ions will easily penetrate through the fluorosilicate glass 22 during the chemical mechanical polishing of the back surface, and then penetrate into the channel region of the transistor T and affect the electrical properties of the transistor. Especially when a back gate is not formed on the back surface of the semiconductor structure, the ions infiltrated because there is no back gate barrier will affect the electrical properties of the transistor.

[0019] Therefore, in order to solve the problem that the above ions penetrate through the fluorosilicate glass and affect the electrical properties, please refer to FIG. 3, which shows a schematic cross-sectional view of a semiconductor structure including a silicon-on-insulator (SOI) substrate according to another embodiment of the present invention. Most of the elements in FIG. 3 are the same as those in FIG. 2, so the details are not repeated here. However, unlike the structure in FIG. 2, a phosphosilicate glass (PGS)24 is further included between the silicon oxynitride layer 10C and the fluorosilicate glass 22, the thickness of the phosphosilicate glass 24 in this embodiment is about 1000 angstroms, and the thickness of the fluorosilicate glass 22 is about 2500 angstroms. Therefore, the total thickness of the phosphosilicate glass 24 and the fluorosilicate glass 22 is about 3,500 angstroms, which is approximately equivalent to the thickness of the fluorosilicate glass 22 in the above-mentioned FIG. 2.

[0020] In this embodiment, the function of phosphosilicate glass 24 is to collect and block potassium ions. More specifically, phosphosilicate glass 24 contains phosphorus trioxide (P.sub.2O.sub.3), which is easy to combine with potassium ions to form K.sub.2P.sub.2O.sub.3, so as to prevent potassium ions from penetrating through fluorosilicate glass 22. Therefore, in this embodiment, a phosphosilicate glass 24 is further formed between the fluorosilicate glass 22 and the silicon oxynitride layer 10C, which can reduce the probability that potassium ions in the semiconductor structure will penetrate into the channel region of the transistor during the chemical mechanical polishing, and further improve the quality of the whole device.

[0021] Based on the above description and drawings, the present invention provides a semiconductor structure including a silicon-on-insulator (SOI) substrate, which includes a silicon layer 10A and an insulating layer (a silicon oxide layer 10B and a silicon oxynitride layer 10C) stacked from bottom to top, a phosphosilicate glass (PGS)24 located on the insulating layer, and a fluorosilicate glass (FSG)22 located on phosphosilicate glass 24 (see FIG. 3).

[0022] The invention further provides a method for forming a semiconductor structure comprising a silicon-on-insulator (SOI) substrate, which comprises providing a silicon-on-insulator substrate 10, wherein the silicon-on-insulator substrate 10 comprises a silicon layer 10A and an insulating layer (a silicon oxide layer 10B and a silicon oxynitride layer 10C) stacked from bottom to top, a phosphosilicate glass (PGS)24 is formed and located on the insulating layer, and a fluorosilicate glass (FSG)22 is formed and located on the phosphosilicate glass 24 (see FIG. 3).

[0023] In some embodiments of the present invention, a thickness of the phosphosilicate glass 24 is less than a thickness of the fluorosilicate glass 22 (for example, 1000 angstroms and 2500 angstroms, respectively).

[0024] In some embodiments of the present invention, the insulating layer includes a silicon oxide layer 10B and a silicon oxynitride layer 10C stacked from bottom to top (as shown in FIG. 3).

[0025] In some embodiments of the present invention, the phosphosilicate glass 24 directly contacts the silicon oxynitride layer 10C.

[0026] In some embodiments of the present invention, a transistor T is further included, which is located under the silicon layer 10A.

[0027] In some embodiments of the present invention, the transistor T includes a source region S and a drain region D located in the silicon layer 10A, and a gate G located under the silicon layer 10A.

[0028] In some embodiments of the present invention, a dielectric layer 14 is further included under the silicon layer 10A.

[0029] In some embodiments of the present invention, a plurality of contact structures CT are further included, which are located in the dielectric layer 14 and electrically connected to the source region S and the drain region D.

[0030] In some embodiments of the present invention, after the fluorosilicate glass 22 is formed, a planarization step (such as a chemical mechanical polishing step) is further performed.

[0031] In some embodiments of the present invention, during the planarization step, a plurality of ions (e.g., potassium ions) are diffused into the fluorosilicate glass 22 from a polishing solution in the planarization step, and the ions are blocked by the phosphosilicate glass 24.

[0032] In some embodiments of the present invention, the species of the plurality of ions include group 1A or group 2A ions.

[0033] The present invention is characterized in that the applicant found that if only fluorosilicate glass is formed on the back surface of the SOI substrate, when the back surface planarization step is carried out, ions contained in the polishing solution will easily penetrate into the doped region of the transistor, thus affecting the electrical properties of the transistor. Therefore, in addition to forming fluorosilicate glass, a phosphosilicate glass is additionally formed between the SOI substrate and the fluorosilicate glass, the phosphorus ions contained in the phosphosilicate glass is good at grasping 1A or 2A ions (e.g., potassium ions) in the polishing solution, so that the probability of ions infiltrating into the transistor can be reduced and the yield of products can be improved.

[0034] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.