METHOD FOR FABRICATING A FLASH MEMORY

Abstract

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a dielectric stack is formed on the substrate, in which the dielectric stack includes a first silicon oxide layer and a first silicon nitride layer. Next, the dielectric stack is patterned, part of the first silicon nitride layer is removed to form two recesses under two ends of the first silicon nitride layer, second silicon oxide layers are formed in the two recesses, a spacer is formed on the second silicon oxide layers, and third silicon oxide layers are formed adjacent to the second silicon oxide layers.

Claims

1. A method for fabricating semiconductor device, comprising: providing a substrate; forming a dielectric stack on the substrate, wherein the dielectric stack comprises a first silicon oxide layer and a first silicon nitride layer; patterning the dielectric stack; removing part of the first silicon nitride layer for forming two recesses under two ends of the first silicon nitride layer; forming second silicon oxide layers in the two recesses; forming a spacer on the second silicon oxide layers; and forming third silicon oxide layers adjacent to the second silicon oxide layers.

2. The method of claim 1, further comprising: forming a patterned resist on the dielectric stack; using the patterned resist as mask to pattern the dielectric stack by removing part of the first silicon nitride layer; performing a dry etching process to remove the first silicon oxide layer not covered by the first silicon nitride layer; performing a wet etching process to remove part of the silicon oxide layer under the first silicon nitride layer for forming the two recesses under two ends of the first silicon nitride layer; and stripping the patterned resist.

3. The method of claim 1, further comprising performing an n-type implantation process after forming the second silicon oxide layers for forming a buried n+ region in the substrate.

4. The method of claim 1, further comprising: forming a second silicon nitride layer on the substrate, the second silicon oxide layers, and the first silicon nitride layer; and removing part of the second silicon nitride layer for forming the spacer on the second silicon oxide layers and in the two recesses.

5. The method of claim 4, wherein the spacer comprises an L-shape and a reverse L-shape.

6. The method of claim 1, wherein the thickness of the third silicon oxide layers is greater than the thickness of the second silicon oxide layers.

7. The method of claim 1, further comprising: removing the first silicon nitride layer and the spacer after forming the third silicon oxide layers; removing the second silicon oxide layers; and forming a first tunnel oxide layer and a second tunnel oxide layer between the third silicon oxide layers and the first silicon oxide layer.

8. The method of claim 7, wherein the thickness of the third silicon oxide layers is greater than the thicknesses of the first tunnel oxide layer and the second tunnel oxide layer.

9. The method of claim 7, wherein the thickness of the first silicon oxide layer is greater than the thicknesses of the first tunnel oxide layer and the second tunnel oxide layer.

10. The method of claim 7, further comprising: forming a floating gate on the first tunnel oxide layer, the second tunnel oxide layer, the third silicon oxide layers, and the first silicon oxide layer, an oxide-nitride-oxide (ONO) stack on the floating gate, and a control gate on the ONO stack; forming a select gate adjacent to the first tunnel oxide layer; and forming a drain region adjacent to the select gate and a source region adjacent to the third silicon oxide layers.

11. A method for operating memory cell, wherein the memory cell comprises a floating gate on a substrate, a patterned oxide-nitride-oxide (ONO) stack on the floating gate, a control gate on the ONO stack, a first tunnel oxide layer and a second tunnel oxide layer between the floating gate and the substrate, a select gate adjacent to the first tunnel oxide layer, a drain region adjacent to the select gate, and a source region adjacent to the second tunnel oxide layer, the method comprising: during a program operation further comprises: applying a first voltage to the drain region; applying a second voltage to the select gate, wherein the second voltage being higher than the first voltage; and applying zero voltage to the control gate so that electrons are stored from the first tunnel oxide layer to the floating gate; during an erase operation further comprises: applying zero voltage to the select gate while the drain region remains floating; and applying a third voltage to the control gate so that electrons are released from the second tunnel oxide layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIGS. 1-7 illustrate a method for fabricating semiconductor device according to a preferred embodiment of the present invention.

DETAILED DESCRIPTION

[0012] Referring to FIGS. 1-7, FIGS. 1-7 illustrate a method for fabricating semiconductor device according to a preferred embodiment of the present invention. As shown in FIG. 1, a substrate 12, such as a substrate composed of silicon, GaAs, silicon-on-insulator (SOI) layer, epitaxial layer, silicon germanium layer, or other semiconductor material is provided, and a dielectric stack 14 is formed on the substrate 12. In this embodiment, the dielectric stack 14 preferably includes a silicon oxide layer 16 and a silicon nitride layer 18 disposed on the silicon oxide layer 16, and an optional tetraethylorthosilicate (TEOS) layer (not shown) could be formed on the silicon nitride layer 18 thereafter.

[0013] Next, a patterned resist 20 is formed on the dielectric stack 14, and an etching process is conducted to form undercut in the bottom of the silicon nitride layer 18. For instance, as shown in FIG. 2, an etching process is conducted by using the patterned resist 20 as mask to remove part of the silicon nitride layer 18 without removing any of the silicon oxide layer 16. Next, a dry etching process is conducted to remove the silicon oxide layer 16 not covered by the silicon nitride layer 18 so that the edges of the silicon oxide layer 16 are substantially aligned with the edges of the silicon nitride layer 18. A wet etching process is conducted thereafter to remove part of the silicon oxide layer 16 under the silicon nitride layer 18 for forming two recesses 22 directly under two ends of the silicon nitride layer 18. The patterned resist 20 is stripped thereafter.

[0014] Next, as shown in FIG. 3, an oxidation process is conducted to form a plurality of silicon oxide layers 24 in the two recesses 22, and an n-type implantation process is carried out to form a buried n+ region 26 in the substrate 12. Preferably, the thickness of the silicon oxide layers 24 is lower than the thickness of the previous silicon oxide layer 16.

[0015] Next, as shown in FIG. 4, another silicon nitride layer (not shown) is formed on the substrate 12, the silicon oxide layers 24, and the silicon nitride layer 18, and part of the silicon nitride layer is removed to form a spacer 28 on the silicon oxide layers 24. In this embodiment, as part of the silicon nitride layer is inserted into the two recesses 22 formed previously, the spacer 28 when viewed from left side or right side preferably includes an L-shape and a reverse L-shape.

[0016] Next, as shown in FIG. 5, another oxidation process is conducted to forma plurality of silicon oxide layers 30 adjacent to the silicon oxide layers 24, in which the thickness of the silicon oxide layers 30 is greater than the thickness of the silicon oxide layers 24.

[0017] Next, as shown in FIG. 6, after the silicon nitride layer 18 and the spacer 28 are removed to expose the silicon oxide layers 16, 24, 30 underneath, the silicon oxide layers 24 are removed, and another oxidation process is conducted to form a first tunnel oxide layer 32 and a second tunnel oxide layer 34 between the silicon oxide layers 30 and silicon oxide layer 16. Since the silicon oxide layers 24 are typically affected by ions injected into the substrate 12 during formation of the buried n+ region 26, it would be desirable to conduct another oxidation process to form new oxide layers serving as tunnel oxide layers so that the quality of electron movement during operation of memory device is ensured.

[0018] Next, a first gate layer (not shown) is covered on the first tunnel oxide layer 32, the second tunnel oxide layer 34, the silicon oxide layers 30, and the silicon oxide layer 16, an oxide-nitride-oxide (ONO) stack (not shown) is formed on the first gate layer, and a second gate layer (not shown) is formed on the ONO stack. The second gate layer, ONO stack, and first gate layer are then patterned to form a floating gate 36 on the first tunnel oxide layer 32, the second tunnel oxide layer 34, the silicon oxide layers 30, and silicon oxide layer 16, a patterned ONO stack 38 on the floating gate 36, and a control gate 40 on the ONO stack 38.

[0019] Next, as shown in FIG. 7, after forming a gate oxide layer 48 and a third gate layer (not shown) on the substrate 12, the third gate layer and the gate oxide layer 48 are patterned to form a select gate 42 adjacent to the first tunnel oxide layer 32. Next, a spacer 50 is formed around each gate structure, a drain region 44 is formed adjacent to the select gate 42 and a source region 46 is formed adjacent to the second tunnel oxide layer 34. This completes the fabrication of a flash memory according to a preferred embodiment of the present invention.

[0020] Referring again to FIG. 7, which illustrates a structural view of a semiconductor device according to an embodiment of the present invention. Preferably, the semiconductor device includes a substrate 12, a floating gate 36 on the substrate 12, a silicon oxide layer 16 and a plurality of silicon oxide layers 30 between the floating gate 36 and the substrate 12, a first tunnel oxide layer 32 and a second tunnel oxide layer 34 between the silicon oxide layer 16 and silicon oxide layers 30, a control gate 40 on the floating gate 36, a ONO stack 38 between the floating gate 36 and the control gate 40, a select gate 42 adjacent to the first tunnel oxide layer 32, a drain region 44 adjacent to the select gate 42, and a source region 46 adjacent to the second tunnel oxide layer 34. Preferably, the thickness of the first tunnel oxide layer 32 and second tunnel oxide layer 34 is less than the thickness of the silicon oxide layer 16 and silicon oxide layers 30.

[0021] According to the aforementioned memory cell structure, a method for operating memory cell is also disclosed according to an embodiment of the present invention. Preferably, the two tunnel oxide layers 32 and 34 are utilized to perform operations such as programming and erasing to improve the overall endurance of the device thereby increasing the performance and life expectancy of the device. For instance, during a program operation, a first voltage, such as 13 volts could be applied to the drain region 44, a second voltage preferably being higher than the first voltage, such as 15 volts is then applied to the select gate 42, and finally zero volts is applied to the control gate 40 so that electrons are stored from the first tunnel oxide layer 32 into the floating gate 36 to complete the program operation. During an erase operation, zero volts could be applied to the select gate 42 while the drain region 44 remains floating, and a third voltage, such as 13 volts is applied to the control gate 40 so that electrons are released from the second tunnel oxide layer 34 to complete the erase operation.

[0022] Overall, in contrast to the conventional flash memory of using single tunnel oxide layer to perform programming and erase operations, the present invention preferably forms two individual tunnel oxide layers between floating gate and substrate and uses these two separate tunnel oxide layers to carry out program and erase operations. This not only improves the operation speed of the memory cell, but also increases the endurance and life expectancy of the device.

[0023] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.