METHODS OF FORMING PACKAGED SEMICONDUCTOR DEVICES AND LEADFRAMES FOR SEMICONDUCTOR DEVICE PACKAGES
20230117260 · 2023-04-20
Inventors
Cpc classification
H01L23/3178
ELECTRICITY
H01L23/49565
ELECTRICITY
H01L23/481
ELECTRICITY
International classification
Abstract
A method of forming a packaged semiconductor device according to some embodiments includes providing a leadframe blank including a first package blank, a second package blank and a tie bar between the first package blank and the second package blank, forming a recessed cavity in the tie bar, and separating the first and second package blanks by sawing through the leadframe blank along the tie bar.
Claims
1. A method of forming a packaged semiconductor device, comprising: providing a leadframe blank including a first package blank, a second package blank and a tie bar between the first package blank and the second package blank, each package blank comprising a die attach pad and a lead, wherein the leads of the first and second package blanks are attached to the tie bar; forming a recessed cavity in the tie bar; and separating the first and second package blanks by sawing through the leadframe blank along the tie bar.
2. The method of claim 1, wherein forming the recessed cavity in the tie bar comprises etching the tie bar.
3. The method of claim 2, wherein etching the tie bar comprises etching the tie bar at the attachment point to form the recessed cavity in the tie bar at the attachment point.
4. The method of claim 2, wherein etching the tie bar at the attachment point comprises: forming a mask on the leadframe blank; forming an opening in the mask above the attachment point; and isotropically etching the leadframe through the opening in the mask.
5. The method of claim 1, wherein forming the recessed cavity in the tie bar comprises stamping or punching the leadframe blank.
6. The method of claim 1, further comprising: molding first and second package bodies onto the first and second package blanks prior to separating the first and second package blanks.
7. The method of claim 1, further comprising: mounting first and second semiconductor devices on the first and second die attach pads.
8. The method of claim 1, wherein the leadframe blank comprises a plurality of package blanks arranged in a two dimensional grid and connected to a plurality of tie bars arranged in saw streets between adjacent ones of the package blanks.
9. The method of claim 1, wherein each package blank comprises a plurality of leads attached to the tie bar at respective attachment points, the method further comprising forming a plurality of recessed cavities in the tie bar at the attachment points.
10. The method of claim 1, wherein the recessed cavity is formed on a same side of the leadframe blank as die attach surfaces of the die attach pads.
11. The method of claim 1, wherein the recessed cavity has a depth of about 25% to 75% of a thickness of the leadframe blank.
12. The method of claim 1, wherein the recessed cavity is formed in a top surface of the leadframe, the method further comprising forming a mold retention feature in a bottom surface of the leadframe opposite the top surface.
13. The method of claim 1, wherein the recessed cavity has an area greater than about 0.1 mm.sup.2.
14. The method of claim 1, wherein the recessed cavity has a width greater than about 0.3 mm.
15. A method of forming a packaged semiconductor device, comprising: providing a leadframe blank including a first package blank, a second package blank and a tie bar between the first package blank and the second package blank; forming a recessed cavity in the tie bar; and separating the first and second package blanks by sawing through the leadframe blank along the tie bar.
16. A leadframe blank, comprising: a first package blank, a second package blank and a tie bar between the first package blank and the second package blank, wherein the tie bar comprises a recessed cavity therein.
17. The leadframe blank of claim 16, wherein each package blank comprises comprising a die attach pad and a lead, wherein the leads of the first and second package blanks are attached to the tie bar at an attachment point, and wherein the recessed cavity is formed in the tie bar at the attachment point.
18. The leadframe blank of claim 16, wherein each package blank comprises a plurality of leads attached to the tie bar at respective attachment points, wherein the leadframe blank further comprises recessed cavities in the tie bar at each of the attachment points.
19. The leadframe blank of claim 16, wherein the recessed cavity is formed on a same side of the leadframe blank as die attach surfaces of the die attach pads.
20. The leadframe blank of claim 16, wherein the recessed cavity has a depth of about 25% to 75% of a thickness of the leadframe blank.
21. The leadframe blank of claim 16, wherein the recessed cavity has an area greater than about 0.1 mm.sup.2.
22. The leadframe blank of claim 16, wherein the recessed cavity has a width greater than about 0.3 mm.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0026] The accompanying drawings, which are included to provide a further understanding of the disclosure, are incorporated in and constitute a part of this specification, illustrate aspects of the disclosure and together with the detailed description serve to explain the principles of the disclosure. No attempt is made to show structural details of the disclosure in more detail than may be necessary for a fundamental understanding of the disclosure and the various ways in which it may be practiced. In the drawings:
[0027]
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[0033]
DETAILED DESCRIPTION OF THE DISCLOSURE
[0034] Embodiments of the inventive concepts are explained more fully with reference to the non-limiting aspects and examples that are described and/or illustrated in the accompanying drawings and detailed in the following description. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale, and features of some embodiments may be employed with other aspects as the skilled artisan would recognize, even if not explicitly stated herein. Descriptions of well-known components and processing techniques may be omitted so as to not unnecessarily obscure the aspects of the disclosure. The examples used herein are intended merely to facilitate an understanding of ways in which the disclosure may be practiced and to further enable those of skill in the art to practice the aspects of the disclosure. Accordingly, the examples and aspects herein should not be construed as limiting the scope of the disclosure, which is defined solely by the appended claims and applicable law. Moreover, it is noted that like reference numerals represent similar parts throughout the several views of the drawings.
[0035] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
[0036] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the another element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the another element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the another element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
[0037] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
[0038] The terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
[0039] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
[0040] As described above, DFN/QFN packages for high power applications may use leadframes having a thickness greater than 10 mils, such as 20 mils. Such packages may also have wider saw streets (i.e., the space between package blanks that a saw runs through during singulation). When thick leadframes and/or wide saw streets are used, singulating the packages using a sawing process may produce an increased level of mechanical and/or thermal stress at the contact between the metal and the saw blade. The increased stress may cause delamination or separation between the mold compound used to form the package body and the leads of the package.
[0041] Typical DFN/QFN leadless products have either bottom or top half etched designs which allows for narrow saw streets and thinner lead-frame (e.g., less than 10 mils thickness) which has less metal content in the saw street which results in low stress or reduced delamination after the sawing process. However, top or bottom half etch designs may not be suitable for power DFN packages having wider saw streets (e.g., 0.55 mm) and/or thicker leadframes (e.g., greater than 10 mils).
[0042] Accordingly, some embodiments provide methods and structures that can reduce mechanical and/or thermal stress imparted to a package during a sawing process to singulate the packages. In particular, in some embodiments, one or more recessed cavities are formed in the tie bars of a leadframe blank. Forming the recessed cavities in the tie bars of the leadframe blank may reduce the amount of metal that is removed during a sawing operation, which may reduce a level of mechanical and/or thermal stress imparted to the package during singulation. In particular embodiments, the recessed cavities may be formed at or near attachment points where the leads are attached to the tie bars to reduce stress imparted to the leads during the sawing operation.
[0043] A leadframe blank 100 according to some embodiments is shown in
[0044] During a manufacturing process, semiconductor devices are mounted onto a die attach surface 118 of the die attach pads 116 on a top or upper side 108 of the leadframe blank 100, and wire bonds are formed to connect bond pads on the semiconductor devices to leads 114 on the package blanks 112. A plurality of package bodies are then overmolded onto the package blanks 112. Individual semiconductor device packages are then singulated by sawing along the tie bars 120 to separate the packages.
[0045] As shown in
[0046] The recessed cavities 130 may have an area at the openings thereof of greater than about 0.1 mm.sup.2, and in particular embodiments greater than about 0.3 mm.sup.2. In the embodiments illustrated in
[0047] As further shown in
[0048] The recessed cavities 130 may be formed in the leadframe blank 100 by etching, stamping and/or punching. In particular, the recessed cavities may be formed using an isotropic copper etching process, such as aqueous copper etching processes known in the art, by forming a mask on the upper surface 108 of the leadframe blank 100 having openings therein above the attachment points 133 and etching the metal of the leadframe blank 100 through the openings in the mask.
[0049]
[0050] As can be seen in
[0051] In some embodiments, the mold retention features 115 may be formed in a half-etch process that etches half of the thickness from the bottom of the leadframe blank 100. This is illustrated in
[0052]
[0053] Still referring to
[0054]
[0055]
[0056]
[0057] The recessed cavity may be formed in the tie bar by etching the tie bar. In particular, etching the tie bar may include etching the tie bar at the attachment point to form the recessed cavity in the tie bar at the attachment point. In some embodiments, etching the tie bar at the attachment point includes forming a mask on the leadframe blank, forming an opening in the mask above the attachment point, and isotropically etching the leadframe through the opening in the mask.
[0058] In some embodiments, the recessed cavity may be formed in the tie bar by stamping or punching the leadframe blank.
[0059] The method may further include molding first and second package bodies onto the first and second package blanks prior to separating the first and second package blanks. The method may further include mounting first and second semiconductor devices on the first and second die attach pads.
[0060] In some embodiments, the leadframe blank comprises a plurality of package blanks arranged in a two dimensional grid and connected to a plurality of tie bars arranged in saw streets between adjacent ones of the package blanks.
[0061] Each package blank may include a plurality of leads attached to the tie bar at respective attachment points, and the method may further include forming a plurality of recessed cavities in the tie bar at the attachment points.
[0062] The recessed cavity may be formed on a same side of the leadframe blank as die attach surfaces of the die attach pads or on the opposite side of the leadframe as the die attach surfaces.
[0063] The recessed cavity may have a depth of about 25% to 75% of a thickness of the leadframe blank. The recessed cavity may have an area greater than about 0.1 mm.sup.2. In some embodiments, the recessed cavity has a width greater than about 0.3 mm.
[0064] A packaged transistor device that is formed according to some embodiments may be utilized in power semiconductor devices and/or applications. In some embodiments, the power semiconductor devices may be utilized for a power module that may include structure optimized for state-of-the-art wide band gap power semiconductor devices such as Gallium Nitride (GaN), Silicon Carbide (SiC), and the like, which are capable of carrying high amounts of currents and voltages and switching at increasingly faster speeds in comparison with established technologies. The power devices may include Wide Band Gap (WBG) semiconductors, including Gallium Nitride (GaN), Silicon Carbide (SiC), and the like, and offer numerous advantages over conventional Silicon (Si) as a material for the power devices. Nevertheless, various aspects of the disclosure may utilize Si type power devices and achieve a number of the benefits described herein.
[0065] A transistor device according to some embodiments may be utilized in radio frequency (RF) applications. In particular, a transistor device according to some embodiments may be utilized in wireless base stations that connect to a wireless device. In further aspects, the transistor device may be utilized in in wireless communication devices.
[0066] In aspects, the dimensions of z and/or d may be critical in order to address extreme temperature ranges, humidity ranges, and/or a host of other environmental conditions; operation at or near rated currents and voltages over extended periods of time; and address manufacturing issues such as insufficiently optimized wire bonding processes as well as others.