Abstract
A heterojunction device, includes a substrate (4); a Ill-nitride semiconductor region located longitudinally above or over the substrate and including a heterojunction having a two-dimensional carrier gas; first (8) and second (9) laterally spaced terminals operatively connected to the semiconductor; a gate structure (11) of first conductivity type located above or longitudinally over the semiconductor region and laterally spaced between the first and second terminals; a control gate terminal (10) operatively connected to the gate structure, a potential applied to the control gate terminal modulates and controls a current flow through the carrier gas between the terminals, the carrier gas being a second conductivity type; an injector of carriers (101) of the first conductivity type laterally spaced away from the second terminal; and a floating contact layer (102) located over the carrier gas and laterally spaced away from the second terminal and operatively connected to the injector and the semiconductor region.
Claims
1. A III-nitride semiconductor based heterojunction device, comprising: a substrate; a III-nitride semiconductor region located over the substrate, wherein the III-nitride semiconductor region comprises a heterojunction comprising at least one two-dimensional carrier gas; a first terminal operatively connected to the III-nitride semiconductor region; a second terminal operatively connected to the III-nitride semiconductor region and laterally spaced from the first terminal; a gate structure located above the III-nitride semiconductor region and laterally spaced between the first and second terminals, the gate structure being a first conductivity type; a control gate terminal operatively connected to the gate structure, wherein a potential applied to the control gate terminal modulates and controls a current flow through the two-dimensional carrier gas between the first and second terminals, the at least one two-dimensional carrier gas being a second conductivity type; and at least one floating structure of the first conductivity type located over the III-nitride semiconductor region and laterally spaced from the second terminal.
2.-22. (canceled)
23. A III-nitride semiconductor based heterojunction device according to claim 1, wherein the at least one floating structure is between the second terminal and the control gate terminal, and wherein a lateral spacing between the at least one floating structure and the control gate terminal is less than a lateral spacing between the at least one floating structure and the second terminal.
24. A III-nitride semiconductor based heterojunction device according to claim 23, wherein the at least one floating structure is configured to reduce an electric field peak around the gate structure when a high voltage is applied to the second terminal with respect to the first terminal.
25. A III-nitride semiconductor based heterojunction device according to claim 23, further comprising a floating metal layer connected to the at least one floating structure.
26. A III-nitride semiconductor based heterojunction device according to claim 23, wherein the at least one floating structure is connected under a field plate, wherein the field plate is either: connected to the first terminal or the control gate terminal; or the field plate is floating with no connection with a terminal.
27. A III-nitride semiconductor based heterojunction device according to claim 23, further comprising a plurality of floating structures laterally spaced between the gate terminal and the second terminal, wherein a lateral spacing between the floating structures and the gate terminal is less than a lateral spacing between the floating structures and the second terminal.
28. A III-nitride semiconductor based heterojunction device according to claim 23, further comprising a plurality of floating islands of the first conductivity type located in a third dimension.
29. A III-nitride semiconductor based heterojunction device according to claim 28, further comprising a floating contact layer, wherein a connection between the floating contact layer and the III-nitride semiconductor region is absent.
30. A III-nitride semiconductor based heterojunction device according to claim 28, wherein a pitch between the floating islands is selected to reduce an increase in a static on state resistance and to protect the gate structure against high electric fields.
31. A III-nitride semiconductor based heterojunction device according to claim 28, wherein the plurality of floating islands are all connected to a single floating metal layer.
32. A III-nitride semiconductor based heterojunction device according to claim 28, wherein the floating islands in the plurality of floating islands are arranged in rows, wherein each row of islands is connected to a different floating metal layer.
33. A III-nitride semiconductor based heterojunction device according to claim 32, wherein a pitch between the floating islands varies from one row to another.
34. A III-nitride semiconductor based heterojunction device according to claim 32, comprising a first row of floating islands and a second row of floating islands, wherein a pitch between floating islands in the second row is different from a pitch between floating islands in the first row.
35. A III-nitride semiconductor based heterojunction device according to claim 33, wherein the pitch between the floating islands is smallest for a row closest to the gate structure.
36. A method of manufacturing a III-nitride semiconductor based heterojunction device, the method comprising: forming a substrate; forming a III-nitride semiconductor region located over the substrate, wherein the III-nitride semiconductor region comprises a heterojunction comprising at least one two-dimensional carrier gas; forming a first terminal operatively connected to the III-nitride semiconductor region; forming a second terminal laterally spaced from the first terminal in a first dimension and operatively connected to the III-nitride semiconductor region; forming a gate terminal on a gate structure, said gate structure being positioned above the III-nitride semiconductor region; and forming at least one floating structure of the first conductivity type over the III-nitride semiconductor region and laterally spaced from the second terminal.
37. (canceled)
38. A method of manufacturing a III-nitride semiconductor based heterojunction device according to claim 36, comprising forming the at least one floating structure is between the second terminal and the control gate terminal, wherein a lateral spacing between the at least one floating structure and the gate terminal is less than a lateral spacing between the at least one floating structure of the first conductivity type and the second terminal.
39. (canceled)
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0094] The present disclosure will be understood more fully from the accompanying drawings, which however, should not be taken to limit the disclosure to the specific embodiments shown, but are for explanation and understanding only.
[0095] FIG. 1 shows schematically the cross section in the active area of a pGaN HEMT in prior art;
[0096] FIG. 2 shows schematically the cross section in the active area of a pGaN HEMT with an additional hole injector electrode driven by an external drive;
[0097] FIG. 3 illustrates a schematic representation of a cross section of the active area of the proposed disclosure according to one embodiment of the disclosure where the p-injector region is placed outside the drift region;
[0098] FIG. 4A illustrates a schematic representation of a cross section of the active area of the proposed disclosure according to one embodiment of the disclosure where all electrodes are at zero bias;
[0099] FIG. 4B illustrates a schematic representation of a cross section of the active area of the proposed disclosure according to one embodiment of the disclosure where the drain terminal is biased to a moderately high voltage (e.g. approximately 60% of nominal breakdown);
[0100] FIG. 4C illustrates a schematic representation of a cross section of the active area of the proposed disclosure according to one embodiment of the disclosure where the drain terminal is biased to a high voltage (e.g. above nominal breakdown);
[0101] FIG. 4D illustrates a schematic representation of a cross section of the active area of the proposed disclosure according to one embodiment of the disclosure where the gate and drain terminal are biased to a low positive voltage i.e. the device is in the on-state condition;
[0102] FIG. 5A illustrates a circuit schematic representation of the proposed disclosure according to one embodiment of the disclosure where all electrodes are at zero bias;
[0103] FIG. 5B illustrates a circuit schematic representation of the proposed disclosure according to one embodiment of the disclosure where the drain terminal is biased to a high voltage (e.g. above nominal breakdown);
[0104] FIG. 6A illustrates a three-dimensional schematic representation of a section of the active area of the proposed disclosure where at least one p-injector region is placed outside the drift region;
[0105] FIG. 6B shows a top view of the same section of the active area of the proposed disclosure (x, z axis). FIG. 6B shows a schematic representation of a cross section of the active area of the proposed disclosure (x, y axis) along the cutline shown in the top view;
[0106] FIG. 6C shows a top view and cross section of a variant of the structure in FIG. 6B;
[0107] FIG. 7 shows a top view (x, z axis) of a section of the active area of the proposed disclosure where at least one p-injector region is placed outside the drift region; FIG. 7 shows a schematic representation of a cross section of the active area of the proposed disclosure (x, y axis) along the cutline shown in the top view;
[0108] FIG. 8 illustrates a schematic representation of a cross section of the active area of the proposed disclosure according to a further embodiment of the disclosure where the p-injector region is placed inside the drift region;
[0109] FIG. 9A illustrates a three-dimensional schematic representation of a section of the active area of the proposed disclosure where at least one p-injector region is placed inside the drift region;
[0110] FIG. 9B shows a top view of the same section of the active area of the proposed disclosure (x, z axis). FIG. 9B shows a schematic representation of a cross section of the active area of the proposed disclosure (x, y axis) along the cutline shown in the top view;
[0111] FIG. 10 shows a top view (x, z axis) of a section of the active area of the proposed disclosure where at least one p-injector region is placed beneath the drain electrode finger metallization; FIG. 10 shows a schematic representation of a cross section of the active area of the proposed disclosure (x, y axis) along the cutline shown in the top view;
[0112] FIG. 11 shows a top view (x, z axis) of a section of the active area of the proposed disclosure where at least one p-injector region is placed beneath the drain electrode finger metallization; FIG. 11 shows a schematic representation of a cross section of the active area of the proposed disclosure (x, y axis) along the cutline shown in the top view;
[0113] FIG. 12 shows a top view (x, z axis) of a section of the active area of the proposed disclosure where at least one p-injector region is placed inside the drift region and at least one floating contact is placed beneath the drain electrode finger metallization; FIG. 12 shows a schematic representation of a cross section of the active area of the proposed disclosure (x, y axis) along the cutline shown in the top view;
[0114] FIG. 13 shows a top view (x, z axis) of a section of the active area of the proposed disclosure where at least one floating contact is placed inside the drift region and at least one p-injector region is placed beneath the drain electrode finger metallization; FIG. 13 shows a schematic representation of a cross section of the active area of the proposed disclosure (x, y axis) along the cutline shown in the top view;
[0115] FIG. 14 shows a top view (x, z axis) of an interdigitated device layout embodiment of the proposed disclosure;
[0116] FIG. 15A illustrates a schematic representation of a cross section of the active area of the proposed disclosure according to one embodiment of the disclosure where the p-injector region is placed outside the drift region;
[0117] FIG. 15B illustrates a schematic representation of a cross section of the active area of the proposed disclosure according to one embodiment of the disclosure where the p-injector region is placed outside the drift region;
[0118] FIG. 16A illustrates a schematic representation of a cross section of the active area of the proposed disclosure according to one embodiment of the disclosure where the p-injector region is placed outside the drift region;
[0119] FIG. 16B illustrates a schematic representation of a cross section of the active area of the proposed disclosure according to one embodiment of the disclosure where the p-injector region is placed outside the drift region;
[0120] FIG. 17 shows a top view (x, z axis) of an interdigitated device layout embodiment of the proposed disclosure;
[0121] FIG. 18 illustrates a schematic representation of a cross section diode according to the second aspect of the invention, where the p-injector region is placed outside the drift region;
[0122] FIG. 19 illustrates a graph showing a typical increase in on-state resistance of a GaN-on-Si HEMT device following a period of off-state stress;
[0123] FIG. 20 illustrates a Technology Computer-Aided Design (TCAD) result of the electric field peak observed for an off-state drain voltage bias of 100V;
[0124] FIG. 21 illustrates a Technology Computer-Aided Design (TCAD) result of the electric field peak observed for an off-state drain voltage bias of 400V;
[0125] FIG. 22 illustrates a Technology Computer-Aided Design (TCAD) result of the electric field peak observed for an off-state drain voltage bias of 600V;
[0126] FIG. 23 illustrates a schematic representation of a cross section of the active area of the proposed disclosure according to a further embodiment of the disclosure where the p-injector region is placed inside the drift region and the distance between the gate terminal and floating contact layer is reduced, compared to the embodiment illustrated in FIG. 8;
[0127] FIG. 24A illustrates a three dimensional schematic representation of a section of the active area of the proposed disclosure according to a further embodiment of the disclosure where at least one p-injector region is placed inside the drift region, and the distance between the gate terminal and floating contact layer is reduced, compared to the embodiment illustrated in FIG. 9A;
[0128] FIG. 24B shows a top view of the same section of the active area of the proposed disclosure (x, z axis). FIG. 24B shows a schematic representation of a cross section of the active area of the proposed disclosure (x, y axis) along the outline shown in the top view;
[0129] FIG. 25A illustrates a schematic representation of a cross section of the active area of the proposed disclosure according to a further embodiment of the disclosure where the p-injector region is placed inside the drift region and the distance between the gate terminal and floating contact layer is reduced, compared to the embodiment illustrated in FIGS. 8 and 23, and where the floating ohmic contact and p-injector region are placed under the field plate which is at source potential;
[0130] FIG. 25B illustrates a schematic representation of a cross section of the active area of the proposed disclosure according to a further embodiment of the disclosure where the p-injector region is placed inside the drift region and the distance between the gate terminal and floating contact layer is reduced, compared to the embodiment illustrated in FIGS. 8 and 23, and where an additional p-region is placed between the floating contact layer and the drain terminal;
[0131] FIG. 26A illustrates a schematic representation of a cross section of the active area of the proposed disclosure according to a further embodiment of the disclosure where the floating contact layer and the p-injector region are separated along the gate-drain axis and connected with metal interconnect;
[0132] FIG. 26B shows a top view (x, z axis) of a section of the active area according to a further embodiment of the disclosure, wherein the floating contact is placed between the gate terminal and the p-injector region islands;
[0133] FIG. 27 illustrates a schematic representation of a cross section of a further embodiment of the proposed invention comprising a floating p-type doped region, optionally with a floating metal contact;
[0134] FIG. 28 illustrates a top view (x, z axis) of a section of the active area according to an embodiment of the proposed disclosure wherein the floating p-doped region comprises islands separated in the third dimension, and further shows a schematic representation of a cross section of the active area along a outline shown in the top view;
[0135] FIG. 29 illustrates a schematic representation of a cross section of a further embodiment of the proposed invention comprising a second row of a floating p-type doped region and a second metal contact;
[0136] FIG. 30 illustrates a top view (x, z axis) of a section of the active area according to an embodiment of the proposed disclosure wherein the second floating p-doped region comprises islands separated in the third dimension;
[0137] FIG. 31 illustrates a schematic representation of a cross section of a further embodiment of the proposed invention comprising a third row of a floating p-type doped region and a third metal contact;
[0138] FIG. 32 illustrates a top view (x, z axis) of a section of the active area according to an embodiment of the proposed disclosure wherein the third floating p-doped region comprises islands separated in the third dimension;
[0139] FIG. 33 illustrates a schematic representation of a cross section of a further embodiment of the proposed invention, wherein the floating metal contact is connected to the potential of a floating metal field plate;
[0140] FIG. 34 illustrates a schematic representation of a cross section of a further embodiment of the proposed invention, wherein the p-doping field plate structure and the floating metal contact/p-injector region are used in combination the same device.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0141] FIG. 3 illustrates a schematic representation of a cross section of the active area of the proposed disclosure according to one embodiment of the disclosure where the p-injector region 101 is placed outside the drift region. In use, the current flows in the active area of the semiconductor device. In this embodiment, the device comprises a semiconductor (e.g. silicon) substrate 4 defining a major (horizontal) surface at the bottom of the device. Below the substrate 4 there is a substrate terminal 5. The device includes a first region of a transition layer 3 on top of the semiconductor substrate 4. The transition layer 3 comprises a combination of III-V semiconductor materials acting as an intermediate step to allow the subsequent growth of regions of high quality III-V semiconductor materials. On top of the transition layer 3 there exists a second region 2. This second region 2 is of high quality III-V semiconductor (for example GaN) and comprises several layers. A third region 1 of III-V semiconductor containing a mole fraction of Aluminium is formed on top of the second region 2. The third region 1 is formed such that a hetero-structure is formed at the interface between the second 2 and third region 1 resulting in the formation of a two dimensional electron gas (2DEG).
[0142] A fourth region of highly p-doped III-V semiconductor 11 is formed in contact with the third region 1. This has the function of reducing the 2DEG carrier concentration when the device is unbiased and is pGaN material (preferably made of GaN and doped with Magnesium) in this embodiment. A gate control terminal 10 is configured over the fourth region 11 in order to control the carrier density of the 2DEG at the interface of the second 2 and third region 1. A high voltage drain terminal 9 is arranged in physical contact with the third region 1. The high voltage drain terminal forms an ohmic contact to the 2DEG. A low voltage source terminal 8 is also arranged in physical contact with the third region 1 and also forms an ohmic contact to the 2DEG.
[0143] A first portion of surface passivation dielectric 7 is formed on top of the fourth region 11 and between the drain terminal 9 and source terminal 8. A p-injector region 101, preferably made using the same material as the pGaN gate 11, is also formed in contact with third region 1 possibly in the same step as fourth region 11. A floating contact layer 102 is formed in contact with both the p-injector region 101 and third region 1. A second portion of surface passivation dielectric 7 is formed on top of the p-injector region 101, and may be separate from or connected with the first portion of surface passivation dielectric. A layer of SiO2 or nitride or another oxide-nitride playing the role of a passivation layer 6 is formed above the surface passivation dielectric 7 and source and drain terminals 8, 9.
[0144] The injector of holes 101 is not connected physically to any hole injector electrode (or the drain terminal 9) but only physically (electrically) connected to the floating contact 102 that also connects a part or a portion of the 2DEG. A portion of the 2DEG connects the second terminal (drain) 9 to the floating contact 102. This is illustrated in FIG. 4A which shows the 2DEG present in the region beneath the drain terminal and the floating contact.
[0145] FIG. 4A illustrates a schematic representation of a cross section of the active area of the proposed disclosure according to one embodiment of the disclosure. In this configuration, all electrodes (8, 9 and 10), as well as the substrate terminal 5, are at zero bias. There is no bias in the floating contact 102.
[0146] Note that the substrate terminal 5 in this example is at the same potential as the source terminal 8, that is an electrical connection might exist between the two either at package level or possibly circuit level. This is commonly the case in discrete GaN-on-Si or GaN-on-SiC devices. It might however not be the case in GaN-on-Sapphire case or for example, a device on the high side of a monolithically integrated GaN-on-Si half bridge.
[0147] When the drain terminal 9 is positively biased with respect to the source terminal 8, a current flows from the drain terminal 9 through the portion of the 2DEG that connects the drain terminal 9 to the floating contact layer 102. This current is formed by a flow of electrons from the floating contact layer 102 to the drain terminal 9 as illustrated in FIG. 4B.
[0148] FIG. 4B illustrates a schematic representation of a cross section of the active area of the proposed disclosure according to one embodiment of the disclosure. In this configuration, the drain terminal 9 is biased to a moderately high voltage (e.g. approximately 60% of nominal breakdown). The floating contact layer 102 (i.e. metallization region that is not connected to any external electrodes) converts the electrons into holes which are then injected back into the III-Nitride region 2 from the p-injector region 101. In this example, the 2DEG could only be formed of electrons while the p+ injector is only a source of holes. The metal (on the floating contact layer) can provide both electrons and holes and converts the electron current from the 2DEG into a hole current in the p-injector region. This injection is particularly advantageous during the off-state stress or during the transient while the drain voltage raises.
[0149] However, at very high gate voltages, the 2DEG portion between the drain terminal 9 to the floating contact 102 gets depleted as illustrated in FIG. 4C. FIG. 4C illustrates a schematic representation of a cross section of the active area of the proposed disclosure according to one embodiment of the disclosure, where the drain terminal is biased to a high voltage (e.g. above nominal breakdown). As a result, the current made of electrons no longer flows into the floating contact layer 102 to be converted into holes and re-injected as leakage into the structure. The outcome in this embodiment is therefore a lower leakage current at high voltages than in the case where the p-injector 101 is hardwired to a hole injector electrode (e,g. drain 9).
[0150] Hole injection can happen also in the on-state, as the drain terminal 9 is at slightly higher potential than the source 8. This injection is generally limited as the potential difference between the terminals is significantly smaller than in the off-state. This on-state hole injection may however be significant in the scenario where trapped electrons, and therefore a region of negative charge 120, persist in the GaN buffer 2 after a period of off-state bias. This is illustrated in FIG. 4D.
[0151] FIG. 4D illustrates a schematic representation of a cross section of the active area of the proposed disclosure according to one embodiment. The gate 10 and drain terminal 9 are biased to a low positive voltage i.e. the device is in the on-state condition. In addition, some level of hole injection generally occurs from the pGaN region 11 beneath the gate electrode 10 as also illustrated in FIG. 4D.
[0152] The good electrical connection 115 via the 2DEG between the drain terminal 9 and the floating contact 102 at zero bias (or moderate levels of off-state bias) is shown clearly in FIG. 5A which illustrates a circuit schematic representation of the proposed disclosure where all electrodes are at zero bias.
[0153] The weakening or non-existent electrical connection 116 via the 2DEG between the drain terminal 9 and the floating contact 102 at high off-state bias is clearly shown in FIG. 5B. This illustrates a circuit schematic representation of the proposed disclosure where the drain terminal is biased to a high voltage (e.g. above nominal breakdown).
[0154] FIG. 6A illustrates a three-dimensional schematic representation of a section of the active area of the proposed disclosure where again at least one p-injector region 101 is placed outside the drift region. In this embodiment, the floating contact 104 and p-injector region 101 are formed as islands of such structures in the third-dimension. Metal via 105 and floating metal interconnect 103 are used to connect the floating contact 104 to the p-injector region 101. A contact 106, which could be a different metallization from contact 104, is placed on the p-injector. In this diagram, there is a 2DEG connection 107 at zero bias between drain electrode 9 and contact 104. In this diagram, the floating contact layer is formed from the metal contacts 103, 104, 105 and 106.
[0155] FIG. 6B shows a top view of the same section of the active area of the proposed disclosure (x, z axis). FIG. 6B shows a schematic representation of a cross section of the active area of the proposed disclosure (x, y axis) along the cutline shown in the top view.
[0156] FIG. 5C shows a top view and cross section of a variant of the structure in FIG. 6B where the distance of the floating contact island 104 and the p-injector region 101 from the drain electrode 9 is not equal. Advantageously, a reduced distance between p-injector 101 and drain electrode 9 may increase the effectiveness of the mechanism of hole injection. An increased distance between floating contact 104 may lead to more effective depletion of the 2DEG at high off-state bias between the drain electrode 9 and the floating contact 104.
[0157] FIG. 7 shows a top view (x, z axis) of a section of the active area of the proposed disclosure where at least one p-injector region 101 is placed outside the drift region.
[0158] FIG. 7 shows a schematic representation of a cross section of the active area of the proposed disclosure (x, y axis) along the cutline shown in the top view. Similar to FIG. 6, FIG. 7 also contains islands of p-injector regions 101 in the third dimension however a continuous metallisation layer 108. A single process step may be used to form both of the floating contact and the contact on the p-injector islands 101.
[0159] FIG. 8 illustrates a schematic representation of a cross section of the active area of the proposed disclosure according to a further embodiment of the disclosure where the p-injector region 101 is placed inside the drift region. Placing the p-injector 101 and the floating contact layer 102 laterally between the source terminal 8 and the drain terminal 9 and closer to the source terminal 8 would allow the hole injection to become stronger at lower potentials applied to the drain 9. Several such p-injector/floating contact structures can be placed laterally between the source terminal 8 and drain terminal 9. Placing one or more of such p-injector/floating contact structures inside the drift region leads to a weakening of the 2DEG beneath the p-injector regions, which may statically increase the on-state resistance of the device. Advantageously, placing islands of such structures in the third-dimension reduces this effect. Such an embodiment is illustrated in FIG. 9.
[0160] FIG. 9A illustrates a three-dimensional schematic representation of a section of the active area of the proposed disclosure where at least one p-injector region 101 is placed inside the drift region. In this embodiment, a floating contact 104 is shown making a good ohmic connection 107 to the 2DEG at zero bias. Metal via 105 and floating metal interconnect 103 are used to connect the floating contact 104 to the p-injector region 101. A contact 106, which could be a different metallization from contact 104, is placed on the p-injector. In this diagram, the floating contact layer is formed from the metal contacts 103, 104, 105 and 106.
[0161] FIG. 9B shows a top view of the same section of the active area of the proposed disclosure (x, z axis). FIG. 9B shows a schematic representation of a cross section of the active area of the proposed disclosure (x, y axis) along the cutline shown in the top view.
[0162] FIG. 10 shows a top view (x, z axis) of a section of the active area of the proposed disclosure where at least one p-injector region is placed beneath the drain electrode finger metallization. FIG. 10 shows a schematic representation of a cross section of the active area of the proposed disclosure (x, y axis) along the cutline shown in the top view. In this embodiment the metallisation of the drain electrode 9 covers the floating contact 109 and the p-injector region 101 which are again implemented as islands in the third dimension. The drain electrode 9 is separated from these islands electrically using a passivation layer 110.
[0163] FIG. 11 shows a top view (x, z axis) of a section of the active area of the proposed disclosure where at least one p-injector region is placed beneath the drain electrode finger metallization. FIG. 11 shows a schematic representation of a cross section of the active area of the proposed disclosure (x, y axis) along the cutline shown in the top view. In this embodiment, similar to the embodiment of FIG. 10, islands of floating contacts 113 and p-injector region 101 are placed under the drain electrode 9 and separated electrically from it using passivation layer 111. The floating contact 113 and p-injector region 101 are connected electrically using metallisation layer 112. In this diagram, the floating contact layer is formed from the metal contacts 112, 113.
[0164] FIG. 12 shows a top view (x, z axis) of a section of the active area of the proposed disclosure where at least one p-injector region is placed inside the drift region and at least one floating contact is placed beneath the drain electrode finger metallization. FIG. 12 shows a schematic representation of a cross section of the active area of the proposed disclosure (x, y axis) along the cutline shown in the top view. In this embodiment, floating contact 113 is placed under the drain electrode 9 whereas the p-injector region 101 is placed as islands inside the drift region. Floating contact 113 and p-injector 101 are connected electrically using metallisation layer 112 and separated from the drain electrode using passivation layer 111. Advantageously, placing the p-injector region inside the drift region may be more effective in reducing or eliminating the phenomenon of dynamic Ron degradation. In this diagram, the floating contact layer is formed from the metal contacts 112, 113.
[0165] FIG. 13 shows a top view (x, z axis) of a section of the active area of the proposed disclosure where at least one floating contact is placed inside the drift region and at least one p-injector region is placed beneath the drain electrode finger metallization. FIG. 13 shows a schematic representation of a cross section of the active area of the proposed disclosure (x, y axis) along the cutline shown in the top view. In this embodiment, p-injector region 101 is placed under the drain electrode 9 whereas the floating contact 113 is placed as islands inside the drift region. Floating contact 113 and p-injector 101 are connected electrically using metallisation layer 112 and separated from the drain electrode using passivation layer 111. Advantageously, placing the floating contact inside the drift region may lead to achieving a depletion of the 2DEG located between the drain contact 9 and the floating contact 113 at a lower off-state bias voltage in comparison to an embodiment where the floating contact is outside the drift region. This can limit the hole injection current at lower off-state bias if it is found to contribute significantly to the device off-state leakage current.
[0166] FIG. 14 shows a top view (x, z axis) of an interdigitated device layout embodiment of the proposed disclosure. In this embodiment, the floating contact 104, the p-injector region 101 and electrical connection between them, metallisation layer 103, are all placed outside of the drift region. All of the previously described embodiments can be implemented using variations of an interdigitated layout similar to the exemplary layout shown in FIG. 14.
[0167] FIG. 15A illustrates a schematic representation of a cross section of the active area of the proposed disclosure according to one embodiment of the disclosure where the p-injector region is placed outside the drift region. In this embodiment, a second floating p-type region 114 could be inserted laterally between the drain 9 and the contact of the floating contact metal 102. This second floating region 114 has only the role to weaken the charge of the portion of the 2DEG between the drain metal 9 and the actual contact of the floating contact layer 102. Advantageously, in operation this facilitates the depletion of this portion of the 2DEG when a very high voltage is present on the drain terminal 9. The p-type region 114 may be a different from (for example in layer thickness or doping concentration) or the same as p-type region 11 and p-type region 101 as the features of each region may be optimized accordingly.
[0168] FIG. 15B illustrates a schematic representation of a cross section of the active area of the proposed disclosure similar to FIG. 15A where the p-type region 114 is not floating but is connected to an external injector control electrode 117. The voltage bias of electrode 117 can be used to modulate the carrier concentration in the 2DEG beneath it and therefore control the hole injection current from the p-injector region 101. The potential and the current through the electrode 117 could be provided by an external circuit (which could be part of the driver) which could control its operation as to compensate for the dynamic Ron. The control sequence could be pre-determined (for example being on at certain drain voltages in the off-state) or could have a feedback from a circuit estimating the Ron in certain conditions and determine if Ron degrades and as a result injecting current into the hole injector electrode.
[0169] FIG. 16A illustrates a schematic representation of a cross section of the active area of the proposed disclosure according to one embodiment of the disclosure where the p-injector region 101 is placed outside the drift region. In this embodiment, a recess is provided for the p-injector, so that the p-injector 101 is closer to the 2DEG to facilitate easier injection of holes.
[0170] FIG. 16B illustrates a schematic representation of a cross section of the active area of the proposed disclosure according to one embodiment of the disclosure where the p-injector region 101 is placed outside the drift region. In this embodiment, a recess is provided for the p-injector, so that the p-injector 101 is below the 2DEG to facilitate easier injection of holes.
[0171] FIG. 17 shows a top view (x, z axis) of an interdigitated device layout embodiment of the proposed disclosure. In this embodiment, a p-injector region 101 is placed outside the main active area of the device 29, inside its own isolated active area 30. In this case, the floating contact layer 104 and the 2DEG portion between the drain terminal and the contact of the floating contact metal are placed outside the main active area 29 in another isolated active area of the device 30. Such isolated area could be placed at the edge of the device or for example in the vicinity of drain pad 28 as shown.
[0172] FIG. 18 shows a schematic cross section of a diode according to a second aspect of the invention. The feature of this figure are broadly similar to those of FIG. 3, but do not include the fourth region 11 or gate control terminal 10. In this example, electrode 8 would be a Schottky contact in order to produce a Schottky diode. Advantageously, the inclusion of p-injector 101 reduces or minimises the on-state loss of conductivity when the diode is forward-biased, especially when the diode has been previously exposed to a high voltage stress during reverse-bias. The above described alternative embodiments of the p-injector, in particular but not limited to those described with reference to FIGS. 5-11, 13 and 14, may also be utilised in conjunction with a diode according to this aspect of the invention.
[0173] Alternatively, a rectifier where the gate and source terminal of FIG. 3 are electrically connected (rather than a Schottky anode as in FIG. 18) can be designed.
[0174] FIG. 19 illustrates a graph showing a typical increase in on-state resistance of a GaN-on-Si HEMT device following a period of off-state stress, that is the phenomenon described herein as Dynamic Ron. The graph X-axis shows the off-state stress applied and the graph Y-axis shows the percentage increase in on-state resistance compared to the measured on-state resistance of the device (also referred to as the static on-state resistance) before any off-state stress was applied. As illustrated in FIG. 19 the increase in on-state resistance may be greater at relatively low off-state voltages (e.g. 100V-200V) than at higher off-state voltages (e.g. 400V).
[0175] The above-described effect may be related to the electric field peak observed at edge of the gate terminal (on the drain side of the gate). FIGS. 20, 21 and 22 illustrate a Technology Computer-Aided Design (TCAD) result of the electric field peak observed at different off-state drain bias voltages in a standard HEMT (FIG. 1). The source and gate terminals of the device are biased at zero volts. The Norm of the electric field was plotted along the z-dimension at the level of the AlGaN/GaN interface where the 2DEG is present. In FIG. 20 the off-state drain voltage bias is 100V. The electric field peak observed in the plot is present at the edge of the gate structure (on the drain side of the gate). In FIG. 21 the off-state drain voltage bias is 400V. The electric field peak observed in the plot is again present at the edge of the gate structure (on the drain side of the gate). It is interesting to note that the electric filed peak in FIG. 21 is reduced compared to the peak observed in FIG. 20. The reason for this is the abrupt depletion of the 2DEG which leads to a redistribution of the electric field inside the drift region. This leads to a higher electric field being present at the drain terminal and lower field peak at the gate terminal. The lower electric field at the gate terminal in the presence of very high voltage stress may be the cause of the Dynamic Ron increase effect observed at lower voltages (100V, 200V) compared to higher voltages (400V).
[0176] In FIG. 22 the off-state drain voltage bias is 600V. In this plot a second electric field peak appears. An electric field peak is again present at the edge of the gate terminal (on the drain side of the gate). A second peak is observed at the drain terminal (on the gate side of the drain).
[0177] It may be useful to optimise the device described in this invention, so that the p-injector region 101 starts emitting a significant number of holes at off-state bias voltages around 100V-200V or where the Dynamic Ron effect is most severe in other examples. The off-state voltage at which significant hole injection from p-injector region 101 is observed might be adjusted by decreasing the separation of the p-injector region 101 and the floating contact layer 102 from the gate terminal 10, 11. The smaller the distance between the gate terminal and the floating contact layer 102 the lower the off-state voltage at which the hole injection from the p-injector region might be observed.
[0178] An example where the distance between the gate terminal 11 and floating contact layer 102 is reduced, compared to the embodiment in FIG. 8, is shown in FIG. 23.
[0179] Additionally, a corresponding increase in the distance between the floating contact layer 102 and the drain contact layer 9 (with the gate-drain distance remaining unchanged in FIGS. 8, 23) may lead to the 2DEG portion between the drain terminal 9 and the floating contact 102 getting significantly depleted at a lower off-state bias in the device of FIG. 23 compared to the device of FIG. 8.
[0180] FIG. 24A illustrates a three-dimensional schematic representation of a section of the active area of the proposed disclosure where at least one p-injector region 101 is placed inside the drift region. This embodiment is similar to the embodiment illustrated in FIG. 9A. In this embodiment however the distance between the gate terminal 11 and the floating contact layer is reduced, compared to the embodiment in FIG. 9A.
[0181] The formation of the floating contact layer 104 and p-injector region 101 as islands rather than a continuous strip can have two advantages: [0182] Effect on on-state resistance mentioned in previous sections of this disclosure. [0183] Can enable a lateral depletion (along z-axis) to extend from the gate terminal, through the gaps between the islands, depleting the 2DEG 107 between the drain terminal 9 and floating contact 104 and creating a potential difference between the drain terminal 9 and the floating contact 104. This effect may reduce the hole injection from p-injector region 101 at a lower off-state bias compared to the vertical depletion (along y-axis) of the 2DEG 107 between the drain terminal and floating contact.
[0184] FIG. 24B shows a top view of the same section of the active area of the proposed disclosure (x, z axis). FIG. 24B shows a schematic representation of a cross section of the active area of the proposed disclosure (x, y axis) along the outline shown in the top view.
[0185] An increase in the distance between the floating contact layer 104 and the drain contact layer 9 (with the gate-drain distance remaining unchanged in FIG. 9A, 24A) may lead to the 2DEG portion 107 between the drain terminal and the floating contact getting depleted at a reduced off-state bias in the device of FIG. 24A compared to the device of FIG. 9A.
[0186] In FIG. 25A, the distance between the gate terminal 11 and the floating contact layer 102 is reduced further, compared to the embodiment in FIG. 8 and FIG. 23. In this embodiment the floating ohmic contact and p-injector region 101 are placed under the field plate which is at source potential.
[0187] In FIG. 25B, an additional p-region 132 is placed between the floating contact layer 102 and the drain terminal to enable an easier depletion of the 2DEG layer between the floating contact layer and the drain terminal in the off-state condition where the hole injection current/leakage current from the p-injector region 101 needs to be limited.
[0188] In an additional embodiment, the floating contact layer 102 and the p-injector region 101 are separated along the gate-drain axis and connected with metal interconnect 125 as illustrated in FIG. 26A. Metal contact 126 is placed on p-injector region 101 in this embodiment.
[0189] Similarly, in other embodiments, which feature p-injector region islands (such as the embodiment illustrated in FIG. 24A) a separation could exist between floating contact 104 and p-injector region 101 along the gate-drain axis (z-axis). Floating metal interconnect 103 can be used to connect regions 101 and 104.
[0190] In some embodiments, the distance between the floating contact 102, 104 and gate terminal 10 may be smaller than the distance between the p-injector region island 101 and the gate terminal 10.
[0191] In other embodiments, the distance between the p-injector region island 101 and gate terminal 10 may be smaller than the distance between the floating contact 102, 104 and the gate terminal 10.
[0192] In other embodiments, the floating contact 102, 104 may be placed between the gate terminal 10 and the p-injector region island 101 (along the z-axis).
[0193] In other embodiments, the p-injector region island 101 may be placed between the gate terminal 10 and the floating contact 102, 104 (along the z-axis).
[0194] One example of the embodiments described here is illustrated in FIG. 26B. FIG. 26B shows a top view (x, z axis) of a section of the active area. In this embodiment, the floating contact 102 is placed between the gate terminal 10 and the p-injector region islands 101. The floating contact 102 is connected to the p-injector islands 101 using metal interconnect 128. Both the floating contact 102 and the p-injector islands 101 are covered by source connected field plate 130. Region 129 is a via connection between the source contact and field plate metal 130.
[0195] FIG. 27 illustrates a schematic representation of a cross section of a further embodiment of the proposed invention. This embodiment does not comprise a floating contact on the AlGaN layer 1. This embodiment comprises a floating p− type doped region 119, optionally with a floating metal contact 118. The p-doped region can act as a field ring in this embodiment with the aim of reducing the electric field peak at the drain edge of the gate terminal (see electric field peak in FIGS. 20, 21.) The effect of this field ring on reducing the field peak at the gate structure may be more effective than the more common use of metals as field plates. By achieving a reduction in the electric field peak observed and a more favourable distribution of the electrostatic potential in the structure at a given off-state bias (for example 100V-200V) the effect of Dynamic Ron may be reduced.
[0196] FIG. 28 shows a top view (x, z axis) of a section of the active area of the proposed disclosure where the p-doped region 119 comprises islands separated in the third dimension rather than a continuous stripe of p− type doped region. This embodiment may be more favourable by achieving a lower static on-state resistance compared to the embodiment illustrated in FIG. 27 as the regions of 2DEG directly under the p-doped region may have a lower concentration of electrons. A depletion region developing between the p-doped island regions (along x-axis) in the off-state condition, can protect the edge of the gate terminal from being exposed to a high electric field.
[0197] FIG. 28 further shows a schematic representation of a cross section of the active area of the proposed disclosure (x, y axis) along the outline shown in the top view.
[0198] FIG. 29 illustrates a schematic representation of a cross section of a further embodiment of the proposed invention. This embodiment is similar to the embodiment in FIG. 27 but comprises a second row of a floating p− type doped region 121 and a second metal contact 131.
[0199] FIG. 30 shows a top view (x, z axis) of a section of the active area of the proposed disclosure where the second p-doped region 121 comprises islands separated in the third dimension rather than a continuous stripe of p-type doped region.
[0200] FIG. 30 further shows a schematic representation of a cross section of the active area of the proposed disclosure (x, y axis) along the outline shown in the top view.
[0201] FIG. 31 illustrates a schematic representation of a cross section of a further embodiment of the proposed invention. This embodiment is similar to the embodiment in FIG. 29 but contains a third row of p-type doped region 123 and a third metal contact 122.
[0202] FIG. 32 shows a top view (x, z axis) of a section of the active area of the proposed disclosure where the second p-doped region 121 comprises islands separated in the third dimension rather than a continuous stripe of p-type doped region.
[0203] In the example illustrated in FIG. 32: [0204] the separation of the p− type doped island regions in the first row, along the x-axis, is labelled as distance (a). Distance (a) also signifies the separation between the edge of the gate terminal and the first row of p-doped islands along the z-axis. [0205] the separation of the p-type doped island regions in the second row, along the x-axis, is labelled as distance (b). Distance (b) also signifies the separation between the edge of the first row of p-doped islands and the second row of p-doped islands along the z-axis. [0206] the separation of the p-doped island regions in the third row, along the x-axis, is labelled as (c). Distance (c) also signifies the separation between the edge of the second row of p-doped islands and the third row of p-doped islands along the z-axis.
[0207] In this example (c)>(b)>(a). These dimensions may be an important design parameter which shapes the electrostatic potential in the device in off-state conditions and therefore can be optimized in different device designs.
[0208] FIG. 33 illustrates a schematic representation of a cross section of a further embodiment of the proposed invention. In this embodiment the floating metal contact is connected to the potential of floating metal field plate 127. In other embodiments the floating metal contacts 118, 131, 122 could be connected to source potential, gate potential or the potential of other floating metal field plates.
[0209] FIG. 34 illustrates a schematic representation of a cross section of a further embodiment of the proposed invention. In this embodiment the p-doping field plate structure 118, 119, 127 and the floating metal contact 102/p-injector region 101 are used in combination the same device. This design may lead to the suppression of both electric field peaks present in the structure at high off-state bias voltage condition as shown in the example of FIG. 22. This combination design may further improve the device Dynamic Ron performance.
[0210] In addition to the embodiment in FIG. 34, other combinations of the p-doped field plate structures 119, 121, 123 and the floating p-injector structures 101, 102 presented herein are within the scope of this invention. Such combinations of different structures disclosed in this invention (in different embodiments) can be implemented to further reduce the effect of the dynamic on-state resistance for a wide range of off-state stresses.
[0211] Generally speaking, in this disclosure, the first conductivity type refers to p-type conductivity and the second conductivity type generally refers to the n-type conductivity. However, it will be understood that the conductivity type can be readily reversed. The skilled person will understand that in the preceding description and appended claims, positional terms such as ‘top’, ‘above’, ‘overlap’, ‘under’, ‘lateral’, etc. are made with reference to conceptual illustrations of a device, such as those showing standard cross-sectional perspectives and those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a device when in an orientation as shown in the accompanying drawings.
[0212] Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.
[0213] Many other effective alternatives will occur to the person skilled in the art. It will be understood that the disclosure is not limited to the described embodiments, but encompasses all the modifications which fall within the spirit and scope of the disclosure.
List of Reference Numerals
[0214] 1—AlGaN layer [0215] 2—GaN layer [0216] 3—Transition layer [0217] 4—Silicon substrate [0218] 5—Substrate electrode [0219] 6—Silicon Dioxide passivation [0220] 7—Surface passivation [0221] 8—Source electrode [0222] 9—Drain electrode [0223] 10—Gate electrode [0224] 11—pGaN layer [0225] 26—gate pad metal [0226] 27—source pad metal [0227] 28—drain pad metal [0228] 29—active area [0229] 30—second active area [0230] 80—external drive [0231] 90—additional electrode [0232] 101—p-injector region/pGaN hole injection layer [0233] 102—floating contact (electron/hole converter) [0234] 103—floating metal interconnect [0235] 104—ohmic contact [0236] 105—metal via [0237] 106—metal contact [0238] 107—2DEG connection at zero bias between drain electrode 9 and ohmic contact 104 [0239] 108—floating contact/metallisation track (electron/hole converter) [0240] 109—floating contact (electron/hole converter) [0241] 110—passivation/inter-metal dielectric [0242] 111—passivation/inter-metal dielectric [0243] 112—floating metal interconnect [0244] 113—ohmic contact [0245] 114—additional p-region [0246] 115—Strong 2DEG electrical connection [0247] 116—Weak 2DEG electrical connection [0248] 117—Injector Control Electrode [0249] 118—floating metal contact [0250] 119—p-doped region [0251] 120—region of trapped negative charge [0252] 121—p-doped region [0253] 122—floating metal contact [0254] 123—p-doped region [0255] 125—metal interconnect [0256] 126—metal contact [0257] 127—metal field plate [0258] 128—metal interconnect [0259] 129—metal via [0260] 130—metal field plate [0261] 131—floating metal contact [0262] 132—additional p-region
