Bond pad structure for low temperature flip chip bonding

Abstract

Methods for preparing 3D integrated semiconductor devices and the resulting devices are disclosed. Embodiments include forming a first and a second bond pad on a first and a second semiconductor device, respectively, the first and the second bond pads each having plural metal segments, the metal segments of the first bond pad having a configuration different from a configuration of the metal segments of the second bond pad or having the same configuration as a configuration of the metal segments of the second bond pad but rotated with respect to the second bond pad; and bonding the first and second semiconductor devices together through the first and second bond pads.

Claims

1. A method comprising: forming a first and a second bond pad on a first and a second semiconductor device, respectively, the first and the second bond pads each having plural metal segments, the metal segments of the first bond pad having a configuration different from a configuration of the metal segments of the second bond pad or having the same configuration as a configuration of the metal segments of the second bond pad but rotated with respect to the second bond pad; and bonding the first and second semiconductor devices together through the first and second bond pads, wherein the metal segments of the first bond pad on the first semiconductor device comprise only columns of segments, the columns being staggered with respect to each other, and the metal segments of the second bond pad on the second semiconductor device comprise only rows of segments, the rows being staggered with respect to each other, wherein the columns of segments are perpendicular to the rows of segments.

2. The method according to claim 1, comprising forming a larger first bond pad on the first semiconductor device than the second bond pad on the second semiconductor device.

3. The method according to claim 1, comprising patterning the first and second bond pads on the first and second semiconductor devices, respectively, by a copper damascene process.

4. The method according to claim 1, further comprising surrounding the first and second bond pads on the first and second semiconductor devices, respectively, by a dielectric layer; and bonding the first and second semiconductor devices together through the dielectric layers in a chemical or plasma activated fusion bonding process.

5. The method according to claim 1, wherein the first and second semiconductor devices include a low temperature inorganic layer around the metal segments, the method further comprising planarizing the first and second bond pads and the low temperature inorganic layer on the first and second semiconductor devices, respectively, by Chemical Machine Polishing (CMP) before bonding together.

6. The method according to claim 1, further comprising patterning the bond pads on the first and second semiconductor devices by a copper damascene process, and bonding the first and second semiconductor devices together through copper-to-copper bonds in the patterned bond pads.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:

(2) FIGS. 1A and 1B illustrate a conventional 3D integration of semiconductor devices;

(3) FIGS. 2A through 2C illustrate a bond pad pattern, according to an exemplary embodiment;

(4) FIG. 3 illustrates a cross-sectional view of a 3D integration of semiconductor devices, according to an exemplary embodiment.

(5) FIGS. 4A through 4C illustrate another bond pad pattern, according to an exemplary embodiment; and

(6) FIGS. 5A through 5C illustrate another bond pad pattern, according to an exemplary embodiment.

DETAILED DESCRIPTION

(7) In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term about.

(8) The present disclosure addresses and solves the current problem of dishing of bond pad surfaces attendant upon CMP of the bond pad surfaces prior to bonding and the resulting voids in interconnects between semiconductor devices, e.g., ICs and MEMS, in 3D integrated devices. In order to avoid or minimize the effect of dishing of bond pad surfaces after CMP and the resulting voids between semiconductor devices, a method in accordance with embodiments of the present disclosure includes forming a first and a second bond pad on a first and a second semiconductor device, respectively, the first and the second bond pads each having plural metal segments, the metal segments of the first bond pad having a configuration different from a configuration of the metal segments of the second bond pad or having the same configuration as a configuration of the metal segments of the second bond pad but rotated with respect to the second bond pad; and bonding the first and second semiconductor devices together through the first and second bond pads.

(9) The replacement of large solid bond pads used in conventional 3D integration processes with bond pads having different configurations or rotated configurations between two semiconductor devices, minimizes the effect of copper dishing during planarization by CMP and the resulting voids between adjoined semiconductor devices and allows for improved bonding. That is, rather than a single large point of contact between the bond pads on adjoined devices, interconnects are formed through multiple smaller contact points. The bond pad design can be adjusted to allow for required resistance values depending on specific needs of each interconnect function (i.e. power/ground, I/O, etc). The integration falls directly within existing dual damascene process techniques, so it can be easily implemented. It also allows the elimination of top bond pad layers for improved flip chip cost structure as well.

(10) The first and second semiconductor devices may be bonded together in a face-to-face (F2F), wafer-to-wafer (W2W), die-to-wafer (D2W), or die-to-die (D2D) manner. The first bond pad on the first device may be larger than the second bond pad on the second device to allow for any misalignment during placement, especially for individual die placement, e.g. D2W or D2D. The first and second bond pads on the first and second devices, respectively, may be patterned in the dielectric layers on the devices by a copper damascene process. The first and second devices may be bonded together through the dielectric layers using a chemical or plasma activated fusion bonding process. The first and second devices may include a low temperature inorganic layer around the metal segments, in which the first and second bond pads and the low temperature inorganic layer are planarized to be ultra-smooth by CMP before bonding together. The bond pads on the first and second may be patterned by a damascene process and the first and second devices may be bonded together through copper-to-copper bonds in the patterned bond pads.

(11) FIGS. 2A through 2C illustrate the metal segments of bond pads having a pattern of perpendicular lines, in accordance with an exemplary embodiment. As shown in FIG. 2A, the metal segments of the first bond pad 201 on the first semiconductor device (not shown for illustrative convenience) include columns of segments 203, the columns being staggered with respect to each other. The metal segments of the second bond pad 205 on the second semiconductor device (not shown for illustrative convenience) include rows of segments 207, the rows being staggered with respect to each other, as illustrated in FIG. 2B. As shown, the columns of segments 203 are perpendicular to the rows of segments 207. However, the angle could range from 45 to 90. Also shown in FIGS. 2A and 2B is a dielectric 209 surrounding the first and second bond pads. The dielectric layers may, for example, be low temperature inorganic dielectric layers. Further the bond pads may be patterned in the dielectric layers by a copper damascene process. FIG. 2C illustrates the overlay of the metal segments of the first bond pad 201 on the metal segments of the second bond pad 205. The two semiconductor devices may be bonded together through the dielectric layers, e.g. by chemical or plasma activated fusion bonding. In addition, as the bond pads may be copper, the devices may be bonded through copper-to-copper bonds formed after annealing.

(12) FIG. 3 illustrates a cross-sectional view of a 3D integration 301 for F2F bonding of two semiconductor devices with the metal segments of bond pads having a pattern of perpendicular lines. The device 301 includes top die 303 and bottom die 305, each of which includes a dielectric layer 307. Dies 303 and 305 are joined together along bond plane 309. Also shown are the top and bottom metal routing layers, 311 and 313, respectively, which are connected to the top and bottom bond pads, 315 and 317, respectively, through vias 319. As illustrated, the bond pads 315 and 317 are in good contact with each other along the bond plane 309. (In FIG. 3, the top and bottom dies only show the top pad in a BEOL stack for illustration convenience. There may be multiple metal/dielectric layers in the BEOL stack.)

(13) FIGS. 4A through 4C illustrate the metal segments of bond pads having a pattern of lines on islands, in accordance with an exemplary embodiment. As shown in FIG. 4A, the metal segments of the first bond pad 401 on the first semiconductor device (not shown for illustrative convenience) include columns and rows of metal islands 403. Adverting to FIG. 4B, the metal segments of the second bond pad 405 on the second semiconductor device (not shown for illustrative convenience) include lines of diagonal segments 407, the lines being staggered with respect to each other. As shown, the lines of segments 407 are at a 45 angle to the columns and rows of metal islands 403. However, the angle could range from 45 to 90. A dielectric 409 surrounds the first and second bond pads. The dielectric layers may, for example, be low temperature inorganic dielectric layers. Further the bond pads may be patterned in the dielectric layers by a copper damascene process. FIG. 4C illustrates the overlay of the metal segments of the first bond pad 401 on the metal segments of the second bond pad 405. The two semiconductor devices may be bonded together through the dielectric layers, e.g. by chemical or plasma activated fusion bonding. In addition, as the bond pads may be copper, the devices may be bonded through copper-to-copper bonds formed after annealing.

(14) FIGS. 5A through 5C illustrate the metal segments of bond pads having a pattern of an alternating cross-hatch, in accordance with an exemplary embodiment. As shown in FIG. 5A, the metal segments of first bond pad 501 on the first semiconductor device (not shown for illustrative convenience) include a first grid 503 of rows and columns. As illustrated in FIG. 5B, the metal segments of the second bond pad 505 on the second semiconductor device (not shown for illustrative convenience) include a second grid 507 of rows and columns. As shown, the second grid 507 of rows and columns is at a 45 degree angle with respect to the first grid 503 of rows and columns. A dielectric 509 surrounds the first and second bond pads. The dielectric layers may, for example, be low temperature inorganic dielectric layers. Further the bond pads may be patterned in the dielectric layers by a copper damascene process. FIG. 5C illustrates the overlay of the metal segments of the first bond pad 501 on the metal segments of the second bond pad 505. The two semiconductor devices may be bonded together through the dielectric layers, e.g. by chemical or plasma activated fusion bonding. In addition, as the bond pads may be copper, the devices may be bonded through copper-to-copper bonds formed after annealing.

(15) As described above and shown in FIGS. 2A through 2C, the metal segments of the bond pads on the semiconductor devices may have a pattern of perpendicular lines. Alternatively, as described above and shown in FIGS. 4A through 4C, the metal segments of bond pads on the semiconductor devices may have a pattern of lines on islands. Further, as described above and shown in FIGS. 5A through 5C, the metal segments of bond pads on the semiconductor devices may have a pattern of an alternating cross-hatch. However, other configurations in which the bond pads meet in small areas, rather than the entire pad are possible as well. In addition, although not shown for illustrative convenience, the first bond pad may be larger than the second bond pad.

(16) Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

(17) The embodiments of the present disclosure can achieve several technical effects, such as reduced dishing resulting in improved interconnect contacts for ICs or MEMS implemented with existing dual damascene techniques. Devices formed in accordance with embodiments of the present disclosure are useful in various industrial applications, e.g., microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure therefore has industrial applicability in any of various types of highly integrated semiconductor devices.

(18) In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.