Method for Forming a Semiconductor Structure

Abstract

A method for forming a semiconductor structure includes forming a layer stack. The method also includes forming a gate structure on the layer stack, and forming at least one cavity by removing the at least one second sacrificial layer of the layer stack. The method further includes depositing a first dielectric material, and filling the at least one cavity with the first dielectric material. Further, the method includes providing a dielectric free gate surface, free from the first dielectric material. Furthermore, the method includes depositing a second dielectric material on the dielectric free gate surface. The second dielectric material is different from the first dielectric material.

Claims

1. A method for forming a semiconductor structure, the method comprising: forming a layer stack on a substrate, the layer stack comprising: a first sub-stack comprising a first sacrificial layer, and on the first sacrificial layer, a channel layer defining a topmost layer of the first sub-stack, a second sub-stack on the first sub-stack and comprising a plurality of sacrificial layers alternating between first and second sacrificial layers, wherein the first sacrificial layers define a respective bottommost and topmost layer of the second sub-stack, and the second sub-stack comprises at least one second sacrificial layer, and a third sub-stack on the second sub-stack and comprising a channel layer defining a bottommost layer of the third sub-stack and a first sacrificial layer on the channel layer, wherein the first sacrificial layers are formed of a first sacrificial semiconductor material, and the second sacrificial layers are formed of a second sacrificial semiconductor material different from the first sacrificial semiconductor material, forming a gate structure on the layer stack; forming at least one cavity by removing the at least one second sacrificial layer of the second sub-stack; depositing a first dielectric material, wherein depositing the first dielectric material comprises filling the at least one cavity with the first dielectric material; providing a dielectric free gate surface, the dielectric free gate surface being an end surface of the gate structure, free from the first dielectric material; and depositing a second dielectric material on the dielectric free gate surface, wherein: the second dielectric material is different from the first dielectric material, and depositing the second dielectric material is performed after depositing the first dielectric material.

2. The method according to claim 1, wherein the second dielectric material has a dielectric constant below 6.5.

3. The method according to claim 1, wherein the second dielectric material comprises SiOCN and/or SiOC.

4. The method according to claim 1, wherein the first dielectric material is SiN, or SiOC or SiOCN or SiCN.

5. The method according to claim 1, wherein: first dielectric material is deposited on the end surface of the gate structure while filling the at least one cavity with the first dielectric material, and forming the dielectric free gate surface comprises removing first dielectric material from the end surface of the gate structure.

6. The method according to claim 5, wherein removing first dielectric material from the end surface of the gate structure is performed by dry isotropic etching.

7. The method according to claim 1, wherein depositing the first dielectric material is performed by chemical vapor deposition or physical vapor deposition.

8. The method according to claim 1, wherein: depositing the first dielectric material is performed by a chemical vapor deposition method comprising: reacting, as a film-forming gas, an oxygen-containing silicon compound gas with a non-oxidizing hydrogen-containing gas in a state in which at least the non-oxidizing hydrogen-containing gas is plasmarized, to form a film of a flowable silanol compound, and subsequently, annealing the film of the flowable silanol compound into the first dielectric material, the oxygen-containing silicon compound gas comprises Si.sub.O.sub.(OC.sub.mH.sub.n)C.sub.xH.sub.y, m, n, and are integers of 1 or more, and , , x, and y are integers of 0 or more; and and are not 0 at a same time.

9. The method according to claim 1, wherein depositing the second dielectric material is performed by atomic layer deposition.

10. The method according to claim 1, wherein depositing the first dielectric material is performed by conformal deposition.

11. The method according to claim 1, further comprising: removing, by vertical recessing, ends of the layer stack and second dielectric material on the ends; subsequently, laterally recessing end surfaces of the first sacrificial layers of the layer stack to form recesses; and forming inner spacers in the recesses.

12. The method according to claim 1, wherein the second sub-stack comprises at least two second sacrificial layers, such that at least two cavities are formed and filled with the first dielectric material.

13. The method according to claim 1, wherein: the gate structure is a sacrificial gate body, and the method further comprises replacing the sacrificial gate body with a gate stack.

14. The method according to claim 13, further comprising: forming source/drain regions at opposite ends of the channel layer of the first sub-stack; and forming source/drain regions at opposite ends of the channel layer of the third sub-stack, wherein the semiconductor structure forms a stack of field effect transistors comprising: a first field effect transistor comprising the channel layer of the first sub-stack, and a second field effect transistor comprising the channel layer of the second sub-stack.

15. The method according to claim 1, wherein: the gate structure comprises a first end surface for forming a source region at an end of a stack of field effect transistors formed by the semiconductor structure, and the gate structure comprises a second end surface for forming a drain region at the end of the stack of field effect transistors formed by the semiconductor structure.

16. The method according to claim 1, wherein neighboring first and second sacrificial layers of the second sub-stack are separated by a liner layer, the liner layer of the second sub-stack being formed of a semiconductor material different from the first and second sacrificial semiconductor materials.

17. The method according to claim 16, wherein the channel layer defining the topmost layer of the first sub-stack and the channel layer defining the bottommost layer of the third sub-stack are formed from the same material used to form the liner layer of the second sub-stack.

18. The method according to claim 1, wherein: the channel layer defining the topmost layer of the first sub-stack and the channel layer defining the bottommost layer of the third sub-stack are formed of silicon, and the first sacrificial semiconductor material and the second sacrificial semiconductor material are formed of SiGe having different Ge compositions.

19. A semiconductor structure comprising: a layer stack comprising: a first sub-stack comprising a first sacrificial layer, and on the first sacrificial layer, a channel layer defining a topmost layer of the first sub-stack, a second sub-stack on the first sub-stack and comprising a plurality of layers alternating between first sacrificial layers and layer of first dielectric material, wherein the first sacrificial layers define a respective bottommost and topmost layer of the second sub-stack, and a third sub-stack on the second sub-stack and comprising a channel layer defining a bottommost layer of the third sub-stack and a first sacrificial layer on the channel layer, wherein the first sacrificial layers are formed of a first sacrificial semiconductor material; a gate structure arranged on the layer stack; and a second dielectric material arranged on an end surface of the gate structure, wherein the second dielectric material is different from the first dielectric material.

20. The semiconductor structure according to claim 19, wherein the second dielectric material has a dielectric constant below 6.5.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0064] The above, as well as additional, features will be better understood through the following illustrative and non-limiting detailed description of example embodiments, with reference to the appended drawings. In the drawings like reference numerals will be used for like elements unless stated otherwise.

[0065] FIG. 1a, FIG. 1b, FIG. 1c, FIG. 1d, FIG. 1e, FIG. 1f, and FIG. 1g illustrate a method for forming a semiconductor structure, according to an example embodiment.

[0066] FIG. 2a and FIG. 2b illustrate further steps towards a finished stack of FETs, according to an example embodiment.

[0067] FIG. 3a and FIG. 3b illustrate further steps towards a finished stack of FETs, according to an example embodiment.

[0068] FIG. 4a and FIG. 4b illustrate further steps towards a finished stack of FETs, according to an example embodiment.

[0069] FIG. 5a and FIG. 5b illustrate further steps towards a finished stack of FETs, according to an example embodiment.

[0070] FIG. 6a and FIG. 6b illustrate further steps towards a finished stack of FETs, according to an example embodiment.

[0071] FIG. 7a and FIG. 7b illustrate further steps towards a finished stack of FETs, according to an example embodiment.

[0072] FIG. 8a, and FIG. 8b illustrate further steps towards a finished stack of FETs, according to an example embodiment.

[0073] FIG. 9a, FIG. 9b, and FIG. 9c illustrate the use of liner layers, according to an example embodiment.

[0074] All the figures are schematic, not necessarily to scale, and generally only show parts which are necessary to elucidate example embodiments, wherein other parts may be omitted or merely suggested.

DETAILED DESCRIPTION

[0075] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings. That which is encompassed by the claims may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided by way of example. Furthermore, like numbers refer to the same or similar elements or components throughout.

[0076] FIG. 1a to FIG. 1g illustrate an example implementation of a method for forming a semiconductor structure. FIG. 2a and FIG. 2b illustrate further steps towards a finished stack of FETs. Likewise, FIG. 3a and FIG. 3b illustrate further steps towards a finished stack of FETs. Similarly, FIG. 4a and FIG. 4b illustrate further steps towards a finished stack of FETs. FIG. 5a and FIG. 5b also illustrate further steps towards a finished stack of FETs. Additionally, FIG. 6a and FIG. 6b illustrate further steps towards a finished stack of FETs. FIG. 7a and FIG. 7b also illustrate further steps towards a finished stack of FETs. Furthermore, FIG. 8a and FIG. 8b illustrate further steps towards a finished stack of FETs.

[0077] The axes X, Y and Z (shown in at least some figures) indicate a first direction, a second direction transverse to the first direction, and a vertical or bottom-up direction, respectively. The X-direction and the Y-direction can be referred to as lateral or horizontal directions in that they are parallel to a main plane of a substrate 102 of a structure 100. The Z-direction is parallel to a normal direction to the substrate 102.

[0078] FIG. 1a and FIG. 1b depict respective cross-sectional views of a layer stack 110 taken along vertical planes B-B (parallel to the XZ-plane) and A-A (parallel to the YZ plane). FIG. 1c is a schematic illustration of the first, second, and third sub-stacks. The cross-sectional views of FIG. 1d to FIG. 1g correspond to that of FIG. 1a unless stated otherwise, i.e. along vertical planes B-B. The layer stack 110 has a first end 111 and a second end 112, as illustrated in FIG. 1a.

[0079] The layer stack 110 is arranged on a substrate 102. The substrate 102 can be a conventional semiconductor substrate suitable for complementary FETs. The substrate 102 can be a single-layered semiconductor substrate, for instance formed by a bulk substrate such as a silicon (Si) substrate, a germanium (Ge) substrate or a silicon-germanium (SiGe) substrate. A multi-layered/composite substrate is however also possible, such as an epitaxially grown semiconductor layer on a bulk substrate, or a semiconductor-on-insulator (SOI) substrate, such as a Si-on-insulator substrate, a Ge-on-insulator substrate, or a SiGe-on-insulator substrate.

[0080] The layer stack 110 comprises a first sub-stack 120, a second sub-stack 130 on the first sub-stack 120, and a third sub-stack 140 on the second sub-stack 130.

[0081] FIG. 1c depicts the first sub-stack 120 (bottom), the second sub-stack 130 (middle) and the third sub-stack 140 (top) in isolation for illustrational clarity.

[0082] The first sub-stack 120 comprises a first sacrificial layer 122a and a channel layer 124 on the first sacrificial layer 122a. The channel layer 124 forms a top (i.e. topmost) layer of the first sub-stack 120. The first sacrificial layer 122a and the channel layer 124 can be referred to as one unit of the first sub-stack 120. Although FIG. 1c depicts merely one such unit (i.e. a single unit) of the first sub-stack 120, it is to be understood that the first sub-stack 120 can comprise more than merely a single unit. For instance, the first sub-stack 120 can comprise two, three, four, or more units. As such, the first sub-stack 120 can comprise two, three, four, or more first sacrificial layers 122a and two, three, four, or more channel layers 124. In case the first sub-stack 120 comprises a plurality of such units, the units can be consecutively arranged. For instance, the units can be arranged on top of each other.

[0083] The second sub-stack 130 comprises a plurality of sacrificial layers alternating between first and second sacrificial layers 132a, 132b.

[0084] FIG. 1c illustrates a second sub-stack 130 comprising (along a bottom-up direction) a bottommost first sacrificial layer 132a, a second sacrificial layer 132b, a first sacrificial layer 132a, a second sacrificial layer 132b, and a topmost first sacrificial layer 132a. The bottommost first sacrificial layer 132 is thus arranged on the first sub-stack 120, i.e. on the channel layer 124. Although FIG. 1c depicts merely two second sacrificial layers 132b of the second sub-stack 130, it is to be understood that the second sub-stack 130 can comprise more than two second sacrificial layers 132b. It is also conceivable that the second sub-stack 130 can comprise one (i.e. a single) second sacrificial layer 132b.

[0085] The third sub-stack 140 comprises a channel layer 144 and a first sacrificial layer 142a on the channel layer 144. The channel layer 144 forms a bottom (i.e. bottom-most) layer of the third sub-stack 140. The channel layer 144 is thus arranged on the second sub-stack 130, i.e. on the topmost first sacrificial layer 132a. The channel layer 144 and the first sacrificial layer 142a can be referred to as one unit of the third sub-stack 140. Although FIG. 1c depicts merely one such unit (i.e. a single unit) of the third sub-stack 140, it is to be understood that the third sub-stack 140 can comprise more than merely a single unit. For instance, the third sub-stack 140 can comprise two, three, four, or more. units. As such, the third sub-stack 140 can comprise two, three, four, or more first sacrificial layers 142a and two, three, four, or more channel layers 144. In case the third sub-stack 140 comprises a plurality of such units, the units can be consecutively arranged. For instance, the units can be arranged on top of each other.

[0086] The first sacrificial layers 122a, 132a, 142a of the first through third sub-stacks 120, 130, 140, respectively, and the second sacrificial layers of the first through third sub-stacks 120, 130, 140 can be formed with a uniform or at least similar thickness. It is also conceivable that the second sacrificial layers can be formed with a greater thickness than each of the first sacrificial layers 122a, 132a, 142a of the first through third sub-stacks 120, 130, 140, respectively. The total thickness of the second sub-stack 130 can accordingly exceed a thickness of each first sacrificial layer of the first sub-stack 120 and the third sub-stack 140.

[0087] The channel layers 124, 144 of the first sub-stack 120 and the third sub-stack 140, respectively, can be of a uniform or at least similar thickness, e.g. a different or a same thickness as the first sacrificial layers of the layer stack 110.

[0088] By way of example, the channel layers 124, 144 of the first and third sub-stacks 120, 140, respectively, can each be formed with a thickness of 3-10 nm, the first sacrificial layers 122a, 132a, 142a of the first through third sub-stacks 120, 130, 140, respectively, can each be formed with a thickness of 3-10 nm, the second sacrificial layers 132b can be formed with a thickness of 5-30 nm. The total thickness of the second sub-stack 130 can, for example, be 20-50 nm.

[0089] The material of the channel layers (i.e., the channel material) can be Si.sub.1-aGe.sub.a. The first sacrificial material can be Si.sub.1-cGe.sub.c. The second sacrificial material can be Si.sub.1-aGe.sub.a. The values of the subscripts in those material identifiers can be defined as 0a<c<d. For example, the subscript c can be in a range of 0.1 to 0.25. As another example, the subscript d can be in a range of 0.35 to 0.5. In a more specific example, the channel material can be Si (i.e., a=0), the first sacrificial material can be Si.sub.0.75Ge.sub.0.25, and the second sacrificial material can be Si.sub.0.5Ge.sub.0.5. These relative differences in Ge-content facilitate a selective processing (e.g. selective etching) of the different sacrificial layers and the channel layers of the layer stack 110 (and the liner layers discussed in conjunction with FIG. 9a to FIG. 9c).

[0090] The layers of the device layer stack 110 can each be epitaxial layers, for example, layers epitaxially grown using deposition techniques, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). This enables high quality material layers with a degree of control of composition and dimensions.

[0091] The deposited layers can be sequentially formed and subsequently patterned to define an elongated fin-shaped layer stack, extending in the X-direction. The dashed line 110 schematically indicates a contour of the layer stack 110 subsequent to fin patterning and prior to fin recess, described below. While the figures depict only a single layer stack, it is to be understood that a plurality of parallel fin-shaped layer stacks can be formed. Conventional fin patterning techniques can be used, e.g. single patterning techniques such as lithography and etching (litho-etch) or multiple-patterning techniques such as (litho-etch) x, self-aligned double or quadruple patterning (SADP or SAQP).

[0092] The layers of the layer stack 110 can each be formed as nanosheets, e.g. with a width (along Y) to thickness (along Z) ratio greater than 1, such as a width in a range from 10 nm to 30 nm and a thickness in a range from 3 nm to 10 nm. It is also possible to pattern the layer stacks such that the channel layers form nanowire-shaped layers. A nanowire can, by way of example, have a thickness similar to the example nanosheet however with a smaller width, such as 3 nm to 10 nm.

[0093] As shown in FIG. 1a and FIG. 1b, subsequent to the fin patterning, a lower portion of the device layer stack 110 can be surrounded by a shallow trench isolation (STI) 104, e.g., of SiO.sub.2.

[0094] As further shown in FIG. 1a and FIG. 1b, a gate structure 250 in the form of a sacrificial gate body 152 can be formed to extend across the layer stack 110. The gate structure 250 comprises two end surfaces 255, as illustrated. The sacrificial gate body 250, 152 can be formed by depositing a sacrificial gate body material (e.g., amorphous Si) over the layer stack 110 and subsequently patterning the sacrificial gate body 250, 152 therein. While the figures depict only a sacrificial gate body 250, 152, it is to be understood that a plurality of parallel sacrificial gate structures can be formed across the layer stack 110. Conventional patterning techniques can be used, e.g., single patterning techniques such as lithography and etching (litho-etch) or multiple-patterning techniques such as (litho-etch) x, SADP or SAQP.

[0095] On-top of the sacrificial gate body 250, 152 there can be a capping layer 156, for example, formed of one or more layers of hardmask material remaining from the sacrificial gate body patterning.

[0096] As shown in FIG. 1a and FIG. 1b, the layer stack 110 can also comprise a bottom second sacrificial layer 116. The bottom second sacrificial layer 116 can be arranged between the substrate 102 and the first sub-stack 120.

[0097] The bottom second sacrificial layer 116 can be subject to the same processing steps as the second sacrificial layers 132b of the second sub-stack 130 (and the first sacrificial layers of the first sub-stack 120, the second sub-stack 130, and the third sub-stack 140).

[0098] During the manufacturing process for at least some embodiments, the bottom second sacrificial layer 116 can be replaced with dielectric material, for example, replaced with first dielectric material 201, as will be shown later. The dielectric material replacing the bottom second sacrificial layer 116 can form a bottom dielectric isolation for the finished stack of FETs. During the manufacturing process for at least some other embodiments, the bottom second sacrificial layer 116 is not replaced with dielectric material, e.g., is not replaced with first dielectric material 201. Accordingly, a bottom dielectric isolation is not used in some embodiments, and a bottom second sacrificial layer 116 not used in some other embodiments.

[0099] FIG. 1d shows the removal of the second sacrificial layers 132b of the second sub-stack 130. In FIG. 1d, the second sacrificial layers 132b of the second sub-stack 130 have been removed by selectively etching the second sacrificial semiconductor material, thereby forming cavities 135 in the second sub-stack 130. The second sacrificial semiconductor material can be etched using an isotropic etching process (wet or dry), to laterally etch back end surfaces of the second sacrificial layers 132b from opposite ends of the layer stack 110. For example, an HCl-based dry etch can be used to remove second sacrificial layer material, e.g., remove second sacrificial material having higher Ge-content than the first sacrificial material. However, other appropriate etching processes (e.g. wet etching processes) are also known in the art and can also be employed for this purpose.

[0100] After forming the cavities 135, first dielectric material 201 is deposited to fill the cavities 135. First dielectric material 201 having a dielectric constant below 6.5 can be used. The first dielectric material 201 can be or comprise, for example, SiN, or SiOC, or SiOCN, or SiCN.

[0101] The first dielectric material 201 can be deposited to fill the cavities 135 and also cover end surfaces 255 of the gate structure 250, as illustrated in FIG. 1e. In this case, the dielectric free gate surface can be provided by removing first dielectric material 201 from the end surfaces 255 of the gate structure 250, as illustrated in FIG. 1f. This corresponds to the first way of providing a dielectric free gate surface, discussed above.

[0102] Alternatively, the first dielectric material 201 can be deposited by a method which does not deposit on the end surfaces 255 of the gate structure 250. In such a case, the situation illustrated in FIG. 1e may not arise. Instead, the layer stack 110 can look as illustrated in FIG. 1f directly after deposition of the first dielectric material 201, without any need for removing first dielectric material 201 from the end surfaces 255 of the gate structure 250. This corresponds to the second way of providing a dielectric free gate surface, discussed above.

[0103] In the first way of providing a dielectric free gate surface, the first dielectric material 201 can be deposited by a conformal deposition method, such as ALD. Alternatively, the first dielectric material 201 can be deposited by the first CVD method discussed below.

[0104] In the second way of providing a dielectric free gate surface, the first dielectric material 201 can be deposited by a deposition method configured to deposit in cavities 135. Such deposition method can be referred to as a first CVD method.

[0105] The first CVD method can comprise reacting, as a film-forming gas, an oxygen-containing silicon compound gas with a non-oxidizing hydrogen-containing gas in a state in which at least the non-oxidizing hydrogen-containing gas is plasmarized, to form a film of a flowable silanol compound, and subsequently, annealing the film of the flowable silanol compound into the first dielectric material. The oxygen-containing silicon compound gas can comprise Si.sub.O.sub.(OC.sub.mH.sub.n)C.sub.xH.sub.y. The subscripts m, n, and are integers of 1 or more. The subscripts , , x, and y are integers of 0 or more. The subscripts and are not 0 at the same time.

[0106] If first dielectric material 201 has been deposited on the end surfaces 255 of the gate structure 250, it can be removed by etching. For example, any suitable isotropic etching process (wet or dry) for etching the dielectric material (e.g. SiN) can be used.

[0107] FIG. 1g illustrates a second dielectric material 202 being deposited on the dielectric free gate surface. The second dielectric material 202 is herein different from the first dielectric material 201. The second dielectric material 202 can be deposited by a conformal deposition method, such as ALD. The second dielectric material 202 can comprise SiOCN and/or SiOC. The second dielectric material 202 can, as illustrated, also cover ends 111, 112 of the layer stack 110.

[0108] Next, further steps that can be performed to obtain a finished stack of FETs will be discussed, in conjunction with FIG. 2a to FIG. 8b. FIG. 2a and FIG. 2b depict respective cross-sectional views of the layer stack 110 taken along vertical planes B-B (parallel to the XZ-plane) and A-A (parallel to the YZ plane). The cross-sectional views of the subsequent figures correspond to those in FIG. 2a and FIG. 2b unless stated otherwise.

[0109] FIG. 2a and FIG. 2b illustrate that ends 111, 112 of the layer stack 110 can be removed by vertical recessing. Thus, vertical recesses 103 are formed, and these vertical recesses can be called source/drain recesses 103. The vertical recessing can be performed by anisotropic etching, such as dry anisotropic etching. The second dielectric material 202 covering ends 111, 112 of the layer stack 110 can, as illustrated, also be removed by the vertical recessing.

[0110] FIG. 3a and FIG. 3b show that subsequent to forming source/drain recesses 103, end surfaces of the first sacrificial layers 122a, 132a, 142a of the layer stack 110 can be laterally recessed to form recesses 160.

[0111] In FIG. 3a, recesses 160 have been formed in the layer stack 110 by laterally etching back (e.g., along the X-direction and the negative X-direction) end surfaces of each first sacrificial layer of the layer stack 110 from opposite ends of the layer stack 110, by selective etching. The lateral etch back can be achieved by an isotropic etching process. Any suitable dry etching process or wet etching process allowing selective etching of the first sacrificial material can be used (e.g. HCl, or APM). As indicated in FIG. 3a, the extent of the lateral etch back can correspond to a thickness of the first dielectric material 201 on the respective end surfaces 255 of the gate structure 250.

[0112] In FIG. 4a and FIG. 4b, the recesses 160 have been filled with one or more conformally deposited inner spacer materials. Examples of inner spacer materials include conformally deposited dielectric materials, such as an oxide, a nitride or a carbide. In one example, a single inner spacer material (e.g., SiN) can be deposited to fill the recesses 160. In another example, a first inner spacer material (e.g. SiOC) can be deposited to partially fill the recesses 160, and a second inner spacer material (e.g. SiN) can be deposited to fill (by pinch-off) a remaining space in the recesses 160. The inner spacers 162 have been formed in the recesses 160 by subjecting the inner spacer material to an isotropic etching process to remove portions of the inner spacer material deposited outside the recesses 160. Any suitable isotropic etching process (wet or dry) for etching the dielectric material (e.g., SiN or SiN and SiOC) can be used. As shown, the etching can be stopped when end surfaces of the channel layers of the device layer stack 110 are exposed and discrete portions of the inner spacer material remain in the recesses 160 to form the inner spacers 162.

[0113] In FIG. 5a and FIG. 5b, source and drain regions 164 and 166 have been formed on the channel layers of the first sub-stack 120 and the third sub-stack 140, respectively. The source and drain regions 164, 166 have been formed by epitaxially growing semiconductor material on end surfaces of the channel layers exposed at opposite ends of the channel layers.

[0114] The source and drain regions 164 formed on the channel layer end surfaces of the first sub-stack 120 can be of a first conductivity type and the source and drain regions 166 formed on the channel layer end surfaces of the third sub-stack 140 can be of a second opposite conductive type. The first and second conductivity types can be a p-type and an n-type, or vice versa. The doping can be achieved by in-situ doping. Different conductivity types of the source and drain regions 164 and the source and drain regions 166 can be achieved by masking the channel layer end surfaces of the third sub-stack 140 while performing epitaxy on the channel layer end surfaces of the first sub-stack 120. The masking of the channel layer end surfaces of the third sub-stack can, for example, be provided by forming a temporary cover spacer along the third sub-stack. After completing the epitaxy of the source and drain regions 164, the temporary cover spacer can be removed and the source and drain regions 164 can be covered with one or more dielectric materials (e.g. ALD-deposited SiN and an inter-layer dielectric like SiO.sub.2). Epitaxy can then be performed on the channel layer end surfaces of the third sub-stack 140. This, however, is merely one example and other process techniques facilitating forming of the source and drain regions 164, 166 with different conductivity types can also be used instead or in addition to.

[0115] The source and drain regions 164, 166 can, as shown, subsequently be embedded in, or, encapsulated by an insulating layer 170. The insulating layer 170 can be formed of an insulating material, such as an oxide, e.g., SiO.sub.2, or another inter-layer dielectric, deposited, planarized and recessed, e.g., by chemical mechanical polishing (CMP) and/or etch back. The CMP and/or etch back can proceed to also remove any capping layer 156 of the sacrificial gate structure 150. It is also possible, however, to stop the CMP and/or etch back on the capping layer 156 and subsequently open the capping using a separate etch step.

[0116] In FIG. 6a and FIG. 6b, a gate trench 172 has been formed by removing the sacrificial gate body 250, 152 between the opposite second dielectric material 202. Any conventional suitable etching process (isotropic or anisotropic, wet or dry) allowing selective removal of the sacrificial gate body 250, 152 (e.g., of amorphous Si) can be used.

[0117] In FIG. 7a and FIG. 7b, the first sacrificial layers of the device layer stack 110 have been removed by selectively etching the first sacrificial semiconductor material from the gate trench 172. A same type of etching process can be used for this step as during the forming of the recesses 160. By removing the first sacrificial layers, the channel layers of the device layer stack 110 can be released in the sense that upper and lower surfaces thereof can be exposed within the gate trench 172.

[0118] In FIG. 8a and FIG. 8b, a gate stack 180 has replaced the sacrificial gate body 152 and the first sacrificial layers.

[0119] The gate stack 180 comprises a gate dielectric layer (not shown), one or more work function metals (WFMs), and gate fill metal 178. In the following example, a gate stack 180 comprising first 174 and second 176 WFMs will be described. At least two WFMs may be needed for a stack of FETs 1000 comprising both an NFET and a PFET. FIG. 8a and FIG. 8b illustrate a stack of FETs 1000 comprising a first FET 1001 and a second FET 1002. In the illustration, one of the first FET 1001 and the second FET 1002 is an NFET and the other is a PFET. Thus, the stack of FETs 1000 forms a CFET.

[0120] The gate dielectric layer can be conformally deposited in the gate trench 172 to conformally coat the channel layers. The gate dielectric layer can be formed of a conventional a high-k dielectric, such as HfO.sub.2, HfSiO, LaO, AlO, or ZrO.

[0121] Subsequently, the first WFM 174 can be conformally deposited in the gate trench 172. The first WFM 174 can be formed of one or more effective WFMs (e.g., an n-type WFM such as TiAl or TiAlC, and/or a p-type WFM, such as TiN or TaN). The first WFM 174 can thus surround the channel layers of the first sub-stack 120.

[0122] Subsequently, the first WFM 174 can be removed from the channel layers of the third sub-stack 140, e.g., using a block mask as an etch mask. The first WFM 174 surrounding the channel layers of the first sub-stack 120 can remain. The second WFM 176 can then be deposited on the gate dielectric surrounding the channel layers of the third sub-stack 140, and on portions of the first dielectric material 201. The second WFM 176 can thus surround the channel layers of the third sub-stack 140. The second WFM 176 can further surround the first WFM 174 of the first sub-stack 120.

[0123] The gate dielectric layer and/or the first WFM 174 and/or the second WFM 176 can be conformally deposited, e.g., by ALD.

[0124] Subsequently, a gate fill metal 178 (such as W, or Al) can be deposited to fill a remaining space of the gate trench 172. The gate fill metal 176 can, for instance, be deposited by CVD or PVD.

[0125] In the discussion above, a layer stack 110 without liner layers 133 has been used. However, liner layers 133 can be used in some embodiments. Accordingly, neighboring first and second sacrificial layers 132a, 132b of the second sub-stack 130 can be separated by a liner layer 133, the liner layers 133 of the second sub-stack 130 being formed of a semiconductor material different from the first 201 and second 202 sacrificial semiconductor materials.

[0126] FIG. 9a, FIG. 9b, and FIG. 9c illustrate the principle of liner layers 133.

[0127] First, FIG. 9a depicts a cross-sectional view of a layer stack 110 comprising liner layers 133. The layer stack 110 comprises a first sub-stack 120, a second sub-stack 130 on the first sub-stack 120, and a third sub-stack 140 on the second sub-stack 130. The first sub-stack 120 and the third sub-stack 140 can be described analogously to the first sub-stack 120 and third sub-stack 140 discussed in conjunction with FIG. 1a. The second sub-stack 130 can be described analogously to the second sub-stack 130 discussed in conjunction with FIG. 1a, but with the addition of liner layers 133 between neighboring first 132a and second 132b sacrificial layers of the second sub-stack 130. Each liner layer 133 can abut the respective first sacrificial layer 132a and second sacrificial layers 132b that it separates.

[0128] Next, FIG. 9b depicts the first sub-stack 120 (bottom), the second sub-stack 130 (middle) and the third sub-stack 140 (top) in isolation for illustrational clarity.

[0129] As mentioned, the liner layers 133 are formed of a semiconductor material different from the first and second semiconductor materials. For example, the channel material can be Si.sub.1-aGe.sub.a, the liner material can be Si.sub.1-bGe.sub.b, the first sacrificial material can be Si.sub.1-cGe.sub.c, and the second sacrificial material can be Si.sub.1-dGe.sub.a, wherein 0ab<c<d. For example, b can be in a range of 0-0.05. Further, c can be in a range of 0.1-0.25. Further, d can be in a range of 0.35-0.5. In a more specific example, the channel material can be Si (i.e., a=0), the liner material can be Si (i.e., b=0), the first sacrificial material can be Si.sub.0.75Ge.sub.0.25, and the second sacrificial material can be Si.sub.0.5Ge.sub.0.5. These relative differences in Ge-content facilitate a selective processing (e.g., selective etching) of the different sacrificial layers, the liner layers 133, and the channel layers of the layer stack 110.

[0130] Liner layers 133 can be formed by epitaxial growth. Liner layers 133 can be formed with a thickness of 1-5 nm.

[0131] Next, FIG. 9c depicts a cross-sectional view of the layer stack 110 comprising liner layers 133 after removal of the second sacrificial layers 132b of the second sub-stack 130.

[0132] As further shown in FIG. 9c, the liner layers 133 can prevent rounding of the corners of the first sacrificial layers 132a of the second sub-stack 130. As the second sacrificial layers 132b of the second sub-stack 130 are etched, the etchant cannot attack the first sacrificial layers 132a via the cavities 135 formed due to the protective liner layers 133. Thus, the first sacrificial layers 132a of the second sub-stack 130 can only be attacked laterally via the recesses 160 of the second sub-stack 130.

[0133] While some embodiments have been illustrated and described in detail in the appended drawings and the foregoing description, such illustration and description are to be considered illustrative and not restrictive. Other variations to the disclosed embodiments can be understood and effected in practicing the claims, from a study of the drawings, the disclosure, and the appended claims. The mere fact that certain measures or features are recited in mutually different dependent claims does not indicate that a combination of these measures or features cannot be used. Any reference signs in the claims should not be construed as limiting the scope.