Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device

Abstract

A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of the first conductivity type, a third semiconductor layer of the first conductivity type, a fourth semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, gate insulating films, gate electrodes, a first electrode, and a second electrode. When a current flows from the first electrode to the second electrode, a peak light emission intensity at a wavelength close to 390 nm is lower than a peak light emission intensity at a wavelength close to 500 nm.

Claims

1. A silicon carbide semiconductor device, comprising: a silicon carbide semiconductor substrate of a first conductivity type, having a first main surface and a second main surface opposite to each other; a first semiconductor layer of the first conductivity type, provided on the first main surface of the silicon carbide semiconductor substrate, the first semiconductor layer having an impurity concentration lower than an impurity concentration of the silicon carbide semiconductor substrate, the first semiconductor layer having a first surface and a second surface opposite to each other, the second surface facing the silicon carbide semiconductor substrate; a second semiconductor layer of the first conductivity type, provided on the first surface of the first semiconductor layer, the second semiconductor layer having a first surface and a second surface opposite to each other, the second surface of the second semiconductor layer facing the first semiconductor layer; a third semiconductor layer of the first conductivity type, provided on the first surface of the second semiconductor layer, the third semiconductor layer having an impurity concentration lower than the impurity concentration of the silicon carbide semiconductor substrate, the third semiconductor layer having a first layer and a second layer on the first layer, the first layer of the third semiconductor layer facing the second semiconductor layer; a fourth semiconductor layer of a second conductivity type, provided on the second layer of the third semiconductor layer, the fourth semiconductor layer having a first surface and a second surface opposite to each other, the second surface of the fourth semiconductor layer facing the second layer of the third semiconductor layer; a first semiconductor region of the first conductivity type, selectively provided in the fourth semiconductor layer, at the first surface of in the fourth semiconductor layer; a gate electrode provided on at least a portion of a surface of the fourth semiconductor layer, between the third semiconductor layer and the first semiconductor region via a gate insulating film; a first electrode provided on surfaces of the first semiconductor region and the fourth semiconductor layer; and a second electrode provided on the second main surface of the silicon carbide semiconductor substrate, wherein a light generated in response to a current flowing from the first electrode to the second electrode has an intensity profile having a first peak and a second peak respectively approximately at 390 nm and 500 nm, and an intensity at the first peak is lower than an intensity at the second peak, and a portion of the silicon carbide semiconductor substrate, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer each contain injected protons or helium that introduce point defects, and the intensity at the first peak is 1/20 or less of the intensity at the second peak.

2. The silicon carbide semiconductor device according to claim 1, wherein the intensity at the first peak is 1/100 or less of the intensity at the second peak.

3. The silicon carbide semiconductor device according to claim 1, wherein the first layer of the third semiconductor layer has an impurity concentration lower than an impurity concentration of the second layer of the third semiconductor layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a cross-sectional view of a structure of a silicon carbide semiconductor device according to an embodiment.

(2) FIG. 2 is a graph depicting light emission intensity of a body diode after proton irradiation.

(3) FIG. 3 is a graph depicting light emission intensity of the body diode after proton irradiation.

(4) FIG. 4 is a diagram depicting an oxide film, 4H-SiC, and band offset.

(5) FIG. 5 is a graph depicting current dependency of Vth.

(6) FIG. 6 is a cross-sectional view of a state of the silicon carbide semiconductor device according to the embodiment during manufacture.

(7) FIG. 7 is a cross-sectional view of a state of the silicon carbide semiconductor device according to the embodiment during manufacture.

(8) FIG. 8 is a cross-sectional view of a state of the silicon carbide semiconductor device according to the embodiment during manufacture.

(9) FIG. 9 is a cross-sectional view of a state of the silicon carbide semiconductor device according to the embodiment during manufacture.

(10) FIG. 10 is a cross-sectional view of a state of the silicon carbide semiconductor device according to the embodiment during manufacture.

(11) FIG. 11 is a cross-sectional view of a state of the silicon carbide semiconductor device according to the embodiment during manufacture.

(12) FIG. 12 is a cross-sectional view depicting a trench gate structure of a conventional silicon carbide semiconductor device.

DETAILED DESCRIPTION OF THE INVENTION

(13) First, problems associated with the conventional techniques are discussed. The silicon carbide semiconductor device emits light when the body diode is energized and electrons and positive holes recombine. At this time, band edge emission for a wavelength close to 390 nm and light emission for a wavelength close to 500 nm due to the energy level of an impurity by ion implantation occur. Under conditions of high temperature and large current close to the rating of the silicon carbide semiconductor device, the intensity of the band edge emission at a wavelength close to 390 nm increases. Due to this light emission, charge is excited and becomes trapped in an oxide film constituting the gate insulating films 109. As a result, a problem arises in that due to the charge in the oxide film, the threshold voltage (Vth) fluctuates and device characteristics degrade. For example, during operation, the ON resistance may increase and loss may occur.

(14) Embodiments of a silicon carbide semiconductor device and a method of manufacturing a silicon carbide semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present description and accompanying drawings, layers and regions prefixed with n or p mean that majority carriers are electrons or holes. Additionally, + or appended to n or p means that the impurity concentration is higher or lower, respectively, than layers and regions without + or . In the description of the embodiments below and the accompanying drawings, main portions that are identical will be given the same reference numerals and will not be repeatedly described. In the present description, when Miller indices are described, means a bar added to an index immediately after the , and a negative index is expressed by prefixing to the index. Further, with consideration of variation in manufacturing, description indicating the same or equal may be within 5%.

(15) A semiconductor device according to the present invention is configured using a wide band gap semiconductor. In the embodiment, a silicon carbide semiconductor device fabricated (manufactured) using, for example, silicon carbide (SiC) as a wide band gap semiconductor is described taking a trench-type MOSFET 70 as an example. FIG. 1 is a cross-sectional view of a structure of the silicon carbide semiconductor device according to an embodiment. In FIG. 1, only an active region through which a main current of the trench-type MOSFET 70 flows is depicted.

(16) As depicted in FIG. 1, the silicon carbide semiconductor device according to the embodiment is configured using a silicon carbide semiconductor base 18 in which on a first main surface (front surface), for example, a (0001)-plane (Si-face) of an n.sup.+-type silicon carbide substrate (silicon carbide semiconductor substrate of a first conductivity type) 1, an n-type boundary layer (first semiconductor layer of the first conductivity type) 20, a high-concentration n.sup.+-type buffer layer (second semiconductor layer of the first conductivity type) 21, an n.sup.-type silicon carbide epitaxial layer (third semiconductor layer of the first conductivity type) 2, and a p-type base layer (fourth semiconductor layer of a second conductivity type) 6 are sequentially stacked.

(17) In the n.sup.-type silicon carbide epitaxial layer 2, at a first surface thereof opposite to a second surface thereof facing the n.sup.+-type silicon carbide substrate 1, n-type high-concentration regions 5 may be provided. The n-type high-concentration regions 5 are a high-concentration n-type drift layer having an impurity concentration lower than an impurity concentration of the n.sup.+-type silicon carbide substrate 1 and higher than an impurity concentration of the n.sup.-type silicon carbide epitaxial layer 2.

(18) The n-type boundary layer 20 has an impurity concentration lower than the impurity concentration of the n.sup.+-type silicon carbide substrate 1 and, for example, is doped with nitrogen (N). The n-type boundary layer 20 fixes an origin of expansion of stacking faults and is provided so that crystal defects of the n.sup.+-type silicon carbide substrate 1 are not transmitted to the n.sup.-type silicon carbide epitaxial layer 2. The high-concentration n.sup.+-type buffer layer 21 is a highly doped layer, for example, doped with nitrogen at a high concentration.

(19) In the trench-type MOSFET 70 of the embodiment, a particle beam of protons (p), helium (He), etc. is irradiated from a back surface, whereby point defects 22 are introduced in a range from the substrate (the n.sup.+-type silicon carbide substrate 1) to the drift layer (the n.sup.-type silicon carbide epitaxial layer 2). The point defects 22 are recombination centers, a percentage of light emission at a wavelength close to 500 nm increases, and light emission during body diode conduction (when current flows from a source electrode 12 to a back electrode 13) shifts to a long wavelength side. As a result, in the trench-type MOSFET 70 of the embodiment, during body diode conduction, a peak light emission intensity (maximum intensity) of a wavelength close to 390 nm is lower than a peak light emission intensity (maximum intensity) of a wavelength close to 500 nm. For example, under a condition of 100 degrees C., when the body diode is conducted, the peak light emission intensity at a wavelength close to 390 nm may be preferably 1/20 of the peak light emission intensity at a wavelength close to 500 nm and more preferably may be 1/100. Suppression of light emission at a wavelength close to 390 nm of a high energy in this manner may suppress the trapping of charge in a SiO.sub.2 oxide film, thereby suppressing fluctuation of Vth and stabilizing device characteristics.

(20) FIGS. 2 and 3 are graphs depicting light emission intensity of the body diode after proton irradiation. FIGS. 2 and 3 depict results measured at a temperature of 100 degrees C. when an irradiation amount of the protons is set to 110.sup.10/cm.sup.2, 10.sup.11/cm.sup.2, 510.sup.11/cm.sup.2, 110.sup.12/cm.sup.2, and 510.sup.12/cm.sup.2, and a current at a current density of 300 A/cm.sup.2 is passed through the body diode in which the point defects 22 have been introduced. In FIG. 2, a horizontal axis depicts wavelength of light emitted from the body diode in units of nm. A vertical axis depicts light emission count/light intensity emitted from the body diode in units of light emission count. In FIG. 3, a horizontal axis depicts the proton irradiation amount/cm.sup.2. A vertical axis depicts the intensity of light emitted from the body diode in units of light emission count.

(21) As depicted in FIGS. 2 and 3, as the proton irradiation amount increases and the concentration of the point defects 22 increases, the light emission percentage at a wavelength close to 390 nm decreases, and the light emission percentage at a wavelength close to 500 nm increases. From the results in FIGS. 2 and 3, the proton irradiation amount may be preferably at least 510.sup.11/cm.sup.2 at which light emission at a wavelength close to 390 nm is nearly 0. Here, while an instance in which the point defects 22 due to proton irradiation is depicted, an instance in which the point defects 22 are due to helium irradiation is similar hereto.

(22) FIG. 4 is a diagram depicting an oxide film, 4H-SiC, and band offset. Here, while an instance is depicted in which a side surface of a trench is an m-plane, another plane is similar hereto. As depicted in FIG. 4, band offset between 4-layer periodic hexagonal crystal silicon carbide (4H-SiC) and the SiO.sub.2 oxide film constituting gate insulating films 9 is about 2.49 eV (498 nm). Therefore, in the light emission at a wavelength close to 390 nm of high energy, charge is easily trapped in the SiO.sub.2 oxide film while in the light emission at a wavelength close to 500 nm of low energy, charge is not easily trapped in the SiO.sub.2 oxide film.

(23) FIG. 5 is a graph depicting current dependency of Vth. In FIG. 5, measurement results of a pulse width modulation (PWM) drive test at a temperature of 130 degrees C. when currents of 20 A and 48 A are passed through the body diode are depicted. In FIG. 5, a horizontal axis depicts test time in units of h. A horizontal axis depicts threshold voltage fluctuation (Vth) in units of V.

(24) As depicted in FIG. 5, fluctuation of the threshold voltage decreases as the current is reduced. Further, the light emission intensity of the body diode is current dependent and when the current is reduced, the light emission intensity of the body diode decreases. This result is suggestive that fluctuation of the threshold voltage may be suppressed by reducing the light emission intensity of the body diode. In an instance in which the point defects 22 are introduced, recombination at defect energy levels occurs, whereby fluctuation of the threshold voltage may be reduced since it is possible to reduce the light emission intensity of the body diode for a wavelength of 390 nm.

(25) On a second main surface (the back surface, i.e., the back surface of the silicon carbide semiconductor base 18) of the n.sup.+-type silicon carbide substrate 1, the back electrode 13 constituting the drain electrode is provided. On a surface of the back electrode 13, a drain electrode pad (not depicted) is provided.

(26) At a first main surface side (side having the p-type base layer 6) of the silicon carbide semiconductor base 18, the trench structure is formed. In particular, trenches 16 penetrate through the p-type base layer 6 from a first surface (the first main surface side of the silicon carbide semiconductor base 18) of the p-type base layer 6 opposite to a second surface thereof facing the n.sup.+-type silicon carbide substrate 1 and reach the n-type high-concentration regions 5 (in an instance in which the n-type high-concentration regions 5 are omitted, the n.sup.-type silicon carbide epitaxial layer 2, hereinafter, indicated simply as (2)). Along inner walls of the trenches 16, the gate insulating films 9 are formed on sidewalls and bottoms of the trenches 16, and gate electrodes 10 are formed on the gate insulating films 9 in the trenches 16. The gate electrodes 10 are insulated from the n-type high-concentration regions 5 (2) and the p-type base layer 6 by the gate insulating films 9. The gate electrodes 10 may partially protrude toward the source electrode 12, from tops (respective sides on which the later-described source electrode 12 is provided) of the trenches 16.

(27) In a surface layer of each of the n-type high-concentration regions 5 (2), at a first side (the first main surface side of the silicon carbide semiconductor base 18) thereof opposite to a second side thereof facing the n.sup.+-type silicon carbide substrate 1, first p.sup.+-type base regions 3 are provided between the trenches 16. Further, second p.sup.+-type base regions 4 respectively in contact with the bottoms of the trenches 16 are provided in the n-type high-concentration regions 5 (2). The second p.sup.+-type base regions 4 are provided at positions facing the bottoms of the trenches 16 in a depth direction (a direction from the source electrode 12 to the drain electrode 13). A width of the second p.sup.+-type base regions 4 is wider than a width of the trenches 16. The bottoms of the trenches 16 may respectively reach the second p.sup.+-type base regions 4 or may be positioned in the n-type high-concentration regions 5 (2), between the p-type base layer 6 and the second p.sup.+-type base regions 4, respectively.

(28) In the p-type base layer 6, n.sup.+-type source regions (first semiconductor regions of the first conductivity type) 7 are selectively provided at the first main surface side of the silicon carbide semiconductor base 18. Further, p.sup.+-type contact regions 8 may be selectively provided. Further, the n.sup.+-type source regions 7 and the p.sup.+-type contact regions 8 are in contact with one another.

(29) An interlayer insulating film 11 is provided in an entire area of the first main surface side of the silicon carbide semiconductor base 18 so as to cover the gate electrodes 10 embedded in the trenches 16. The source electrode 12 is in contact with the n.sup.+-type source regions 7 and the p-type base layer 6 via contact holes opened in the interlayer insulating film 11. Further, in an instance in which the p.sup.+-type contact regions 8 are provided, the source electrode 12 is in contact with the n.sup.+-type source regions 7, the p-type base layer 6, and the p.sup.+-type contact regions 8. The source electrode 12 is electrically insulated from the gate electrodes 10 by the interlayer insulating film 11. On the source electrode 12, a source electrode pad (not depicted) is provided. Between the source electrode 12 and the interlayer insulating film 11, for example, a barrier metal 14 that prevents diffusion of metal atoms from the source electrode 12 to the gate electrodes 10 may be provided.

(30) Next, a method of manufacturing a silicon carbide semiconductor device according to the embodiment is described. FIGS. 6, 7, 8, 9, 10, and 11 are cross-sectional views of states of the silicon carbide semiconductor device according to the embodiment during manufacture.

(31) First, the n.sup.+-type silicon carbide substrate 1 containing an n-type silicon carbide is prepared. The n.sup.+-type silicon carbide substrate 1 is, for example, about 5.010.sup.18/cm.sup.3. Further, on the first main surface of the n.sup.+-type silicon carbide substrate 1, the n-type boundary layer 20 containing silicon carbide is epitaxially grown and has a thickness of, for example, about 5 m while an n-type impurity, for example, nitrogen atoms (N) is doped.

(32) Next, on the surface of the n-type boundary layer 20, the high-concentration n.sup.+-type buffer layer 21 containing silicon carbide is epitaxially grown and has a thickness in range, for example, from 1 m to 5 m while an n-type impurity, for example, nitrogen atoms (N) is doped.

(33) Next, on the surface of the high-concentration n.sup.+-type buffer layer 21, a lower n.sup.-type silicon carbide epitaxial layer 2a is epitaxially grown and has a thickness of, for example, about 30 m while an n-type impurity, for example, nitrogen atoms (N) is doped. The state up to here is depicted in FIG. 6.

(34) Next, on the surface of the lower n.sup.-type silicon carbide epitaxial layer 2a, an ion implantation mask having predetermined openings is formed by a photolithographic technique using, for example, an oxide film. Subsequently, a p-type impurity such as aluminum is implanted in the openings of the oxide film, thereby forming lower first p.sup.+-type base regions 3a and the second p.sup.+-type base regions 4 at a depth of about 0.5 m.

(35) Next, the ion plantation mask may be partially removed, an n-type impurity such as nitrogen may be ion-implanted in the openings, whereby in a portion of a surface region of the lower n.sup.-type silicon carbide epitaxial layer 2a, for example, lower n-type high-concentration regions 5a of a depth of about 0.5 m may be formed. An impurity concentration of the lower n-type high-concentration regions 5a may be set to be, for example, about 110.sup.17/cm.sup.3. The state up to here is depicted in FIG. 7.

(36) Next, on the surface of the lower n.sup.-type silicon carbide epitaxial layer 2a, an upper n.sup.-type silicon carbide epitaxial layer 2b doped with an n-type impurity such as nitrogen is formed and has a thickness of about 0.5 m. An impurity concentration of the upper n.sup.-type silicon carbide epitaxial layer 2b is set to be about 310.sup.15/cm.sup.3. Hereinafter, the lower n.sup.-type silicon carbide epitaxial layer 2a and the upper n.sup.-type silicon carbide epitaxial layer 2b constitute the n.sup.-type silicon carbide epitaxial layer 2.

(37) Next, on the surface of the upper n.sup.-type silicon carbide epitaxial layer 2b, an ion implantation mask having predetermined openings is formed by photolithography using, for example, an oxide film. Subsequently, a p-type impurity such as aluminum is implanted in openings of the oxide film, thereby forming upper first p.sup.+-type base regions 3b at a depth of about 0.5 m, overlapping the lower first p.sup.+-type base regions 3a, respectively. The lower first p.sup.+-type base regions 3a and the upper first p.sup.+-type base regions 3b form continuous regions constituting the first p.sup.+-type base regions 3. An impurity concentration of the upper first p.sup.+-type base regions 3b is set to be, for example, about 510.sup.18/cm.sup.3.

(38) Next, the ion plantation mask may be partially removed, an n-type impurity such as nitrogen may be ion-implanted in the openings, whereby in a portion of a surface region of the n.sup.-type silicon carbide epitaxial layer 2, for example, upper n-type high-concentration regions 5b at a depth of about 0.5 m may be formed. An of impurity concentration the upper n-type high-concentration regions 5b may be set to be, for example, about 110.sup.17/cm.sup.3. The upper n-type high-concentration regions 5b and the lower n-type high-concentration regions 5a are formed so as to at least partially be in contact with one another, thereby forming the n-type high-concentration regions 5. However, the n-type high-concentration regions 5 may be formed in an entire area of the substrate surface or may be formed only in the active region while a voltage withstanding structure region of an outer periphery of the active region is free of the n-type high-concentration regions 5. The state up to here is depicted in FIG. 8.

(39) Next, on the surface of the n.sup.-type silicon carbide epitaxial layer 2, the p-type base layer 6 is formed by epitaxial growth and has a thickness of about 1.1 m. An impurity concentration of the p-type base layer 6 is set to be about 3.510.sup.16/cm.sup.3. After the p-type base layer 6 is formed by epitaxial growth, a p-type impurity such as aluminum may be further ion-implanted in the p-type base layer 6.

(40) Next, in a first main surface layer (surface layer of the p-type base layer 6) of the silicon carbide semiconductor base 18, predetermined regions configuring the MOS gates are formed. In particular, on the surface of the p-type base layer 6, an ion implantation mask having predetermined openings is formed by photolithography using, for example, an oxide film. An n-type impurity such as nitrogen (N) or phosphorus (P) is ion-implanted in the openings, whereby the n.sup.+-type source regions 7 are formed in portions of the p-type base layer 6, at the surface of the p-type base layer 6. Next, the ion plantation mask used to form the n.sup.+-type source regions 7 is removed and by a similar method, an ion implantation mask having predetermined openings may be formed, a p-type impurity such as boron may be ion-implanted in a portion of the p-type base layer 6, at the surface of the p-type base layer 6, whereby the p.sup.+-type contact regions 8 may be formed. An impurity concentration of the p.sup.+-type contact regions 8 may set to be higher than the impurity concentration of the p-type base layer 6.

(41) Next, a heat treatment (activation annealing) for activating all the regions formed by ion implantation is performed. For example, a heat treatment (annealing) under an inert gas atmosphere at about 1700 degrees C. is performed, thereby implementing an activation treatment for the first p.sup.+-type base regions 3, the second p.sup.+-type base regions 4, the n.sup.+-type source regions 7, and the p.sup.+-type contact regions 8. As described above, the ion implanted regions may be collectively activated by a single session of the heat treatment or the heat treatment may be performed each time ion implantation is performed. The state up to here is depicted in FIG. 9.

(42) Next, on the surface of the p-type base layer 6, a trench forming mask having predetermined openings is formed by photolithography using, for example, an oxide film. Next, the trenches 16 penetrating through the p-type base layer 6 and reaching the n-type high-concentration regions 5 (2) are formed by dry etching. The bottoms of the trenches 16 may respectively reach the second p.sup.+-type base regions 4 formed in the n-type high-concentration regions 5 (2). Next, the trench forming mask is removed.

(43) Next, the gate insulating films 9 are formed along the surfaces of the n.sup.+-type source regions 7 and the p.sup.+-type contact regions 8, and along the bottom and the sidewalls of the trenches 16. The gate insulating films 9 may be formed by thermal oxidation at a temperature of about 1000 degrees C. under an oxygen atmosphere. Further, the gate insulating films 9 may be formed by a deposition method by a chemical reaction such as that for a high temperature oxide (HTO). The state up to here is depicted in FIG. 10.

(44) Next, on the gate insulating films 9, for example, a polycrystalline silicon layer doped with phosphorous atoms is provided. The polycrystalline silicon layer may be formed so as to be embedded in the trenches 16. The polycrystalline silicon layer is patterned by photolithography and left in the trenches 16, whereby the gate electrodes 10 are formed.

(45) Next, for example, phosphate glass is deposited so as to cover the gate insulating films 9 and the gate electrodes 10 and has a thickness of about 1 m, whereby the interlayer insulating film 11 is formed. Next, the barrier metal 14 containing titanium (Ti) or titanium nitride (TiN) may be formed so as to cover the interlayer insulating film 11. The interlayer insulating film 11 and the gate insulating films 9 are patterned by photolithography, whereby contact holes exposing the n.sup.+-type source regions 7 and the p.sup.+-type contact regions 8 are formed. Thereafter, a heat treatment (reflow) is performed, whereby the interlayer insulating film 11 is planarized.

(46) Next, the interlayer insulating film 11 is selectively removed and a nickel (Ni) or a Ti film is deposited on the surface of the silicon carbide semiconductor base 18. Next, the surface is protected and a Ni or a Ti film is deposited on the back surface of the n.sup.+-type silicon carbide substrate 1. Next, a heat treatment of about 1000 degrees C. is performed, whereby an ohmic electrode on the surface of the silicon carbide semiconductor base 18 and an ohmic electrode on the back surface of the n.sup.+-type silicon carbide substrate 1 are formed.

(47) Next, a particle beam irradiation 23 is performed from the back surface side of the n.sup.+-type silicon carbide substrate 1. The particle beam irradiation 23 irradiates protons. The irradiation amount of the protons may be preferably at least 510.sup.11/cm.sup.2. Alternatively, instead of protons, helium may be irradiated. The particle beam irradiation 23 is performed from the substrate so as to introduce the point defects 22 in the drift region. The point defects 22 disappear at a temperature of at least 500 degrees C. and therefore, the particle beam irradiation 23 is performed after the activation annealing. Here, while the particle beam irradiation 23 is performed after an annealing treatment for forming a nickel silicide is performed, the particle beam irradiation 23 may be performed after an annealing treatment for forming the trenches 16. Further, the particle beam irradiation 23 may be preferably performed from the back surface side of the silicon carbide semiconductor base 18. In this instance, effects of the particle beam irradiation 23 on the gate electrodes 10 may be reduced. The state up to here is depicted in FIG. 11.

(48) Next, a conductive film constituting the source electrode 12 is provided on the interlayer insulating film 11 so as to be in contact with the ohmic electrode portion formed in the contact holes, thereby bringing the n.sup.+-type source regions 7 and the p.sup.+-type contact regions 8 in contact with the source electrode 12.

(49) Subsequently, the back electrode 13 constituted by, for example, a nickel (Ni) film is formed on the second main surface of the n.sup.+-type silicon carbide substrate 1. Thereafter, for example, a heat treatment is performed at a temperature of about 970 degrees C., thereby forming an ohmic contact between the n.sup.+-type silicon carbide substrate 1 and the back electrode 13.

(50) Next, for example, by a sputtering method, an electrode pad constituting the source electrode pad (not depicted) is deposited on the source electrode 12 on the front surface of the silicon carbide semiconductor base 18 and in the openings of the interlayer insulating film 11. A thickness of a portion of the electrode pad on the interlayer insulating film 11 may be, for example, 5 m. The electrode pad may be formed to contain, for example, aluminum (AlSi) containing silicon at a rate of 1%. Next, the source electrode pad is selectively removed.

(51) Next, for example, titanium (Ti), nickel (Ni), and gold (Au) are sequentially deposited on the surface of the back electrode 13 as the drain electrode pad (not depicted). As described above, the silicon carbide semiconductor device depicted in FIG. 1 is completed.

(52) As described above, according to the embodiment, point defects are introduced in a range from the substrate to the drift layer. As a result, during body diode conduction, the peak light emission intensity at a wavelength close to 390 nm (an intensity at a first peak) is less than the peak light emission intensity at a wavelength close to 500 nm (an intensity at a second peak). Therefore, the trapping of charge in the SiO.sub.2 oxide film may be suppressed, fluctuation of Vth is suppressed, and device characteristics are stabilized. Further, particle beam irradiation is performed from the back surface side of the silicon carbide substrate to form the point defects. As a result, effects of the particle beam irradiation on the gate electrodes may be reduced.

(53) In the foregoing, the present invention may be variously modified within a range not departing from the spirit of the invention and, for example, in the embodiments described above, dimensions, impurity concentrations, etc. of parts may be variously set according to necessary specifications. Further, in the embodiments described above, while description is given taking a trench-gate-type vertical MOSFET as an example, application is further possible to PiN diodes, insulated gate bipolar transistors (IGBTs), etc. Further, in the embodiments, while the first conductivity type is an n-type and the second conductivity type is a p-type, the present invention is similarly implemented when the first conductivity type is a p-type and the second conductivity type is an n-type.

(54) According to the described invention, point defects are introduced in a range from the substrate to the drift layer. As a result, during body diode conduction, the peak light emission intensity at a wavelength close to 390 nm is less than the peak light emission intensity at a wavelength close to 500 nm. Therefore, the trapping of charge in the SiO.sub.2 oxide film may be suppressed, fluctuation of Vth is suppressed, and device characteristics are stabilized. Further, the particle beam irradiation is performed from the back surface side of the silicon carbide substrate to form the point defects. As a result, effects of the particle beam irradiation on the gate electrodes may be reduced.

(55) The silicon carbide semiconductor device and the method of manufacturing a silicon carbide semiconductor device according to the present invention achieve an effect in that the trapping of charge in the oxide film is reduced, whereby fluctuation of Vth is suppressed, and device characteristics may be stabilized.

(56) As described above, the silicon carbide semiconductor device and the method of manufacturing a silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power converting equipment such as inverters, power source devices of various industrial machines, igniters of vehicles, etc.

(57) Although the invention has been described with respect to a specific embodiment for a complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modifications and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.