Insulated gate bipolar transistor device

Abstract

An IGBT device includes an p-type collector region, an n-type semiconductor layer, several p-type body regions located in the n-type semiconductor layer, a gate trench located in the n-type semiconductor layer and between adjacent p-type body regions, a gate trench located in the n-type semiconductor layer and between adjacent p-type body regions, a shielded gate located in a lower part of the gate trench, and a gate located in an upper part of the gate trench. The gate, the shielded gate, and the n-type semiconductor layer are insulated and isolated from each other. Among the several p-type body regions, at least one p-type body region has a first doping concentration and is defined as a first p-type body region, and at least one p-type body region has a second doping concentration and is defined as a second p-type body region.

Claims

1. An IGBT device, comprising: a p-type collector region; an n-type semiconductor layer located above the p-type collector region; a plurality of p-type body regions located in the n-type semiconductor layer, wherein an n-type emitter electrode region is disposed in each of the plurality of p-type body regions; and gate trenches each located in the n-type semiconductor layer and between adjacent p-type body regions among the plurality of p-type body regions, shielded gates each located in a lower part of one of the gate trenches, and gates each located in an upper part of one of the gate trenches, wherein each of the gates, each of the shielded gates, and the n-type semiconductor layer are insulated and isolated from each other, wherein among the plurality of p-type body regions, at least one p-type body region has a first doping concentration and is defined as a first p-type body region, and at least one p-type body region has a second doping concentration and is defined as a second p-type body region; and the first doping concentration of the first p-type body region is smaller than the second doping concentration of the second p-type body region; and wherein at least one of the shielded gates in at least one of the gate trenches adjacent to one first p-type body region is externally connected to a gate voltage, and a shielded gate in a gate trench, which is other than the at least one gate trench where the at least one shielded gate externally connected to the gate voltage, is located is externally connected to an emitter electrode voltage.

2. The IGBT device according to claim 1, wherein each of the shielded gates extends from the lower part of one of the gate trenches into the upper part of one of the gate trenches.

3. The IGBT device according to claim 2, wherein a width of the upper part of each of the gate trenches is greater than a width of the lower part of the each of the gate trenches.

4. The IGBT device according to claim 3, further comprising n-type charge storage regions located in the n-type semiconductor layers, wherein each of the n-type charge storage regions is located below the gate.

5. The IGBT device according to claim 1, further comprising n-type collector regions, wherein the IGBT device comprises a plurality of p-type collector regions, the n-type collector regions are located below the n-type semiconductor layer, and the n-type collector regions and the plurality of p-type collector regions are disposed alternately.

6. The IGBT device according to claim 1, further comprising an n-type field cutoff region, wherein the n-type field cutoff region is located between the p-type collector region and the n-type semiconductor layer.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a section view of an IGBT device in a first embodiment according to the present application.

(2) FIG. 2 is a section view of an IGBT device in a second embodiment according to the present application.

DETAILED DESCRIPTION

(3) The solution of the present application is described hereinafter through specific implementations in conjunction with drawings in embodiments of the present application. Apparently, the described embodiments are part, not all, of embodiments of the present application. Meanwhile, to illustrate embodiments of the present application clearly, in the schematic views illustrated in BRIEF DESCRIPTION OF DRAWINGS, thicknesses of layers and regions described in the present application are enlarged, and dimensions illustrated in the views do not represent the actual dimensions.

(4) FIG. 1 is a section view of an IGBT device in a first embodiment according to the present application. As shown in FIG. 1, the IGBT device in the present application includes a p-type collector region 20, an n-type semiconductor layer 21 located above the p-type collector region 20, and several p-type body regions 22 located in the n-type semiconductor layer 21. An n-type emitter electrode region 23 is disposed in each p-type body region 22.

(5) The IGBT device also includes a gate trench located in the n-type semiconductor layer 21 and between adjacent p-type body regions 22, a gate 25 located in an upper part of the gate trench, and a shielded gate 27 located in a lower part of the gate trench. The shielded gate 27 may be merely located in the lower part of the gate trench so that the gate 25 and the shielded gate 27 are an upper and lower structure. Optionally, the shielded gate 27 may also be located in the lower part of the gate trench and extend upward into the upper part of the gate trench. FIG. 1 illustrates an example in which the shielded gate 27 is located in the lower part of the gate trench and extends upward into the upper part of the gate trench. Moreover, the width of the upper part of the gate trench may be greater than, equal to, or smaller than the width of the lower part of the gate trench. FIG. 1 illustrates that the width of the upper part of the gate trench is greater than the width of the lower part of the gate trench.

(6) The gate 25, the shielded gate 27, and the n-type semiconductor layer 21 are insulated and isolated from each other. In FIG. 1, the gate 25 is insulated and isolated from the n-type semiconductor layer 21 through a gate dielectric layer 24, and the shielded gate 27 is isolated from the gate 25 and the n-type semiconductor layer 21 through a field oxide layer 26.

(7) In the several p-type body regions 22 in the present application, embodiments of the present application exemplarily show four p-type body regions 22. At least one p-type body region 22 has a first doping concentration and is defined as a first p-type body region 22a. At least one p-type body region 22 has a second doping concentration and is defined as a second p-type body region 22b. The first doping concentration of the first p-type body region 22a is smaller than the second doping concentration of the second p-type body region 22b. FIG. 1 exemplarily illustrates one first p-type body region 22a and three second p-type body regions 22b.

(8) For the IGBT device in the present application, at least one shielded gate 27 in at least one gate trench adjacent to the first p-type body region 22a is externally connected to a gate voltage. A shielded gate 27 in a remaining gate trench is externally connected to an emitter electrode voltage. In FIG. 1, exemplarily, a shielded gate 27 in a gate trench on the right of the first p-type body region 22a and a gate 25 are externally connected to the gate voltage (G). Shielded gates 27 in the remaining gate trenches (that is, gate trenches other than the gate trench where the shielded gate externally connected to the gate voltage is located) and n-type emitter electrode regions 23 are externally connected to the emitter electrode voltage (not shown).

(9) For the IGBT device in the present application, a threshold voltage Vth1 of a current channel in the first p-type body region 22a with the first doping concentration is smaller than a threshold voltage Vth2 of a current channel in the second p-type body region 22b with the second doping concentration. When a shielded gate 27 is externally connected to the gate voltage, a gate 25 in the gate trench has a greater gate charge Qg1. When a shielded gate 27 is externally connected to the emitter electrode voltage, a gate 25 in the gate trench has a smaller gate charge Qg2. The arrangement in which at least one shielded gate 27 in at least one gate trench adjacent to the first p-type body region 22a is externally connected to the gate voltage and a shielded gate 27 in a remaining gate trench is externally connected to the emitter electrode voltage enables the small Vth1 to be combined with the great Qg1 and enables the great Vth2 to be combined with the small Qg2. Accordingly, in a process in which the IGBT device turns off from turning on, a current channel in a region where the great Vth2 is combined with the small Qg2 may turn off rapidly, while a current channel in a region where the small Vth1 is combined with the great Qg1 may turn off later. In this case, when the current channel in the region where the great Vth2 is combined with the small Qg2 just turns off, the current channel in the region where the small Vth1 is combined with the great Qg1 is still in the on state. With a further reduction of the gate voltage Vg, the current channel in the region where the small Vth1 is combined with the great Qg1 turns off. Therefore, as an external manifestation of the IGBT device, a turning-off loss of the region where the small Vth1 is combined with the great Qg1 reduces a turning-off loss of the region where the great Vth2 is combined with the small Qg2, thereby reducing a turning-off loss of the IGBT device entirely.

(10) FIG. 2 is a section view of an IGBT device in a second embodiment according to the present application. As shown in FIG. 2, on the basis of the structure of the IGBT device shown in FIG. 1, the IGBT device in the present application further includes an n-type charge storage region 32 located in the n-type semiconductor layer 21. The n-type charge storage region 32 is located below the gate 25. The IGBT device in the present application further includes n-type collector regions 30. The n-type collector regions 30 are located below the n-type semiconductor layer 21. Moreover, the n-type collector regions 30 and the p-type collector regions 20 are disposed alternately: Optionally, the IGBT device in the present application may further include an n-type field cutoff region 31. The n-type field cutoff region 31 is located between the p-type collector region 20 and the n-type semiconductor layer 21. The n-type charge storage region 32, the n-type field cutoff region 31, and the n-type collector region 30 are all known technology and are not described in detail in embodiments of the present application.