SYSTEMS AND METHODS FOR DETECTING CURRENTS OF POWER MANAGEMENT SYSTEMS

Abstract

System and method for detecting one or more currents. For example, a system for detecting one or more currents includes: one or more current sampling units coupled to one or more terminal transistors respectively and configured to sample one or more terminal currents that flow between a system terminal of a power management system and one or more port terminals through the one or more terminal transistors respectively; one or more operational amplifiers coupled to the one or more current sampling units respectively and configured to generate one or more detection currents respectively, the one or more detection currents representing one or more magnitudes of the one or more terminal currents respectively; and a signal combiner configured to receive the one or more detection currents, generate a combined detection voltage representing a sum of the one or more magnitudes of the one or more terminal currents.

Claims

1.-11. (canceled)

12. A system for detecting one or more currents, the system comprising: one or more current sampling units coupled to one or more terminal transistors respectively and configured to sample one or more terminal currents that flow between a system terminal of a power management system and one or more port terminals through the one or more terminal transistors respectively; one or more operational amplifiers coupled to the one or more current sampling units respectively and configured to generate one or more detection currents respectively, the one or more detection currents representing one or more magnitudes of the one or more terminal currents respectively; and a signal combiner configured to receive the one or more detection currents, generate a combined detection voltage representing a sum of the one or more magnitudes of the one or more terminal currents, and output the combined detection voltage to the power management system to regulate the sum of the one or more magnitudes of the one or more terminal currents; wherein: the one or more current sampling units include a first sampling unit; the one or more terminal transistors include a first terminal transistor; the one or more terminal currents include a first terminal current; the one or more port terminals include a first port terminal; the one or more operational amplifiers include a first operational amplifier; the one or more detection currents include a first detection current; and the one or more magnitudes of the one or more terminal currents include a first magnitude of the first terminal current; wherein: the first current sampling unit is coupled to the first terminal transistor and configured to sample the first terminal current that flows between the system terminal of the power management system and the first port terminal through the first terminal transistor; and the first operational amplifier is coupled to the first current sampling unit and configured to generate the first detection current, the first detection current representing the first magnitude of the first terminal current; wherein: the first terminal transistor includes a first transistor terminal, a second transistor terminal, and a third transistor terminal; wherein: the second transistor terminal is connected to the system terminal of the power management system; and the third transistor terminal is connected to the first port terminal; wherein: the first sampling unit includes a first sampling transistor and a second sampling transistor; wherein: the first sampling transistor includes a fourth transistor terminal, a fifth transistor terminal, and a sixth transistor terminal; and the second sampling transistor includes a seventh transistor terminal, an eighth transistor terminal, and a ninth transistor terminal; wherein: the first operational amplifier includes a first amplifier terminal, a second amplifier terminal, and a third amplifier terminal; wherein: the first amplifier terminal is connected to the sixth transistor terminal of the first sampling transistor; and the second amplifier terminal is connected to the ninth transistor terminal of the second sampling transistor; wherein the first operational amplifier further includes: a chopper amplifier; a current mirror coupled to the chopper amplifier; and a digital-to-analog converter coupled to the current mirror.

13. The system of claim 12 wherein the current mirror of the first operational amplifier is configured to output the first detection current.

14. A chopper amplifier comprising: a ground voltage generator configured to receive a first ground voltage and a system voltage and generate a second ground voltage based at least in part on the first ground voltage and the system voltage; a clock signal generator configured to receive an input clock signal, the first ground voltage and the second ground voltage and generate a first clock signal and a second clock signal based at least in part on the input clock signal, the first ground voltage and the second ground voltage; and a chopper and amplification unit including a first chopper unit, a second chopper unit coupled to the first chopper unit through multiple transistors, and a third chopper unit coupled to the second chopper unit through multiple transistors; wherein: the second ground voltage is higher than or equal to the first ground voltage: wherein: if the first clock signal is equal to the first ground voltage, the first clock signal is at a logic low level; and if the second clock signal is equal to the second ground voltage, the second clock signal is at the logic low level: wherein: the first chopper unit is configured to receive the second clock signal; the second chopper unit is configured to receive the second clock signal; and the third chopper unit is configured to receive the first clock signal.

15. The chopper amplifier of claim 14 wherein a clock signal generator includes: a first voltage converter configured to, with one or more other components, convert the input clock signal to the second clock signal; and a second voltage converter configured to, with one or more other components, convert the second clock signal to the first clock signal.

16. The chopper amplifier of claim 14 wherein the ground voltage generator is further configured to: if the system voltage is larger than a predetermined threshold, generate the second ground voltage to be equal to the system voltage minus a predetermined magnitude; and if the system voltage is smaller than the predetermined threshold, generate the second ground voltage to be equal to the first ground voltage.

17.-21. (canceled)

Description

4. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG. 1 is a simplified diagram showing a conventional current detection system as part of a charging system.

[0019] FIG. 2 is a simplified diagram showing a current detection system as part of a charging system according to certain embodiments of the present invention.

[0020] FIG. 3 is a simplified diagram showing certain components of the current sampling unit, the operational amplifier, and the signal combiner of the current detection system as part of the charging system as shown in FIG. 2 according to some embodiments of the present invention.

[0021] FIG. 4 is a simplified diagram showing certain components of the chopper amplifier of the operational amplifier of the current detection system as part of the charging system as shown in FIG. 2 and FIG. 3 according to certain embodiments of the present invention.

[0022] FIG. 5 is a simplified diagram showing certain components of the clock signal generator of the chopper amplifier of the operational amplifier of the current detection system as part of the charging system as shown in FIG. 2, FIG. 3 and FIG. 4 according to certain embodiments of the present invention.

[0023] FIG. 6 is a simplified diagram showing certain components of the virtual ground voltage generator of the chopper amplifier of the operational amplifier of the current detection system as part of the charging system as shown in FIG. 2, FIG. 3 and FIG. 4 according to some embodiments of the present invention.

5. DETAILED DESCRIPTION OF THE INVENTION

[0024] Certain embodiments of the present invention are directed to circuits. More particularly, some embodiments of the invention provide systems and methods for detecting currents. Merely by way of example, some embodiments of the invention have been applied to power management systems. But it would be recognized that the invention has a much broader range of applicability.

[0025] As shown in FIG. 1, for the conventional current detection system, the one or more current sampling resistors 110.sub.1, 110.sub.2, . . . , and 110.sub.N need to be provided for the one or more terminals 190.sub.1, 190.sub.2, . . . , and 190.sub.N respectively according to certain embodiments. For example, the use of the one or more current sampling resistors 110.sub.1, 110.sub.2, . . . , and 110.sub.N increases bill of materials (BOM), increases circuit loss, and/or reduces circuit efficiency. As another example, to reduce circuit loss, each resistor of the one or more resistors 110.sub.1, 110.sub.2, . . . , and 110.sub.N has a small resistance value (e.g., 5 m).

[0026] According to some embodiments, if the resistance value of each resistor of the one or more resistors 110.sub.1, 110.sub.2, . . . , and 110.sub.N is small, when the magnitude of the current 115.sub.i is small, the voltage received by the terminal 122.sub.i minus the voltage received by the terminal 124.sub.i is also small, reducing signal-to-noise ratio and/or reducing detection accuracy for small currents. For example, when the terminal 190.sub.i needs the current 115.sub.i to be small, the conventional current detection system as shown in FIG. 1 often cannot meet the requirements of the charging system 100. As an example, a wide range for the voltage 105 usually further reduces the detection accuracy for small currents, so that the detection accuracy often is worse than 50%.

[0027] FIG. 2 is a simplified diagram showing a current detection system as part of a charging system according to certain embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The current detection system includes one or more current sampling units 210.sub.1, 210.sub.2, . . . , and 210.sub.N, one or more operational amplifiers 220.sub.1, 220.sub.2, . . . , and 220.sub.N, and a signal combiner 230. For example, in addition to the current detection system, the charging system 200 also includes a power management system 202 and one or more transistors 280.sub.1, 280.sub.2, . . . , and 280.sub.N, and one or more terminals 290.sub.1, 290.sub.2, . . . , and 290.sub.N. As an example, the power management system 202 includes a power supply 240, a power converter 250, an output inductor 260, and an output capacitor 270. As shown in FIG. 2, the charging system 200 includes the one or more current sampling units 210.sub.1, 210.sub.2, . . . , and 210.sub.N, the one or more operational amplifiers 220.sub.1, 220.sub.2, . . . , and 220.sub.N, the one or more transistors 280.sub.1, 280.sub.2, . . . , and 280.sub.N, and the one or more terminals 290.sub.1, 290.sub.2, . . . , and 290.sub.N, wherein N is a positive integer, according to some embodiments. For example, N is equal to 1. As an example, N is larger than 1. Although the above has been shown using a selected group of components for the current detection system, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. Further details of these components are found throughout the present specification.

[0028] In certain embodiments, the current detection system is configured to regulate a current 203 that flows out of the power management system 202 at a terminal 204. For example, as part of the power management system 202, the power supply 240 provides a voltage 241 to the power converter 250. As an example, in response, the power converter 250) (e.g., a DC-DC converter) generates a voltage 251, which is used by the output inductor 260 and the output capacitor 270 to generate a voltage 205 at the terminal 204. For example, additionally, the power converter 250 (e.g., a DC-DC converter) also generates a control signal 253. As an example, one terminal of the output capacitor 270 is biased to a ground voltage 271.

[0029] In some embodiments, the terminal 204 is connected to a drain terminal 284.sub.i of the transistor 280.sub.i and an input terminal 212.sub.i of the current sampling unit 210.sub.i, wherein i is an integer larger than or equal to 1 but smaller than or equal to N. For example, the transistor 280.sub.i also includes a gate terminal 282.sub.i and a source terminal 286.sub.i. As an example, the current sampling unit 210.sub.i also includes an input terminal 214.sub.i, an output terminal 216.sub.i, and an output terminal 218.sub.i. In certain examples, the input terminal 214.sub.i of the current sampling unit 210.sub.i is connected to the source terminal 286.sub.i of the transistor 280.sub.i and is also connected to the terminal 290.sub.i (e.g., a port terminal). For example, the port terminal 290.sub.i is used to charge a load device. As an example, the gate terminal 282.sub.i of the transistor 280.sub.i receives a signal 281.sub.i, which is a part of the control signal 253 and is used to turn on and/or turn off the transistor 280.sub.i. In some examples, the output terminal 216.sub.i of the current sampling unit 210.sub.i is connected to an input terminal 222.sub.i (e.g., an + terminal) of the operational amplifier 220.sub.i, and the output terminal 218.sub.i of the current sampling unit 210.sub.i is connected to an input terminal 224.sub.i (e.g., an terminal) of the operational amplifier 220.sub.i. For example, the operational amplifier 220.sub.i also includes an output terminal 226.sub.i.

[0030] According to certain embodiments, the operational amplifier 220.sub.i generates a detection signal 227.sub.i at the output terminal 226.sub.i. For example, the detection signal 227.sub.i represents a magnitude of a current 215.sub.i that flows from the terminal 204 to the terminal 290.sub.i through the transistor 280.sub.i. In some examples, the signal combiner 230 receives the detection signal 227.sub.i and in response generates a combined detection voltage 231. For example, the combined detection voltage 231 represents a sum of the magnitude of the current 215.sub.1, the magnitude of the current 215.sub.2, . . . , and the magnitude of the current 215.sub.N. In certain examples, the sum of the magnitude of the current 215.sub.1, the magnitude of the current 215.sub.2, . . . and the magnitude of the current 215.sub.N is equal to the magnitude of the current 203 that flows out of the power management system 202 at the terminal 204. For example, the combined detection voltage 231 represents the magnitude of the current 203. As an example, the power converter 250 receives the combined detection voltage 231 and uses the combined detection voltage 231 to regulate the magnitude of the current 203 in order to keep the magnitude of the current 203 at a constant level.

[0031] In some examples, the detection signal 227.sub.i is a current that represents a magnitude of the current 215.sub.i that flows from the terminal 204 to the terminal 290.sub.i through the transistor 280.sub.i. For example, the signal combiner 230 receives the detection current 227.sub.1, the detection current 227.sub.2, . . . , and the detection current 227.sub.N and generates a combined detection current that is equal to a sum of the detection current 227.sub.1, the detection current 227.sub.2, . . . , and the detection current 227.sub.N. As an example, the combined detection current flows through a resistor that is a part of the signal combiner 230 to convert the combined detection current to the combined detection voltage 231.

[0032] According to some embodiments, as shown in FIG. 2, the current detection system is used to establish a stable magnitude for the current 203 that flows out of the power management system 202 by detecting the one or more currents 215.sub.1, 215.sub.2, . . . , and 215.sub.N to generate the one or more detection voltages 227.sub.1, 227.sub.2, . . . , and 227.sub.N, combining the one or more detection voltages 227.sub.1, 227.sub.2, . . . , and 227.sub.N to generate the combined detection voltage 231, and providing the combined detection voltage 231 to the main loop in order to regulate the magnitude of the current 203. For example, the current sampling unit 210.sub.i uses the input terminals 212.sub.i and 214.sub.i to sample the current 215.sub.i that flows from the terminal 204 to the terminal 290.sub.i through the transistor 280.sub.i. As an example, the operational amplifier 220.sub.i in response generates the detection signal 227.sub.i, which represents the magnitude of the current 215.sub.i that flows from the terminal 204 to the terminal 290.sub.i through the transistor 280.sub.i.

[0033] In certain embodiments, the operational amplifier 220.sub.i is configured to perform a chopper function and/or amply a current with a predetermined constant ratio. For example, the operational amplifier 220.sub.i includes a chopper amplifier that is configured to process high voltages and also includes a digital-to-analog converter (DAC).

[0034] As discussed above and further emphasized here. FIG. 2 is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. In some embodiments. N is equal to 1. For example, the charging system 200 includes the current sampling unit 210.sub.1, the operational amplifier 220.sub.1, the transistors 280, and the terminal 290.sub.1. As an example, i is equal to 1, and i cannot be larger than 1. In certain embodiments, the current detection system is used to detect a current that is received by the power management system 202. For example, the power management system 202 does not include the power supply 240, which is external to the power management system 202. In some embodiments, if the DC-DC converter 250) is replaced by an AC-DC converter, the output inductor 260 is replaced by a transformer and the output capacitor 270 is replaced by a rectifier circuit on the secondary side.

[0035] FIG. 3 is a simplified diagram showing certain components of the current sampling unit 210.sub.i, the operational amplifier 220.sub.i, and the signal combiner 230 of the current detection system as part of the charging system 200 as shown in FIG. 2 according to some embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The current sampling unit 210.sub.i includes a transistor 310.sub.i and a transistor 320.sub.i. The operational amplifier 220.sub.i includes a chopper amplifier 330.sub.i, a transistor 340.sub.i, a transistor 342.sub.i, a transistor 344.sub.i, a transistor 346.sub.i, and a digital-to-analog converter (DAC) 350.sub.i. The signal combiner 230 includes a current combiner 360 and a resistor 370. For example, i is an integer larger than or equal to 1 but smaller than or equal to N. As an example, N is a positive integer. Although the above has been shown using a selected group of components for the current detection system, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. Further details of these components are found throughout the present specification.

[0036] In certain embodiments, the current sampling unit 210; includes the transistor 310.sub.i (e.g., a field-effect transistor) and the transistor 320.sub.i. (e.g., a field-effect transistor). For example, a drain terminal of the transistor 310.sub.i is connected to the source terminal 286.sub.i of the transistor 280.sub.i and the terminal 290.sub.i, and a drain terminal of the transistor 320.sub.i is connected to the drain terminal 284.sub.i of the transistor 280.sub.i and the terminal 204. As an example, the gate terminal of the transistor 310.sub.i and the gate terminal of the transistor 320.sub.i are connected to the gate terminal 282.sub.i of the transistor 280.sub.i. In some examples, the gate terminal of the transistor 310.sub.i, the gate terminal of the transistor 320.sub.i, and the gate terminal 282.sub.i of the transistor 280.sub.i all receive the signal 281.sub.i. For example, the transistor 310.sub.i, the transistor 320.sub.i, and the transistor 280.sub.i are all turned on if the signal 281.sub.i is at a logic high level. As an example, the transistor 310.sub.i, the transistor 320.sub.i, and the transistor 280.sub.i are all turned off if the signal 281.sub.i is at a logic low level. In certain examples, the source terminal of the transistor 310.sub.i is connected to an inverting input terminal 332.sub.i (e.g., the terminal) of the chopper amplifier 330.sub.i, and the source terminal of the transistor 320.sub.i is connected to a non-inverting input terminal 334.sub.i (e.g., the + terminal) of the chopper amplifier 330.sub.i. For example, the transistor 280.sub.i, the transistor 310.sub.i and the transistor 320.sub.i each are an NMOS transistor. As an example, the size of the transistor 310.sub.i and the size of the transistor 320.sub.i are the same, equal to the size of the transistor 280.sub.i multiplied by a predetermined ratio.

[0037] In some embodiments, the chopper amplifier 330.sub.i also includes an output terminal 336.sub.i. For example, the output terminal 336.sub.i of the chopper amplifier 330.sub.i is connected to a gate terminal of the transistor 340.sub.i, which also includes a drain terminal and a source terminal. As an example, the drain terminal of the transistor 340.sub.i is connected to the source terminal of the transistor 320.sub.i and the non-inverting input terminal 334.sub.i (e.g., the + terminal) of the chopper amplifier 330.sub.i, and the source terminal of the transistor 340.sub.i is connected to a drain terminal and a gate terminal of the transistor 342.sub.i. In certain examples, the gate terminal of the transistor 342.sub.i is also connected to a terminal 352.sub.i of the digital-to-analog converter (DAC) 350.sub.i, which also includes a terminal 354.sub.i and a terminal 356.sub.i. For example, the terminal 356.sub.i of the digital-to-analog converter (DAC) 350.sub.i and a source terminal of the transistor 342.sub.i are biased to the ground voltage 271. As an example, the terminal 354.sub.i of the digital-to-analog converter (DAC) 350.sub.i are connected to a drain terminal and a gate terminal of the transistor 344.sub.i. In some examples, the gate terminal of the transistor 344.sub.i is also connected to a gate terminal of the transistor 346.sub.i. For example, a source terminal of the transistor 344.sub.i and a source terminal of the transistor 346.sub.i both are biased to a supply voltage 391. As an example, a drain terminal of the transistor 346.sub.i provides a detection signal 227.sub.i, which is a current that flows out of the drain terminal of the transistor 346.sub.i.

[0038] According to certain embodiments, the chopper amplifier 330.sub.i operates in a closed loop with transistor 340.sub.i so that the inverting input terminal 332.sub.i (e.g., the terminal) and the non-inverting input terminal 334.sub.i (e.g., the + terminal) of the chopper amplifier 330.sub.i are at the same voltage level. For example, the non-inverting input terminal 334.sub.i (e.g., the + terminal) of the chopper amplifier 330.sub.i serves as the input terminal 222.sub.i (e.g., the + terminal) of the operational amplifier 220.sub.i. As an example, the inverting input terminal 332.sub.i (e.g., the terminal) of the chopper amplifier 330.sub.i serves as the input terminal 224.sub.i (e.g., the terminal) of the operational amplifier 220.sub.i. In some examples, a current 337.sub.i that flows through the transistor 340.sub.i is equal to the current 215.sub.i multiplied by a predetermined constant. For example, the current 337.sub.i is a sampling current of the current 215.sub.i. In certain examples, the transistor 340.sub.i, the transistor 342.sub.i, the transistor 344.sub.i, and the transistor 346.sub.i are parts of a current mirror. For example, the current mirror receives a current 337.sub.i and generates the detection current 227.sub.i.

[0039] According to some embodiments, the detection current 227.sub.i is determined as follows:

[00001]$\begin{array}{cc}{I}_{227i}=\frac{I_{215i}{R}_{\mathrm{oni}}}{R_{\mathrm{snsi}}}{}_i=\frac{I_{215i}}{N_i}{}_i& \left(\mathrm{Equation}1\right)\end{array}$

where I.sub.227i represents the detection current 227.sub.i, and I.sub.215i represents the current 215.sub.i. Additionally, Roni represents the on resistance of the transistor 280.sub.i, and R.sub.snsi represents the on resistance of the transistor 310.sub.i or the on resistance of the transistor 320.sub.i, wherein the on resistance of the transistor 310.sub.i and the on resistance of the transistor 320.sub.i are equal. Moreover, N.sub.i represents a ratio of the size of the transistor 280.sub.i to the size of the transistor 310.sub.i or a ratio of the size of the transistor 280.sub.i to the size of the transistor 320.sub.i, wherein the size of the transistor 310.sub.i and the size of the transistor 320.sub.i are equal. Also, .sub.i represents the current ratio of the current mirror that includes the transistor 340.sub.i, the transistor 342.sub.i, the transistor 344.sub.i, and the transistor 346.sub.i.

[0040] In certain examples, the current ratio ci of the current mirror is equal to the detection current 227.sub.i divided by the current 337.sub.i. For example, the current ratio .sub.i of the current mirror is adjusted by the digital-to-analog converter (DAC) 350.sub.i. In some examples, as shown by Equation 1, the detection current 227.sub.i depends on the ratio N.sub.i of the size of the transistor 280.sub.i to the size of the transistor 310.sub.i or of the size of the transistor 280.sub.i to the size of the transistor 320.sub.i and also depends on the current ratio .sub.i of the current mirror that includes the transistor 340.sub.i, the transistor 342.sub.i, the transistor 344.sub.i, and the transistor 346.sub.i.

[0041] In some examples, the signal combiner 230 includes the current combiner 360 and the resistor 370. For example, the current combiner 360 receives the one or more detection currents 227.sub.1, 227.sub.2, . . . , and 227.sub.N and generate a combined current 361. As an example, the combined current 361 is determined as follows:

[00002]$\begin{array}{cc}{I}_{361}={.Math.}_{i=1}^N{I}_{227i}& \left(\mathrm{Equation}2\right)\end{array}$

where I.sub.361 represents the combined current 361, and I.sub.227i represents the detection current 227.sub.i. For example, N is equal to 1. As an example, N is a positive integer larger than 1.

[0042] As shown in FIG. 3, the combined current 361 flows through the resistor 370 to generate the combined detection voltage 231 according to certain embodiments. In some examples, the combined detection voltage 231 is determined as follows:

[00003]$\begin{array}{cc}{V}_{231}=I_{361}{R}_{370}=\left({.Math.}_{i=1}^N{I}_{227i}\right)R_{370}& \left(\mathrm{Equation}3\right)\end{array}$

where V.sub.231 represents the combined detection voltage 231, and I.sub.361 represents the combined current 361. Additionally, R.sub.370 represents the resistance of the resistor 370, and I.sub.227i represents the detection current 227.sub.i. For example, N is equal to 1. As an example, N is a positive integer larger than 1. In certain examples, based on Equation 3,

[00004]$\begin{array}{cc}{V}_{231}=\left(I_{2271}+I_{2272}+.Math.+I_{227N}\right)R_{370}& \left(\mathrm{Equation}4\right)\end{array}$

where V.sub.231 represents the combined detection voltage 231 and R.sub.370 represents the resistance of the resistor 370. Additionally, I.sub.2271, I.sub.2272, . . . , and I.sub.227N represent the one or more detection currents 227.sub.1, 227.sub.2, . . . , and 227.sub.N respectively. For example, N is equal to 1. As an example, N is a positive integer larger than 1.

[0043] FIG. 4 is a simplified diagram showing certain components of the chopper amplifier 330.sub.i of the operational amplifier 220.sub.i of the current detection system as part of the charging system 200 as shown in FIG. 2 and FIG. 3 according to certain embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The chopper amplifier 330.sub.i includes a chopper and amplification unit 410.sub.i, a clock signal generator 420.sub.i, and a virtual ground voltage generator 430.sub.i. The chopper and amplification unit 410.sub.i includes chopper units 440.sub.i, 450.sub.i, and 460.sub.i, transistors 472.sub.i, 474.sub.i, 476.sub.i, 478.sub.i, 480.sub.i, 482.sub.i, 484.sub.i, 486.sub.i, 488.sub.i, and 490.sub.i, a resistor 412.sub.i, and a capacitor 414.sub.i. The chopper unit 440.sub.i includes transistors 442.sub.i, 444.sub.i, 446.sub.i, and 448.sub.i, the chopper unit 450.sub.i includes transistors 452.sub.i, 454.sub.i, 456.sub.i, and 458.sub.i, and the chopper unit 460.sub.i includes transistors 462.sub.i, 464.sub.i, 466.sub.i, and 468.sub.i. For example, i is an integer larger than or equal to 1 but smaller than or equal to N. As an example, N is a positive integer. Although the above has been shown using a selected group of components for the chopper amplifier 330.sub.i, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. Further details of these components are found throughout the present specification.

[0044] According to some embodiments, the virtual ground voltage generator 430.sub.i receives the voltage 205, the ground voltage 271, a control voltage 433.sub.i and a reference current 435.sub.i and generates a virtual ground voltage 431.sub.i based at least in part on the voltage 205 according to some embodiments. For example, if the voltage 205 is lower than a predetermined threshold (e.g., 5 volts), the virtual ground voltage generator 430.sub.i generates the virtual ground voltage 431.sub.i that is equal to the ground voltage 271. As an example, if the voltage 205 is higher than the predetermined threshold (e.g., 5 volts), the virtual ground voltage generator 430.sub.i generates the virtual ground voltage 431.sub.i that is equal to the voltage 205 minus a predetermined value (e.g., 5 volts).

[0045] According to certain embodiments, the clock signal generator 420.sub.i receives the virtual ground voltage 431.sub.i, the ground voltage 271, the voltage 205, and a clock signal 421.sub.i and generates clock signals 423.sub.i, 425.sub.i, 427.sub.i and 429.sub.i based at least in part on the virtual ground voltage 431.sub.i, the ground voltage 271, the voltage 205, and the clock signal 421.sub.i. For example, if the clock signal 423.sub.i is at a logic high level, the clock signal 425.sub.i is at a logic low level, and if the clock signal 423.sub.i is at the logic low level, the clock signal 425.sub.i is at the logic high level. As an example, if the clock signal 427.sub.i is at the logic high level, the clock signal 429.sub.i is at the logic low level, and if the clock signal 427.sub.i is at the logic low level, the clock signal 429.sub.i is at the logic high level.

[0046] In some examples, the supply voltage 391 minus the ground voltage 271 is equal to 5 volts, and the voltage 205 minus the virtual ground voltage 431.sub.i, is also equal to 5 volts. For example, if the clock signal 423.sub.i is equal to the supply voltage 391, the clock signal 423.sub.i is at the logic high level, and if the clock signal 423.sub.i is equal to the ground voltage 271, the clock signal 423.sub.i is at the logic low level. As an example, if the clock signal 425.sub.i is equal to the supply voltage 391, the clock signal 425.sub.i is at the logic high level, and if the clock signal 425.sub.i is equal to the ground voltage 271, the clock signal 425.sub.i is at the logic low level. For example, if the clock signal 427.sub.i is equal to the voltage 205, the clock signal 427.sub.i is at the logic high level, and if the clock signal 427.sub.i is equal to the virtual ground voltage 431.sub.i, the clock signal 427.sub.i is at the logic low level. As an example, if the clock signal 429.sub.i is equal to the voltage 205, the clock signal 429.sub.i is at the logic high level, and if the clock signal 429.sub.i is equal to the virtual ground voltage 431.sub.i, the clock signal 429.sub.i is at the logic low level. In certain examples, each clock signal of the clock signals 423.sub.i, 425.sub.i, 427.sub.i and 429.sub.i has a duty cycle that is equal to 50%.

[0047] As shown in FIG. 4, the clock signals 423.sub.i, 425.sub.i, 427.sub.i and 429.sub.i are used by the chopper units 440.sub.i, 450.sub.i, and 460.sub.i according to certain embodiments. For example, the clock signals 427.sub.i and 429.sub.i are received by the chopper units 440.sub.i and 450.sub.i. As an example, the clock signals 423.sub.i and 425.sub.i are received by the chopper unit 460.sub.i.

[0048] In some embodiments, the chopper unit 440.sub.i is a high-voltage chopper unit, and the transistors 442.sub.i, 444.sub.i, 446.sub.i, and 448.sub.i provide four branches for the high-voltage chopper unit 440.sub.i. In certain examples, the transistors 442.sub.i, 444.sub.i, 446.sub.i, and 448.sub.i each are a PMOS transistor. For example, a gate terminal of the transistor 442.sub.i and a gate terminal of the transistor 448.sub.i both receive the clock signal 429.sub.i. As an example, a gate terminal of the transistor 444.sub.i and a gate terminal of the transistor 446.sub.i both receive the clock signal 427.sub.i. In some examples, a source terminal of the transistor 442.sub.i and a source terminal of the transistor 446.sub.i are connected to the source terminal of the transistor 310.sub.i, and a source terminal of the transistor 444.sub.i and a source terminal of the transistor 448.sub.i are connected to the source terminal of the transistor 320.sub.i. For example, a drain terminal of the transistor 442.sub.i and a drain terminal of the transistor 444.sub.i are connected to a source terminal of the transistor 472.sub.i. As an example, a drain terminal of the transistor 446.sub.i and a drain terminal of the transistor 448.sub.i are connected to a source terminal of the transistor 474.sub.i.

[0049] In certain embodiments, the chopper unit 450.sub.i is a high-voltage chopper unit, and the transistors 452.sub.i, 454.sub.i, 456.sub.i, and 458.sub.i provide four branches for the high-voltage chopper unit 450.sub.i. In certain examples, the transistors 452.sub.i, 454.sub.i, 456.sub.i, and 458.sub.i each are a PMOS transistor. For example, a gate terminal of the transistor 452.sub.i and a gate terminal of the transistor 458.sub.i both receive the clock signal 429.sub.i. As an example, a gate terminal of the transistor 454.sub.i and a gate terminal of the transistor 456.sub.i both receive the clock signal 427.sub.i. In some examples, a source terminal of the transistor 452.sub.i and a source terminal of the transistor 456.sub.i are connected to a drain terminal of the transistor 472.sub.i, and a source terminal of the transistor 454.sub.i and a source terminal of the transistor 458.sub.i are connected to a drain terminal of the transistor 474.sub.i. For example, a drain terminal of the transistor 452.sub.i and a drain terminal of the transistor 454.sub.i are connected to a source terminal of the transistor 476.sub.i. As an example, a drain terminal of the transistor 456.sub.i and a drain terminal of the transistor 458.sub.i are connected to a source terminal of the transistor 478.sub.i.

[0050] In some embodiments, the chopper unit 460.sub.i is a low-voltage chopper unit, and the transistors 452.sub.i, 454.sub.i, 456.sub.i, and 458.sub.i provide four branches for the low-voltage chopper unit 460.sub.i. In certain examples, the transistors 462.sub.i, 464.sub.i, 466.sub.i, and 468.sub.i each are an NMOS transistor. For example, a gate terminal of the transistor 462.sub.i and a gate terminal of the transistor 468.sub.i both receive the clock signal 423.sub.i. As an example, a gate terminal of the transistor 464.sub.i and a gate terminal of the transistor 466.sub.i both receive the clock signal 425.sub.i. In some examples, a drain terminal of the transistor 462.sub.i and a drain terminal of the transistor 466.sub.i are connected to a source terminal of the transistor 484.sub.i, and a drain terminal of the transistor 464.sub.i and a drain terminal of the transistor 468.sub.i are connected to a source terminal of the transistor 486.sub.i. For example, a source terminal of the transistor 462.sub.i and a source terminal of the transistor 464.sub.i are connected to a drain terminal of the transistor 488.sub.i. As an example, a source terminal of the transistor 466.sub.i and a source terminal of the transistor 468.sub.i are connected to a drain terminal of the transistor 490.sub.i.

[0051] In certain examples, the transistors 472.sub.i and 474.sub.i each are a PMOS transistor (e.g., a low-voltage PMOS transistor). For example, a gate terminal of the transistor 472.sub.i and a gate terminal of the transistor 474.sub.i both receive a control signal 473.sub.i. In some examples, the transistors 476.sub.i and 478.sub.i each are a PMOS transistor (e.g., a high-voltage PMOS transistor). For example, a gate terminal of the transistor 476.sub.i and a gate terminal of the transistor 478.sub.i both receive a control signal 477.sub.i. In certain examples, the transistors 480.sub.i and 482.sub.i each are an NMOS transistor (e.g., a high-voltage NMOS transistor). For example, a gate terminal of the transistor 480.sub.i and a gate terminal of the transistor 482.sub.i both receive a control signal 481.sub.i. As an example, a drain terminal of the transistor 480.sub.i is connected to a drain terminal of the transistor 476.sub.i, and a drain terminal of the transistor 482.sub.i is connected to a drain terminal of the transistor 478.sub.i. In some examples, the transistors 484.sub.i and 486.sub.i each are an NMOS transistor (e.g., a low-voltage NMOS transistor). For example, a gate terminal of the transistor 484.sub.i and a gate terminal of the transistor 486.sub.i both receive a control signal 485.sub.i. As an example, a drain terminal of the transistor 484.sub.i is connected to a source terminal of the transistor 480.sub.i, and a drain terminal of the transistor 486.sub.i is connected to a source terminal of the transistor 482.sub.i. In certain examples, the transistors 488.sub.i and 490.sub.i each are an NMOS transistor (e.g., a low-voltage NMOS transistor). For example, a gate terminal of the transistor 488.sub.i and a gate terminal of the transistor 490.sub.i both receive a control signal 489.sub.i. As an example, a source terminal of the transistor 488.sub.i and a source terminal of the transistor 490.sub.i both are biased to the ground voltage 271.

[0052] According to certain embodiments, if the clock signal 421.sub.i is at the logic high level, the clock signal generator 420.sub.i generates the clock signals 423.sub.i and 427.sub.i at the logic high level and the clock signals 425.sub.i and 429.sub.i at the logic low level. For example, if the clock signal 421.sub.i is at the logic high level, the transistors 442.sub.i, 472.sub.i, 452.sub.i, 476.sub.i, 480.sub.i, 484.sub.i, 462.sub.i, and 488.sub.i are turned on, allowing a current to flow from the source terminal of the transistor 310.sub.i. As an example, if the clock signal 421.sub.i is at the logic high level, the transistors 448.sub.i, 474.sub.i, 458.sub.i, 478.sub.i, 482.sub.i, 486.sub.i, 468.sub.i, and 490.sub.i are also turned on, allowing a current to flow from the source terminal of the transistor 320.sub.i.

[0053] According to some embodiments, if the clock signal 421.sub.i is at the logic low level, the clock signal generator 420.sub.i generates the clock signals 423.sub.i and 427.sub.i at the logic low level and the clock signals 425.sub.i and 429.sub.i at the logic high level. For example, if the clock signal 421.sub.i is at the logic low level, the transistors 446.sub.i, 474.sub.i, 454.sub.i, 476.sub.i, 480.sub.i, 484.sub.i, 466.sub.i, and 490.sub.i are turned on, allowing a current to flow from the source terminal of the transistor 310.sub.i. As an example, if the clock signal 421.sub.i is at the logic low level, the transistors 444.sub.i, 472.sub.i, 456.sub.i, 478.sub.i, 482.sub.i, 486.sub.i, 464.sub.i, and 488.sub.i are also turned on, allowing a current to flow from the source terminal of the transistor 320.sub.i.

[0054] In certain examples, if the clock signal 421.sub.i changes from the logic high level to the logic low level, the transistors 472.sub.i and 488.sub.i change from receiving the current that flows from the source terminal of the transistor 310.sub.i to receiving the current that flows from the source terminal of the transistor 320.sub.i, and the transistors 474.sub.i and 490.sub.i change from receiving the current that flows from the source terminal of the transistor 320.sub.i to receiving the current that flows from the source terminal of the transistor 310.sub.i. In some examples, if the clock signal 421.sub.i changes from the logic low level to the logic high level, the transistors 472.sub.i and 488.sub.i change from receiving the current that flows from the source terminal of the transistor 320.sub.i to receiving the current that flows from the source terminal of the transistor 310.sub.i, and the transistors 474.sub.i and 490.sub.i change from receiving the current that flows from the source terminal of the transistor 310.sub.i to receiving the current that flows from the source terminal of the transistor 320.sub.i.

[0055] In certain embodiments, the transistors 472.sub.i, 474.sub.i, 488.sub.i and 490.sub.i are configured to perform amplification as parts of the chopper and amplification unit 410.sub.i. In some embodiments, the resistor 412.sub.i and the capacitor 414.sub.i are configured to perform low-pass filtering as parts of the chopper and amplification unit 410.sub.i.

[0056] As discussed above and further emphasized here, FIG. 4 is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. In some examples, the multiple chopper amplifiers do not share one clock signal generator and do not share one virtual ground voltage generator. For example, the chopper amplifier 330.sub.1 and the chopper amplifier 330.sub.2 do not share one clock signal generator and also do not share one virtual ground voltage generator. As an example, the clock signal generator 420.sub.1 and the clock signal generator 420.sub.2 are two separate clock signal generators, and the virtual ground voltage generator 430.sub.1 and the virtual ground voltage generator 430.sub.2 are two separate virtual ground voltage generators. In certain examples, the multiple chopper amplifiers share one clock signal generator and/or share one virtual ground voltage generator. For example, the chopper amplifier 330.sub.1 and the chopper amplifier 330.sub.2 share one clock signal generator and also share one virtual ground voltage generator. As an example, the clock signal generator 420.sub.1 and the clock signal generator 420.sub.2 are one clock signal generator, and/or the virtual ground voltage generator 430.sub.1 and the virtual ground voltage generator 430.sub.2 are one virtual ground voltage generator.

[0057] FIG. 5 is a simplified diagram showing certain components of the clock signal generator 420.sub.i of the chopper amplifier 330.sub.i of the operational amplifier 220.sub.i of the current detection system as part of the charging system 200 as shown in FIG. 2, FIG. 3 and FIG. 4 according to certain embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The clock signal generator 420.sub.i includes a voltage converter 510.sub.i and a voltage converter 520.sub.i. The voltage converter 510.sub.i includes transistors 560.sub.i, 522.sub.i, 524.sub.i, 526.sub.i, 528.sub.i, 530.sub.i, 532.sub.i, 534.sub.i, 536.sub.i, and 538.sub.i. The voltage converter 520.sub.i includes transistors 540.sub.i, 542.sub.i, 544.sub.i, 546.sub.i, 548.sub.i, and 550.sub.i. For example, i is an integer larger than or equal to 1 but smaller than or equal to N. As an example, N is a positive integer. Although the above has been shown using a selected group of components for the clock signal generator 420.sub.i, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. Further details of these components are found throughout the present specification.

[0058] In some embodiments, the voltage converter 510.sub.i is used in order to convert the clock signal 421.sub.i to the clock signal 427.sub.i. For example, the logic high level of the clock signal 421.sub.i corresponds to the supply voltage 391, and the logic low level of the clock signal 421.sub.i corresponds to the ground voltage 271. As an example, the logic high level of the clock signal 427.sub.i corresponds to the voltage 205, and the logic low level of the clock signal 427.sub.i corresponds to the virtual ground voltage 431.sub.i. In certain examples, the virtual ground voltage 431.sub.i is higher than or equal to the ground voltage 271. For example, the voltage converter 510.sub.i is a boost converter (e.g., a step-up converter). In some examples, the clock signal 427.sub.i is used to generate the clock signal 429.sub.i.

[0059] In certain embodiments, the voltage converter 520.sub.i is used in order to convert the clock signal 427.sub.i to the clock signal 423.sub.i. For example, the logic high level of the clock signal 427.sub.i corresponds to the voltage 205, and the logic low level of the clock signal 427.sub.i corresponds to the virtual ground voltage 431.sub.i. As an example, the logic high level of the clock signal 423.sub.i corresponds to the supply voltage 391, and the logic low level of the clock signal 423.sub.i corresponds to the ground voltage 271. In certain examples, the ground voltage 271 is lower than or equal to the virtual ground voltage 431.sub.i. For example, the voltage converter 520.sub.i is a buck converter (e.g., a step-down converter). In some examples, the clock signal 423.sub.i is used to generate the clock signal 425.sub.i.

[0060] According to some embodiments, the clock signal 423.sub.i changes from the logic low level to the logic high level and the clock signal 427.sub.i changes from the logic low level to the logic high at the same time, and the clock signal 423.sub.i changes from the logic high level to the logic low level and the clock signal 427.sub.i changes from the logic high level to the logic low at the same time.

[0061] FIG. 6 is a simplified diagram showing certain components of the virtual ground voltage generator 430.sub.i of the chopper amplifier 330.sub.i of the operational amplifier 220.sub.i of the current detection system as part of the charging system 200 as shown in FIG. 2, FIG. 3 and FIG. 4 according to some embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The virtual ground voltage generator 430.sub.i includes a resistor 610.sub.i, transistors 620.sub.i, 622.sub.i, and 624.sub.i, and a clamper 630.sub.i. For example, i is an integer larger than or equal to 1 but smaller than or equal to N. As an example, N is a positive integer. Although the above has been shown using a selected group of components for the virtual ground voltage generator 430.sub.i, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. Further details of these components are found throughout the present specification.

[0062] As shown in FIG. 6, the virtual ground voltage generator 430.sub.i receives the reference current 435.sub.i from a current source 640.sub.i according to certain embodiments. For example, the current source 640.sub.i is not a part of the virtual ground voltage generator 430.sub.i. In some examples, the clamper 630.sub.i includes transistors 632.sub.i, 634.sub.i, 636.sub.i and 638.sub.i and a current source 642.sub.i. For example, the transistors 620.sub.i, 632.sub.i, and 622.sub.i are parts of a buffer. As an example, a gate terminal of the transistor 620.sub.i and a gate terminal of the transistor 622.sub.i are at the same voltage. In certain examples, the clamper 630.sub.i is used to quickly clamp the virtual ground voltage 431.sub.i when the virtual ground voltage 431.sub.i decreases abruptly.

[0063] According to some embodiments, the virtual ground voltage generator 430.sub.i generates the virtual ground voltage 431.sub.i that is equal to the voltage 205 minus R.sub.1I.sub.ref+V.sub.SG620i, wherein R.sub.1 represents the resistance of the resistor 610.sub.i, I.sub.ref represents the reference current 435.sub.i, and V.sub.SG620i represents a voltage at a source terminal of the transistor 620.sub.i minus a voltage at a gate terminal of the transistor 620.sub.i. For example, the transistor 620.sub.i includes the source terminal 662.sub.i, the gate terminal 664.sub.i, and a drain terminal 666.sub.i. As an example, V.sub.SG620i represents the voltage at the source terminal 662.sub.i minus the voltage at the gate terminal 664.sub.i.

[0064] In some embodiments, a gate terminal of the transistor 624.sub.i receives the control voltage 433.sub.i. For example, if the voltage 205 is smaller than a predetermined threshold, the control voltage 433.sub.i is at a logic high level to turn on the transistor 624.sub.i. As an example, if the voltage 205 is larger than the predetermined threshold, the control voltage 433.sub.i is at a logic low level to turn off the transistor 624.sub.i.

[0065] In certain embodiments, the virtual ground voltage generator 430.sub.i generates the virtual ground voltage 431.sub.i as follows:

[00005]$\begin{array}{cc}\mathrm{if}{V}_{205}>V_{\mathrm{th}},& \left(\mathrm{Equation}5\right)\end{array}$$V_{431i}=V_{205}-\left(R_1{I}_{\mathrm{ref}}+V_{\mathrm{SG}620i}\right)$$\begin{array}{cc}\mathrm{if}{V}_{205}{V}_{\mathrm{th}},& \left(\mathrm{Equation}6\right)\end{array}$$V_{431i}=V_{271}$

where V.sub.205 represents the voltage 205, and V.sub.th represents a predetermined threshold. Additionally, V.sub.431i represents the virtual ground voltage 431.sub.i, and V.sub.271 represents the ground voltage 271 that is equal to zero volts. Also, R.sub.1 represents the resistance of the resistor 610.sub.i, and I.sub.ref represents the reference current 435.sub.i. Additionally, V.sub.SG620i represents the voltage at the source terminal 662.sub.i minus the voltage at the gate terminal 664.sub.i of the transistor 620.sub.i. For example, V.sub.th is equal to 5 volts, and R.sub.1I.sub.ref+V.sub.SG620i is also equal to 5 volts. As an example, according to Equations 5 and 6, the virtual ground voltage 431.sub.i is higher than or equal to the ground voltage 271, which is equal to zero volts.

[0066] Certain embodiments of the present invention significantly decrease the number of resistors in a current detection system, therefore significantly reducing circuit loss and improving efficiency of a charging system that includes the current detection system. Some embodiments of the present invention provide a current detection system that includes an operational amplifier with at least one or more high-voltage chopper units and also includes a digital-to-analog converter (DAC) so that the current detection system performs precise current detection for a wide range of input voltage and/or output voltage of the power management system. For example, the input voltage of the power management system ranges from 3 volts to 48 volts. As an example, the output voltage of the power management system ranges from 3 volts to 48 volts. Certain embodiments of the present invention provide a current detection system that includes an operational amplifier with at least a clock signal generator that generates two clock signals at different voltage levels but completely synchronized in order to avoid chopping residue.

[0067] According to some embodiments, a system for detecting one or more currents includes: one or more current sampling units coupled to one or more terminal transistors respectively and configured to sample one or more terminal currents that flow between a system terminal of a power management system and one or more port terminals through the one or more terminal transistors respectively; one or more operational amplifiers coupled to the one or more current sampling units respectively and configured to generate one or more detection currents respectively, the one or more detection currents representing one or more magnitudes of the one or more terminal currents respectively; and a signal combiner configured to receive the one or more detection currents, generate a combined detection voltage representing a sum of the one or more magnitudes of the one or more terminal currents, and output the combined detection voltage to the power management system to regulate the sum of the one or more magnitudes of the one or more terminal currents. For example, the system for detecting one or more currents is implemented according to at least FIG. 2.

[0068] As an example, the one or more current sampling units include a first sampling unit: the one or more terminal transistors include a first terminal transistor; the one or more terminal currents include a first terminal current; the one or more port terminals include a first port terminal; the one or more operational amplifiers include a first operational amplifier; the one or more detection currents include a first detection current; and the one or more magnitudes of the one or more terminal currents include a first magnitude of the first terminal current. For example, the first current sampling unit is coupled to the first terminal transistor and configured to sample the first terminal current that flows between the system terminal of the power management system and the first port terminal through the first terminal transistor; and the first operational amplifier is coupled to the first current sampling unit and configured to generate the first detection current, the first detection current representing the first magnitude of the first terminal current. As an example, the one or more current sampling units include a second sampling unit; the one or more terminal transistors include a second terminal transistor; the one or more terminal currents include a second terminal current: the one or more port terminals include a second port terminal; the one or more operational amplifiers include a second operational amplifier; the one or more detection currents include a second detection current; and the one or more magnitudes of the one or more terminal currents include a second magnitude of the second terminal current. For example, the second current sampling unit is coupled to the second terminal transistor and configured to sample the second terminal current that flows between the system terminal of the power management system and the second port terminal through the second terminal transistor; and the second operational amplifier is coupled to the second current sampling unit and configured to generate the second detection current, the second detection current representing the second magnitude of the second terminal current. As an example, the signal combiner is further configured to receive at least the first detection current and the second detection current, generate the combined detection voltage representing the sum of at least the first magnitude of the first terminal current and the second magnitude of the second terminal current, and output the combined detection voltage to the power management system to regulate the sum of at least the first magnitude of the first terminal current and the second magnitude of the second terminal current.

[0069] For example, the first terminal transistor includes a first transistor terminal, a second transistor terminal, and a third transistor terminal; wherein: the second transistor terminal is connected to the system terminal of the power management system; and the third transistor terminal is connected to the first port terminal. As an example, the first sampling unit includes a first sampling transistor and a second sampling transistor; wherein: the first sampling transistor includes a fourth transistor terminal, a fifth transistor terminal, and a sixth transistor terminal; and the second sampling transistor includes a seventh transistor terminal, an eighth transistor terminal, and a ninth transistor terminal. For example, the fourth transistor terminal and the seventh transistor terminal each are connected to the first transistor terminal: the fifth transistor terminal is connected to the third transistor terminal; and the eighth transistor terminal is connected to the second transistor terminal.

[0070] As an example, the first operational amplifier includes a first amplifier terminal, a second amplifier terminal, and a third amplifier terminal; wherein: the first amplifier terminal is connected to the sixth transistor terminal of the first sampling transistor; and the second amplifier terminal is connected to the ninth transistor terminal of the second sampling transistor. For example, the first operational amplifier is further configured to generate the first detection current at the third amplifier terminal. As an example, wherein the first operational amplifier further includes: a chopper amplifier; a current mirror coupled to the chopper amplifier; and a digital-to-analog converter coupled to the current mirror. For example, the current mirror of the first operational amplifier is configured to output the first detection current.

[0071] According to certain embodiments, a chopper amplifier includes: a ground voltage generator configured to receive a first ground voltage and a system voltage and generate a second ground voltage based at least in part on the first ground voltage and the system voltage; a clock signal generator configured to receive an input clock signal, the first ground voltage and the second ground voltage and generate a first clock signal and a second clock signal based at least in part on the input clock signal, the first ground voltage and the second ground voltage; and a chopper and amplification unit including a first chopper unit, a second chopper unit coupled to the first chopper unit through multiple transistors, and a third chopper unit coupled to the second chopper unit through multiple transistors; wherein: the second ground voltage is higher than or equal to the first ground voltage; wherein: if the first clock signal is equal to the first ground voltage, the first clock signal is at a logic low level; and if the second clock signal is equal to the second ground voltage, the second clock signal is at the logic low level; wherein: the first chopper unit is configured to receive the second clock signal: the second chopper unit is configured to receive the second clock signal; and the third chopper unit is configured to receive the first clock signal. For example, the chopper amplifier is implemented according to at least FIG. 4.

[0072] As an example, a clock signal generator includes: a first voltage converter configured to, with one or more other components, convert the input clock signal to the second clock signal; and a second voltage converter configured to, with one or more other components, convert the second clock signal to the first clock signal. For example, the ground voltage generator is further configured to: if the system voltage is larger than a predetermined threshold, generate the second ground voltage to be equal to the system voltage minus a predetermined magnitude; and if the system voltage is smaller than the predetermined threshold, generate the second ground voltage to be equal to the first ground voltage.

[0073] According to some embodiments, a method for detecting one or more currents includes: sampling one or more terminal currents that flow between a system terminal of a power management system and one or more port terminals through one or more terminal transistors respectively; generating one or more detection currents representing one or more magnitudes of the one or more terminal currents respectively; receiving the one or more detection currents; generating a combined detection voltage representing a sum of the one or more magnitudes of the one or more terminal currents; and outputting the combined detection voltage to the power management system to regulate the sum of the one or more magnitudes of the one or more terminal currents. For example, the method for detecting one or more currents is implemented according to at least FIG. 2.

[0074] As an example, the one or more terminal transistors include a first terminal transistor; the one or more terminal currents include a first terminal current; the one or more port terminals include a first port terminal; the one or more detection currents include a first detection current; and the one or more magnitudes of the one or more terminal currents include a first magnitude of the first terminal current. For example, the sampling one or more terminal currents that flow between a system terminal of a power management system and one or more port terminals through one or more terminal transistors respectively includes sampling the first terminal current that flows between the system terminal of the power management system and the first port terminal through the first terminal transistor; and the generating one or more detection currents representing one or more magnitudes of the one or more terminal currents respectively includes generating the first detection current representing the first magnitude of the first terminal current. As an example, the receiving the one or more detection currents includes receiving at least the first detection current; and the generating a combined detection voltage representing a sum of the one or more magnitudes of the one or more terminal currents includes generating the combined detection voltage representing the sum of at least the first magnitude of the first terminal current. For example, the sum of the one or more magnitudes of the one or more terminal currents is equal to the first magnitude of the first terminal current.

[0075] In certain examples, some or all components of various embodiments of the present invention each are, individually and/or in combination with at least another component, implemented using one or more software components, one or more hardware components, and/or one or more combinations of software and hardware components. In some examples, some or all components of various embodiments of the present invention each are, individually and/or in combination with at least another component, implemented in one or more circuits, such as one or more analog circuits and/or one or more digital circuits. For example, the one or more current sampling units 210.sub.1, 210.sub.2, . . . , and 210.sub.N each are implemented in one or more circuits. As an example, the chopper and amplification unit 410.sub.i is implemented in one or more circuits. For example, the chopper units 440.sub.i, 450; and 460.sub.i each are implemented in one or more circuits. As an example, various embodiments and/or examples of the present invention can be combined.

[0076] Although specific embodiments of the present invention have been described, it will be understood by those of skill in the art that there are other embodiments that are equivalent to the described embodiments. Accordingly, it is to be understood that the invention is not to be limited by the specific illustrated embodiments.