GaN POWER DEVICE

Abstract

The present disclosure discloses a GaN power device having a structure improved to have an improved current density. The GaN power device includes a GaN layer, a first electrode and a second electrode formed on the GaN layer in a way to have a separation area therebetween, an AlGaN layer formed on the GaN layer of the separation area, a gate electrode formed over the AlGaN layer in a way to be separated from the first electrode and the second electrode, and a 2DEG layer formed at an interface of the AlGaN layer and the GaN layer in an area between the gate electrode and the second electrode.

Claims

1. A gallium nitride (GaN) power device comprising: a GaN layer; a first electrode and a second electrode formed on the GaN layer in a way to have a separation area therebetween; an AlGaN layer formed on the GaN layer of the separation area; a gate electrode formed over the AlGaN layer in a way to be separated from the first electrode and the second electrode; and a 2DEG layer formed at an interface of the AlGaN layer and the GaN layer in an area between the gate electrode and the second electrode, wherein at least one concave surface is formed in the GaN layer under the 2DEG layer, and the interface and the 2DEG layer are formed along the concave surface.

2. The GaN power device of claim 1, wherein the concave surface is composed of an inverted triangular trench by etching.

3. The GaN power device of claim 1, wherein the concave surface is composed of a rectangular trench by etching.

4. The GaN power device of claim 1, wherein a plane pattern of the concave surface has a bar pattern parallel to the gate electrode and the second electrode.

5. The GaN power device of claim 1, wherein a plane pattern of the concave surface has a bar pattern disposed in a direction crossing the gate electrode and the second electrode.

6. The GaN power device of claim 1, wherein: the concave surface is formed in the GaN layer under the 2DEG layer in plural number, and the plurality of concave surfaces is disposed to be separated from one another in a plane between the gate electrode and the second electrode.

7. The GaN power device of claim 6, wherein the plurality of concave surfaces is disposed to be separated from one another in a way to form a matrix structure on a plane between the gate electrode and the second electrode.

8. A GaN power device comprising: a GaN layer; a first electrode and a second electrode formed on the GaN layer in a way to have a separation area therebetween; an AlGaN layer formed on the GaN layer of the separation area; a gate electrode formed over the AlGaN layer in a way to be separated from the first electrode and the second electrode; and a 2DEG layer formed at an interface of the AlGaN layer and the GaN layer in an area between the gate electrode and the second electrode, wherein at least one convex surface is formed in the GaN layer under the 2DEG layer, and the interface and the 2DEG layer are formed along the convex surface.

9. The GaN power device of claim 8, wherein the convex surface is composed of a triangular stacked body.

10. The GaN power device of claim 8, wherein the convex surface is composed of a rectangular stacked body.

11. The GaN power device of claim 8, wherein a plane pattern of the convex surface has a bar pattern parallel to the gate electrode and the second electrode.

12. The GaN power device of claim 8, wherein a plane pattern of the convex surface has a bar pattern disposed in a direction crossing the gate electrode and the second electrode.

13. The GaN power device of claim 8, wherein: the convex surface is formed in the GaN layer under the 2DEG layer in plural number, and the plurality of convex surfaces is disposed to be separated from one another in a plane between the gate electrode and the second electrode.

14. The GaN power device of claim 13, wherein the plurality of convex surfaces is disposed to be separated from one another in a way to form a matrix structure on a plane between the gate electrode and the second electrode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG. 1 is a cross-sectional view of a GaN power device according to a preferred embodiment of the present disclosure.

[0017] FIG. 2 is a cross-sectional view of a GaN power device according to another embodiment of the present disclosure.

[0018] FIG. 3 is a cross-sectional view of a GaN power device according to still another embodiment of the present disclosure.

[0019] FIG. 4 is a cross-sectional view of a GaN power device according to yet another embodiment of the present disclosure.

[0020] FIG. 5 is a plan view illustrating an example of a layout according to the embodiments of the present disclosure.

[0021] FIG. 6 is a plan view illustrating another example of the layout according to the embodiments of the present disclosure.

[0022] FIG. 7 is a plan view illustrating still another example of the layout according to the embodiments of the present disclosure.

DETAILED DESCRIPTION

[0023] A GaN power device of the present disclosure is embodied using characteristics of GaN.

[0024] GaN may have a higher bandgap than silicon, and may have high breakdown field strength and a high saturation electron speed that much.

[0025] The GaN power device may have a 2DEG layer having a high concentration. The GaN power device using the 2DEG layer maintains normally turn-on.

[0026] A GaN power device according to a preferred embodiment of the present disclosure may be described with reference to FIG. 1.

[0027] The GaN power device of FIG. 1 is illustrated as having a transistor structure, and includes a gate, a drain and a source as terminals of the GaN power device. Due to the construction, the GaN power device of FIG. 1 may maintain normally turn-on by a 2DEG layer. It may be understood that the turn-on state of the GaN power device is controlled by a voltage of the gate.

[0028] A GaN power device 100 may be formed on a silicon substrate 10.

[0029] A buffer layer 20 may be constructed on the silicon substrate 10. The buffer layer 20 may include an AlN nucleation layer 22 and an AlGaN/GaN buffer layer 24 sequentially formed over the silicon substrate 10. The AlN means aluminum nitride. Furthermore, the AlGaN/GaN buffer layer 24 means a buffer layer formed using an AlGaN material or a GaN material. Furthermore, the AlGaN means aluminum gallium nitride.

[0030] The buffer layer 20 is constructed in order to grow a GaN layer 30 over the silicon substrate 10.

[0031] If a nitride-series thin film, such as the GaN layer 30, is grown over the silicon substrate 10, a dislocation density may be increased due to a lattice constant mismatch between the silicon substrate 10 and a nitride thin film, and a crack may occur due to tensile stress occurring due to a difference in a coefficient of thermal expansion. The nitride thin film requires the buffer layer 20 in order to have a high crystallizability and be grown over the silicon substrate 10 without a crack.

[0032] The buffer layer 20 including the AlN nucleation layer 22 and the AlGaN/GaN buffer layer 24 is merely an example, and may be variously implemented depending on a manufacturer’s intention.

[0033] Furthermore, the GaN layer 30 may be formed on the buffer layer 20.

[0034] The GaN layer 30 may be understood as a layer on which intended doping with impurities is not performed. Accordingly, the GaN layer 30 may be understood as an N type semiconductor. Furthermore, the GaN layer 30 may be understood as an electron travel layer.

[0035] A first electrode, a second electrode and an AlGaN layer 40 may be formed on the GaN layer 30. In this case, the first electrode may be illustrated as a source electrode S, and the second electrode may be illustrated as a drain electrode D.

[0036] The source electrode S and the drain electrode D may be formed to have a separation area SD therebetween. Furthermore, the AlGaN layer 40 may be formed on the GaN layer 30 of the separation area SD.

[0037] The AlGaN layer 40 may be understood as an electron supply layer.

[0038] A gate electrode G may be formed over the AlGaN layer 40. The gate electrode G is preferably constructed to be separated from the source electrode S and the drain electrode D.

[0039] The gate electrode G, the source electrode S and the drain electrode D may be formed by the deposition of gold (Au), aluminum (Al) or platinum (Pt), for example.

[0040] A cap layer 60 may be formed between the gate electrode G and the AlGaN layer 40. The cap layer 60 may be constructed as a P type semiconductor doped with P type impurities (e.g., magnesium (Mg)) at a preset concentration. That is, the cap layer 60 may be formed using P type GaN.

[0041] Due to the construction, a channel between the gate electrode G and the drain electrode D is formed between the cap layer 60 and the drain electrode D. Accordingly, an area between the gate electrode G and the drain electrode D may be understood as an area indicated by GD in FIG. 1.

[0042] A 2DEG layer 50 is formed at the interface of the GaN layer 30 and the AlGaN layer 40. The 2DEG layer 50 may be formed in an area that belongs to the interface of the GaN layer 30 and the AlGaN layer 40 and that is disposed area between the source electrode S and the gate electrode G and in the area GD between the gate electrode G and the drain electrode D. The 2DEG layer 50 is not formed in an area under the gate electrode G.

[0043] The 2DEG layer 50 may be understood as a layer in which a 2DEG has been generated. The 2DEG layer 50 has a two-dimensional shape at the interface of the GaN layer 30 and the AlGaN layer 40, and thus can guarantee a free movement of electrons.

[0044] In the aforementioned construction, the buffer layer 20, the GaN layer 30, the AlGaN layer 40 and the cap layer 60 may be formed by epitaxy, for example. In order to form each layer, a different source and mixed gas may be used for each layer.

[0045] Furthermore, an insulating film may be formed in the area GD between the gate electrode G and the drain electrode D and the separation area SD between the source electrode S and the drain electrode D. In order to form the insulating film, a nitride film may be deposited. The nitride film may be deposited by atomic layer deposition (ALD) or chemical vapor deposition (CVD), for example.

[0046] An embodiment of the present disclosure has a construction for implementing a high current density.

[0047] To this end, one or more concave surfaces may be formed in the GaN layer 30 under the 2DEG layer 50 corresponding to the area GD between the gate electrode G and the drain electrode D. Furthermore, the interface of the GaN layer 30 and the AlGaN layer 40 and the 2DEG layer 50 may be formed along the concave surfaces.

[0048] The concave surface may be constructed by forming a trench on a corresponding surface of the GaN layer 30. Furthermore, the trench may be formed by a method, such as dry etch.

[0049] In this case, the trench may be formed to have an inverted triangular cross section as in FIG. 1. The concave surface of the GaN layer 30 may be formed to have an inverted triangular cross section by the shape of the trench.

[0050] The embodiment of FIG. 1 illustrates that a plurality of concave surfaces has been formed in the GaN layer 30 under the 2DEG layer 50 corresponding to the area GD between the gate electrode G and the drain electrode D. The concave surfaces may be formed in divided areas, respectively, and may be disposed to be separated from each other.

[0051] According to the present disclosure, if the concave surfaces are formed in the GaN layer 30, in general, a wider area for forming the 2DEG layer 50 can be provided compared to a case where the GaN layer 30 is flat.

[0052] In an embodiment of the present disclosure, as described above, the interface of the GaN layer 30 and the AlGaN layer 40 may be expanded by the concave surfaces. As a result, the 2DEG layer 50 in the area GD between the gate electrode G and the drain electrode D may have a wider area.

[0053] Accordingly, a current density between the gate electrode G and the drain electrode D may be increased in proportion to an increase in the area of the 2DEG layer 50 in the area GD between the gate electrode G and the drain electrode D.

[0054] Accordingly, the embodiment of the present disclosure illustrated in FIG. 1 can increase the area, in which the 2DEG layer is formed, by forming the concave surfaces at the interface of the GaN layer and the AlGaN layer.

[0055] Accordingly, the GaN power device 100 can be designed to have a high current density even in a limited chip size, and can be designed to have a high current density without increasing a chip size.

[0056] Concave surfaces of the present disclosure may be implemented as in FIG. 2. In FIG. 2, the same element as that of FIG. 1 is indicated by the same reference numeral, and a redundant description thereof is omitted.

[0057] As in FIG. 2, a plurality of trenches each having a rectangular cross section may be formed in a GaN layer 30 under a 2DEG layer 50 corresponding to an area GD between a gate electrode G and a drain electrode D.

[0058] Concave surfaces formed by the respective trenches in FIG. 2 having the rectangular cross sections may be formed in divided areas, respectively, and may be disposed to be separated from each other.

[0059] Even in the embodiment of FIG. 2, the interface of the GaN layer 30 and an AlGaN layer 40 and the 2DEG layer 50 may be formed along the concave surfaces having the rectangular cross sections, that is, the trenches.

[0060] In the present disclosure, the concave surfaces may be formed to have various cross section structures depending on a manufacturer’s intention. A cross section structure of the concave surface implemented by the present disclosure is not limited by the embodiments of FIGS. 1 and 2.

[0061] Furthermore, as another embodiment of the present disclosure, a cross section structure of the concave surface may be constructed as in FIG. 3.

[0062] The embodiment of FIG. 3 may be implemented so that one or more convex surfaces are formed in a GaN layer 30 under a 2DEG layer 50 corresponding to an area GD between a gate electrode G and a drain electrode D. Furthermore, the interface of the GaN layer 30 and an AlGaN layer 40 and the 2DEG layer 50 may be formed along the convex surfaces. In FIG. 3, the same element as that of FIG. 1 is indicated by the same reference numeral, and a redundant description thereof is omitted.

[0063] The convex surfaces may be constructed by forming stacked bodies on a corresponding surface of the GaN layer 30. Furthermore, the stacked bodies may be formed by selectively additionally stacking GaN at a corresponding location after the GaN layer 30 is formed.

[0064] In this case, the stacked bodies may be formed to have triangular cross sections, respectively, as in FIG. 3. The convex surfaces of the GaN layer 30 may be formed to have the triangular cross sections by shapes of the stacked bodies.

[0065] The embodiment of FIG. 3 illustrates that a plurality of convex surfaces has been formed in the GaN layer 30 under the 2DEG layer 50 corresponding to the area GD between the gate electrode G and the drain electrode D. The convex surfaces may be formed in divided areas, respectively, and may be disposed to be separated from each other.

[0066] According to the present disclosure, if the convex surfaces are formed in the GaN layer 30, in general, a wider area for forming the 2DEG layer 50 can be provided compared to a case where the GaN layer 30 is flat.

[0067] In an embodiment of the present disclosure, the interface of the GaN layer 30 and the AlGaN layer 40 may be expanded by the convex surfaces as described above. As a result, the 2DEG layer 50 in the area GD between the gate electrode G and the drain electrode D may have a wider area.

[0068] Accordingly, a current density between the gate electrode G and the drain electrode D may be increased in proportion to an increase in the area of the 2DEG layer 50 in the area GD between the gate electrode G and the drain electrode D.

[0069] Accordingly, the embodiment of the present disclosure of FIG. 3 can increase the area, in which the 2DEG layer is formed, by forming the convex surfaces in the interface of the GaN layer and the AlGaN layer.

[0070] Accordingly, the GaN power device 100 can be designed to have a high current density even in a limited chip size, and can be designed to have a high current density without increasing a chip size.

[0071] Convex surfaces of the present disclosure may be implemented as in FIG. 4. In FIG. 4, the same element as that of FIG. 3 is indicated by the same reference numeral, and a redundant description thereof is omitted.

[0072] As in FIG. 4, a plurality of stacked bodies having rectangular cross sections, respectively, may be formed in a GaN layer 30 under a 2DEG layer 50 corresponding to an area GD between a gate electrode G and a drain electrode D.

[0073] Convex surfaces in of FIG. 4 formed by the stacked bodies having the rectangular cross sections may also be formed in divided areas, respectively, and may be disposed to be separated from each other.

[0074] Even in the embodiment of FIG. 4, the interface of the GaN layer 30 and an AlGaN layer 40 and the 2DEG layer 50 may be formed along the convex surfaces having the rectangular cross sections, that is, the stacked bodies.

[0075] In the present disclosure, the convex surfaces may be formed to have various cross section structures depending on a manufacturer’s intention. A cross section structure of the convex surface implemented by the present disclosure is not limited by the embodiments of FIGS. 3 and 4.

[0076] Furthermore, the concave surfaces implemented as in FIGS. 1 and 2 of the present disclosure or the convex surfaces implemented as in FIGS. 3 and 4 of the present disclosure may be embodied to have various plane patterns.

[0077] FIG. 5 illustrates plane patterns of the GaN power device 100 of the present disclosure.

[0078] In FIG. 5, the source electrode S, the gate electrode G and the drain electrode D are illustrated as being separated from one another in parallel. Furthermore, a plurality of plane patterns P is disposed in the area GD between the gate electrode G and the drain electrode D.

[0079] The plane patterns P may be understood to correspond to the concave surfaces of FIGS. 1 and 2 or the convex surfaces of FIGS. 3 and 4, respectively.

[0080] In FIG. 5, the plane patterns P are illustrated as having bar patterns, respectively. Furthermore, the plane patterns P are disposed in parallel at given intervals. Furthermore, the plane patterns P are disposed to be parallel to the gate electrode G and the drain electrode G.

[0081] Plane patterns of the GaN power device 100 of the present disclosure may be illustrated as in FIG. 6. In FIG. 6, the source electrode S, the gate electrode G and the drain electrode D are illustrated as being separated from one another in parallel in the same manner as FIG. 5. Furthermore, the plurality of plane patterns P is disposed in the area GD between the gate electrode G and the drain electrode D.

[0082] The plane patterns P of FIG. 6 are illustrated as having bar patterns, respectively. Furthermore, the plane patterns P are disposed in parallel at given intervals.

[0083] However, unlike FIG. 5, the plane patterns P of FIG. 6 are disposed in a direction crossing the gate electrode G and the drain electrode G.

[0084] Furthermore, the plane patterns of the GaN power device 100 of the present disclosure may be illustrated as in FIG. 7. In FIG. 7, the source electrode S, the gate electrode G and the drain electrode D are illustrated as being separated from one another in parallel in the same manner as FIG. 5. Furthermore, the plurality of plane patterns P is disposed in the area GD between the gate electrode G and the drain electrode D.

[0085] The plane patterns P of FIG. 7 are illustrated as having rectangular patterns, respectively. Furthermore, the plane patterns P are disposed to be separated from one another while forming a matrix structure.

[0086] In the present disclosure, the plane patterns of the concave surfaces or the convex surfaces may be variously formed and disposed depending on a manufacturer’s intention. Shapes and arrangements of the plane patterns implemented by the present disclosure are not limited by the embodiments of FIGS. 5 to 7.

[0087] As in the aforementioned embodiments, the GaN power device of the present disclosure can increase the area, in which the 2DEG layer is formed, by changing the interface structure of the GaN layer and the AlGaN layer in a way to have the concave surfaces or the convex surfaces.

[0088] Accordingly, the GaN power device of the present disclosure can be designed to have a high current density even in a limited chip size.

[0089] Furthermore, the GaN power device of the present disclosure can be designed to have a high current density without increasing a chip size.