Vehicle control device

Abstract

In the present invention, when an abnormality occurs in a task, regardless of whether a critical section is being executed, timeout detection is realized by determining whether the critical section (CS) is necessary for the design in a preset task execution time and a certain period of time to distinguish between necessary interrupt disable and abnormal interrupt disable. A vehicle control device includes task execution means for causing a system to execute a task, and interrupt processing means for performing an interrupt process at the time of execution of the task. A maskable interrupt and a non-maskable interrupt that is commanded to execute after the maskable interrupt are included, the maskable interrupt is commanded to execute during an interrupt disable time, and then the non-maskable interrupt is executed.

Claims

1. A vehicle control device, comprising: an interrupt processor configured to perform an interrupt process at a time of execution of a task, wherein the interrupt processor includes a first non-maskable interrupt, a maskable interrupt that is commanded to execute after a predetermined time from the first non-maskable interrupt, and a second non-maskable interrupt that is commanded to execute after the maskable interrupt that is after a predetermined time from the first non-maskable interrupt, and includes a case where the first non-maskable interrupt is commanded to execute during an interrupt disable time, and the maskable interrupt is executed after the interrupt disable time is released, and wherein the interrupt processor is configured to command the first non-maskable interrupt and the maskable interrupt to execute during the interrupt disable time, and to cause the second non-maskable interrupt to be executed.

2. The vehicle control device according to claim 1, wherein the non-maskable interrupt is executed when the maskable interrupt cannot be executed.

3. The vehicle control device according to claim 1, wherein the interrupt processor is further configured to perform the interrupt process when a failure of a system, for which the task is executed, is monitored.

4. A vehicle control device, comprising: an interrupt processor configured to perform an interrupt process at a time of execution of a task, wherein the interrupt processor includes a first non-maskable interrupt, a maskable interrupt that is commanded to execute after a predetermined time from the first non-maskable interrupt, and a second non-maskable interrupt that is commanded to execute after the maskable interrupt that is after a predetermined time from the first non-maskable interrupt, and includes a case where the first non-maskable interrupt is commanded to execute during an interrupt disable time, and the maskable interrupt is executed after the interrupt disable time is released, and the interrupt processor is configured to command the first non-maskable interrupt and the maskable interrupt to execute during the interrupt disable time, and to cause the second non-maskable interrupt to be executed.

5. The vehicle control device according to claim 4, wherein the second non-maskable interrupt is executed when maskable interrupt cannot be executed.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a configuration diagram of an engine control unit ECU 1 according to a first embodiment.

(2) FIG. 2 is a diagram illustrating an example of a data management table 401 of the engine control unit ECU1.

(3) FIG. 3 is a diagram illustrating an example of a data recording table 402 of the engine control unit ECU1.

(4) FIG. 4 is a diagram illustrating an example of a timer register table 500 of the engine control unit ECU1.

(5) FIG. 5 is a diagram illustrating an example of an operation flow of a hardware timer 5 of the engine control unit ECU1.

(6) FIG. 6 is a diagram illustrating an example of an operation flow of a software control unit 201 of the engine control unit ECU1.

(7) FIG. 7 is a diagram illustrating an example of an operation flow of a task execution unit 202 of the engine control unit ECU1.

(8) FIG. 8 is a diagram illustrating an example of an operation flow of a non-maskable interrupt execution unit 203 of the engine control unit ECU1.

(9) FIG. 9 is a diagram illustrating an example of an operation flow of a software interrupt execution unit 204 of the engine control unit ECU1.

DESCRIPTION OF EMBODIMENTS

First Embodiment

(10) FIG. 1 is a configuration diagram of an engine control unit ECU 1 according to the present invention. The engine control unit ECU1 includes a program area 2, a calculation unit 3, a storage area 4, a hardware timer 5, an interrupt controller 6, and a shared bus 7.

(11) The calculation unit 3 is a processor core (Central Processing Unit) that executes a program stored in the program area 2. The program area 2 stores a software control unit 201, a task execution unit 202, a non-maskable interrupt execution unit 203, and a software interrupt execution unit 204.

(12) The storage area 4 stores a data management table 401 described later with reference to FIG. 2 and a data recording table 402 described with reference to FIG. 3.

(13) The hardware timer 5 counts a clock, and an elapsed time can be known from the counter value of the clock. The timer has a comparison circuit. A numerical value stored in a timer register described later with reference to FIG. 4, and a count value of the timer counter are always compared by a comparison circuit. When the two values match, a non-maskable signal is generated in the interrupt controller 6. As a result, an interrupt is generated when the set time has elapsed, and processing that requires time management can be performed. Further, the hardware timer 5 stores a timer register table 500 of FIG. 4 described later.

(14) When the interrupt controller 6 receives the above-described non-maskable signal from the hardware timer 5, the interrupt controller 6 interrupts the process being executed by the calculation unit and generates a non-maskable interrupt (hereinafter, non-maskable interrupt).

(15) The configuration of the engine control unit ECU 1 in the first embodiment is not limited to this. For example, a non-volatile memory (backup RAM) for storing data, a shared memory for accessing each calculation unit, a different sensor, or the like may be provided.

(16) A table stored in the storage area 4 and the hardware timer 5 of the engine control unit ECU1 will be described below. FIG. 2 is a diagram illustrating an example of the calculation unit data management table 401 stored in the storage area 4. The data management table 401 includes a name field 40101 and a setting value field 40102. The name field 40101 is a name of an object managed by the data management table 401. In the present embodiment, the maximum value of the HW timer counter, the first compare match time, and the second compare match time are included, but the type and number of objects to be managed and the management method are not limited thereto. The setting value field 40102 represents a value in which a setting value to be managed by the data management table 401 stored.

(17) FIG. 3 is a diagram illustrating an example of the data recording table 402 stored in the storage area 4. The data recording table 402 includes a name field 40201 and a value field 40202. The name field 40201 is a name of an object managed by the data recording table 402. In the present embodiment, an HW timer counter value and the number of the non-maskable interrupt execution are included, but the types of objects to be managed, the number of objects, and the management method are not limited to this. A value field 40202 represents a value in which a value to be managed by the data recording table 402 is stored.

(18) FIG. 4 is a diagram illustrating an example of the timer register table 500 stored in the hardware timer 5. The timer register table 500 includes a name field 501 and a setting value field 502. The name field 501 is a name of a target managed by the timer register table 500. In the present embodiment, a compare match flag and a compare match counter are included, but the types of objects to be managed, the number of objects, and the management method are not limited to this. The setting value field 502 represents a value in which a setting value to be managed by the timer register table 500 is stored.

(19) The above-described table is stored in the storage area 4 and the hardware timer 5 of the engine control unit ECU 1 of the first embodiment, but the storage location of the table is not limited to this.

(20) The operation of the hardware timer 5 of the engine control unit ECU 1 and the operation flow of the program stored in the program area 2 and executed by the calculation unit 3 will be described.

(21) FIG. 5 is an operation flow of the hardware timer 5. Hereinafter, each step of FIG. 5 will be described.

(22) (FIG. 5: Step 600)

(23) The hardware timer 6 5 increments and updates a hardware timer counter value.

(24) (FIG. 5: Step 601)

(25) The hardware timer 5 proceeds to step 602 when the hardware timer counter value reaches the maximum value, and proceeds to step 603 otherwise.

(26) (FIG. 5: Step 602)

(27) The hardware timer 5 resets a counter and proceeds to step 40301.

(28) (FIG. 5: Step 603)

(29) When the compare match flag managed by the timer register table 500 is 1, the hardware timer 5 proceeds to step 604 if values match, and proceeds to step 606 otherwise.

(30) (FIG. 5: Step 604)

(31) The hardware timer 5 compares the hardware timer with the compare match counter managed by the timer register table 500, and the hardware timer 5 proceeds to step 604 if they match, and proceeds to step 606 otherwise.

(32) (FIG. 5: Step 605)

(33) The hardware timer 5 calls a non-maskable interrupt described later, and proceeds to step 606.

(34) (FIG. 5: Step 606)

(35) The hardware timer 5 determines whether or not end conditions are satisfied. If the end conditions are satisfied, the hardware timer 5 ends the process, or proceeds to step 601 if not satisfied.

(36) FIG. 6 is an operation flow of the software control unit 201. Hereinafter, each step of FIG. 6 will be described.

(37) (FIG. 6: Step 20100)

(38) The software control unit 201 initializes the storage area 4 and an HW timer 5, and proceeds to step 20101.

(39) (FIG. 6: Step 20101)

(40) The software control unit 201 calls a task execution unit described later and proceeds to step 20102.

(41) (FIG. 6: Step 20102)

(42) The software control unit 201 determines whether or not end conditions are satisfied, and ends the process if satisfied, or proceeds to step 20101 if not satisfied.

(43) FIG. 7 is an operation flow of the task execution unit 202. Hereinafter, each step of FIG. 7 will be described.

(44) (FIG. 7. Step 20200)

(45) The task execution unit 202 sets a compare match setting value in the timer register table 500 and proceeds to Step 20201. Here, setting of the compare match setting value refers to the process of setting the compare match flag in the timer register table 500 to 1 to set the mode to generate a compare match, and the process of acquiring the current HW timer counter from an input capture register to set the period (compare match counter) until a compare match generates.

(46) (FIG. 7: Step 20201)

(47) The task execution unit 202 executes the CS start process and proceeds to Step 20202. Here, the CS start process is an interrupt prohibition process for preventing the process in a critical section from being interrupted by other processes.

(48) (FIG. 7: Step 20202)

(49) The task execution unit 202 executes the CS process and proceeds to Step 20203.

(50) (FIG. 7: Step 20203)

(51) The task execution unit 202 executes a CS end process and proceeds to Step 20204. Here, the CS end process is a process for releasing an interrupt disable process and the like for preventing a critical section from being interrupted by other processes.

(52) (FIG. 7: Step 20204)

(53) The task execution unit 202 executes a compare match end process and ends the process. Here, the compare match end process is a process for setting the compare match flag of the timer register table 500 to 0 and turning off the compare match function.

(54) (FIG. 8: Step 20300)

(55) The NMI execution unit 203 determines the number of times of non-maskable interrupt execution in the data recording table 402. If it is the first time. The NMI execution unit 203 proceeds to step 20301, and proceeds to step 20304 otherwise.

(56) (FIG. 8: Step 20301)

(57) The NMI execution unit 203 executes a compare match setting process and proceeds to step 20302. Here, the compare match setting process refers to a process of acquiring a second compare match time from the data management table 401 and setting it in the compare match counter of the timer register table 500.

(58) (FIG. 8: Step 20302)

(59) The NMI execution unit 203 executes an SW interrupt call process and proceeds to Step 20303. Here, the SW interrupt process is an interrupt generation process for calling a software interrupt execution unit of FIG. 9 described later.

(60) (FIG. 8: Step 20303)

(61) The NMI execution unit 203 executes an NMI execution counter update process and ends the process. Here, the NMI execution counter update process refers to a process of incrementing the number of times of non-maskable interrupt execution in the data recording table 402.

(62) (FIG. 8: Step 20304)

(63) The NMI execution unit 203 executes a reset process and ends the process.

(64) (FIG. 9: Step 20300)

(65) The software interrupt execution unit 204 executes a saving process and proceeds to step 20401. Here, the saving process refers to a process of storing a register value, a program counter value, and an HW timer counter value of the currently executing process in the storage area 4, but is not limited thereto.

(66) (FIG. 9: Step 20301)

(67) The software interrupt execution unit 204 executes task stop process and proceeds to step 20401. The task stop process is a process for stopping a task in which an abnormality is detected by a compare match.

(68) (FIG. 9: Step 20302)

(69) The software interrupt execution unit 204 executes a compare match end process and ends the process. The compare match end process is a process of setting the compare match flag of the timer register table 500 to 0 and turning off the compare match function.

(70) As described above, according to the first embodiment, when an abnormality occurs in a task, regardless of whether a critical section is being executed, timeout detection is realized by determining whether the critical section (CS) is necessary for the design in a preset task execution time and a certain period of time to distinguish between necessary interrupt disable and abnormal interrupt disable.

(71) The present embodiment can express the following configuration.

(72) A vehicle control device includes task execution means for causing a system to execute a task, and interrupt processing means for performing an interrupt process at the time of execution of the task. A maskable interrupt and a non-maskable interrupt that is commanded to execute after the maskable interrupt are included, the maskable interrupt is commanded to execute during an interrupt disable time, and then the non-maskable interrupt is executed.

(73) The non-maskable interrupt is executed when the maskable interrupt cannot be executed.

(74) The interrupt processing means performs the interrupt processing when monitoring a failure of the system.

(75) Task execution means for executing a task, and interrupt processing means for performing an interrupt process at the time of execution of the task are provided. The interrupt processing means includes a first non-maskable interrupt, a maskable interrupt that is commanded to execute after a predetermined time from the first non-maskable interrupt, and a second non-maskable interrupt that is commanded to execute after the maskable interrupt that is after a predetermined time from the first non-maskable interrupt. The interrupt processing means includes a case where the first non-maskable interrupt is commanded to execute during an interrupt disable time, and the maskable interrupt is executed after the interrupt disable time is released, and a case where the first non-maskable interrupt and the maskable interrupt are commanded to execute during the interrupt disable time, and then the second non-maskable interrupt is executed.

(76) The second non-maskable interrupt is executed when the maskable interrupt cannot be executed.