Semiconductor device with a bond pad and a sandwich passivation layer and manufacturing method thereof

Abstract

A method of forming a sandwich passivation layer (405) on a semiconductor device (400) comprising a bond pad (404) is provided. The method comprises forming a first layer (406) over a surface of the semiconductor device (400), removing a part of the first layer (406) to expose a surface of the bond pad (404), forming a second layer (407) over the first layer (406) and the surface of the bond pad (404), and forming a third layer (408) over the second layer (407), wherein the surface of the bond pad (404) is not in contact with the first layer (406) or third layer (408).

Claims

1. A method of forming a sandwich passivation layer on a semiconductor device comprising a bond pad, the method comprising: forming a first layer over a surface of the semiconductor device and over a top surface of the bond pad; removing a part of the first layer to expose the top surface of the bond pad; forming a second layer over the first layer and the top surface of the bond pad; and forming a third layer over the second layer; wherein the top surface of the bond pad is not in contact with the first layer or third layer, and wherein a wettability of the first layer and third layer is higher than a wettability of the second layer.

2. The method according to claim 1 wherein forming the first layer comprises forming the first layer on an initial layer formed on the semiconductor device, wherein removing the part of the first layer further comprises removing a part of the initial layer to expose the top surface of the bond pad, and wherein the top surface of the bond pad is not in contact with the initial layer.

3. The method according to claim 1 further comprising removing a part of the third layer and second layer to expose the top surface of the bond pad.

4. The method according to claim 1 wherein the first layer and third layer are formed from plasma-enhanced TEOS (PETEOS).

5. The method according to claim 1 wherein the second layer is formed from plasma enhanced oxide (PEOX).

6. The method according to claim 1 wherein the semiconductor device is an optical device.

7. The method according to claim 1 wherein the third layer is formed at a deposit rate of 500 A/min or below.

8. The method according to claim 1 wherein the first layer, the second layer, and the third layer are formed using same equipment.

9. A semiconductor device comprising: a bond pad; and a sandwich passivation layer comprising: a first layer on a surface of the semiconductor device, wherein the first layer is formed on an initial layer formed on the semiconductor device; a second layer on the first layer and on a top surface of the bond pad; and a third layer on the second layer; wherein the top surface of the bond pad is not in contact with the initial layer, first layer, or third layer, and wherein a wettability of the first layer and third layer is higher than a wettability of the second layer.

10. The semiconductor device according to claim 9 wherein the first layer and third layer are formed from plasma-enhanced TEOS (PETEOS).

11. The semiconductor device according to claim 9 wherein the second layer is formed from plasma enhanced oxide (PEOX).

12. The semiconductor device according to claim 9 wherein the semiconductor device is an optical device.

13. The semiconductor device according to claim 9 wherein the third layer is formed at a deposit rate of 500 A/min or below.

14. The semiconductor device according to claim 9 wherein the first layer, the second layer, and the third layer are formed using same equipment.

Description

BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENTS

(1) Some embodiments of the disclosure will now be described by way of example only and with reference to the accompanying drawings, in which:

(2) FIG. 1 illustrates a semiconductor device known in the prior art.

(3) FIG. 2a illustrates pad corrosion found at the bond pad in X-ray cross section (XSEM) during failure mode analysis.

(4) FIG. 2b illustrates a failure mechanism of aluminium bond pad corrosion.

(5) FIG. 3 illustrates contamination of a PETEOS film in a passivation layer.

(6) FIG. 4a shows a semiconductor device in accordance with the present disclosure.

(7) FIG. 4b shows a semiconductor device in accordance with the present disclosure.

(8) FIG. 4c shows a semiconductor device in accordance with the present disclosure.

(9) FIG. 4d shows a semiconductor device in accordance with the present disclosure.

(10) FIG. 5 illustrates a method in accordance with the present disclosure.

(11) FIG. 6 illustrates a method in accordance with the present disclosure.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(12) Generally speaking, the disclosure provides a sandwich, or composite, passivation layer to reduce corrosion of a bond pad in a semiconductor device. The sandwich passivation layer comprises a first layer, a third layer and a second layer between the first layer and third layer. This reduces corrosion of the bond pad arising from molecules trapped on a surface of the first layer or third layer.

(13) Some examples of the solution are given in the accompanying figures.

(14) FIG. 4a shows a semiconductor device 400 in accordance with an embodiment of the invention. The semiconductor device 400 comprises a semiconductor substrate 401 on which are formed device layers 402 that provide device structure. In an embodiment, the device structure is an optical structure. For example, the device structure may be a light emitting diode or a photodiode. The device layers 402 further comprise any interconnect layer required to enable connection to parts of the device structure.

(15) An initial layer 403 is formed over the device layers 402. The initial layer 403 may be a top dielectric layer. In an embodiment the initial layer is formed from PETEOS.

(16) The bond pad 404 may be made of an aluminium-copper (AlCu) composite. A surface of the bond pad 404 defines an area on the surface of the top metal layer for forming a metal bond to, for example, a wire, contact, device, or circuit board.

(17) A sandwich passivation layer 405 is formed over the initial layer. The sandwich passivation layer 405 comprises a first layer 406, a second layer 407 over the first layer 406 and the surface of the bond pad 404, and a third layer 408 over the second layer 407. As can be seen from FIG. 4a the surface of the bond pad 404 is not in contact with the first layer 406 or third layer 407.

(18) Referring to both FIG. 4a and FIG. 5 the method for creating the sandwich passivation layer is detailed below.

(19) In step S501, a first layer 406 is formed over the initial layer 403, covering the bond pad 404. The first layer 406 is formed using a CVD process or a PECVD process. The deposit ratio (A/min) for the first layer 406 will depend on the thickness of the metal layer 404. In an embodiment, the deposit ratio is in the range 20008000 A/min. In an embodiment, the first layer 406 is formed from PETEOS.

(20) In step S502, a part of the first layer 406 is removed to form an opening over the bond pad 404. In an embodiment, this is achieved by an etching process. However, it would be apparent to the person skilled in the art that other techniques could be utilised, for example, chemical mechanical polishing (CMP).

(21) In step S503, a second layer 407 is formed over the first layer 406 and the surface of the bond pad 404. The second layer 407 is formed using a CVD process or a PECVD process. The deposit ratio (A/min) for the second layer may be below 500 A/min. In an embodiment, the second layer 407 has a wettability less than the first layer 406. In an embodiment, the second layer 407 is formed from PEOX.

(22) In step S504, a third layer 408 is formed on the second layer 407. The third layer is formed using a CVD process or a PECVD process. In an embodiment, the second layer 407 has a wettability less than the third layer 408. In an embodiment, the third layer 408 is formed from PETEOS.

(23) Referring to FIG. 6, in an embodiment the method may comprise additional steps. Optionally, the initial layer 403 may be formed on the semiconductor device 400 prior to the formation of the first layer 406 (S601). Consequently in S602, the first layer 406 is formed on the initial layer 403 and in S603 part of the first layer 406 and the initial layer 403 are removed to expose the bond pad 404.

(24) Steps S604 and S605 are equivalent to S503 and S504 described above.

(25) In step S606, a part of the third layer 408 and second layer 407 are removed to form an opening over the bond pad 404 and expose the surface of the bond pad 404, as illustrated in FIG. 4b. In an embodiment, this is achieved by an etching process. However, it would be apparent to the person skilled in the art that other techniques could be utilised, for example, chemical mechanical polishing (CMP).

(26) Alternatively, the sandwich passivation layer 405 may then be etched or subjected to CMP so that a much thinner second layer 407 remains on the surface of the bond pad 404, as illustrated in FIG. 4c and FIG. 4d. This thinner second layer 407 would protect the surface of the bond pad 404 until it is needed for metal contacting. An additional removing step would be required to remove the thinner second layer 407 before the metal contact on the surface of the bond pad 404 can be formed.

(27) Embodiments of the present disclosure can be employed in many different semiconductor manufacture applications including optical devices, for example, in the optical device industry and other industries.

LIST OF REFERENCE NUMERALS

(28) 100 a semiconductor device 101 a semiconductor substrate 102 a top dielectric layer 103 a bond pad 104 a passivation layer 104a silicon oxide 104b silicon nitride 400 a semiconductor device 401 a semiconductor substrate 402 device layers 403 an initial layer 404 a bond pad 405 a sandwich passivation layer 406 a first layer 407 a second layer 408 a third layer

(29) The skilled person will understand that in the preceding description and appended claims, positional terms such as above, along, side, etc. are made with reference to conceptual illustrations, such as those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to an object when in an orientation as shown in the accompanying drawings.

(30) Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in any embodiments, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.