METHOD AND APPARATUS FOR ANALOG FLOATING GATE MEMORY CELL

Abstract

A floating-node memory device includes a metal-oxide-semiconductor (MOS) transistor including a first polysilicon gate, a source region, and a drain region in a first well region, a tunneling device including a second polysilicon gate in a second well region, and a metal-insulator-metal (MIM) capacitor including a conductive top plate and a bottom plate formed in a metal interconnect layer. The floating-node device includes a floating-node comprising the first polysilicon gate, the second polysilicon gate, and the conductive top plate of the MIM capacitor coupled together, a control node at the bottom plate of the MIM capacitor, an erase node in the second well region, a source node at the source region of the MOS transistor, and a drain node at the drain region of the MOS transistor.

Claims

1. A non-volatile memory device, comprising: a floating-node memory cell, including: a P-type metal-oxide-semiconductor (PMOS) transistor having a first polysilicon gate; a tunneling device having a second polysilicon gate; and a metal-insulator-metal (MIM) capacitor including a conductive top plate and a bottom plate formed in a metal interconnect layer, wherein the first polysilicon gate, the second polysilicon gate, and the conductive top plate of the MIM capacitor are coupled together to form a floating-node; a high-voltage input node for coupling to a programmable high-voltage source; a high-voltage switch circuit coupled to the high-voltage input node for providing a voltage signal for performing: hot-electron programming of the first polysilicon gate in the PMOS transistor; and tunneling erase of the second polysilicon gate in the tunneling device.

2. The memory device of claim 1, wherein the memory device is disposed in an integrated circuit (IC), and the programmable high-voltage source is disposed external to the IC.

3. The memory device of claim 1, wherein the high-voltage switch circuit comprises: PMOS transistors M1, M2, M3, and M4; NMOS transistors M5, M6, M7, M8, and M9; wherein: M1, M3, M5, M7, and M9 are coupled in series between the high-voltage input node and a ground node, a drain node of M9 coupled to a source node of M9; M2, M4, M6, and M8 are coupled in series between the high-voltage input node and the ground node, a node between M4 and M6 providing a high-voltage signal to the memory device; M1 and M2 are coupled to form a current mirror; a gate node of M3 is coupled to a gate node of M4; a gate note of M3 and gate node M4 is coupled to a power supply; a gate node of M5 and a gate node of M6 are coupled to a power supply voltage; a gate node of M7 and a gate node of M8 are coupled to a control signal and a complement of the control signal, respectively.

4. The memory device of claim 1, wherein the power supply voltage is lower than the voltage at the high-voltage input node.

5. The memory device of claim 1, wherein the first polysilicon gate and the second polysilicon gate are connected by a second layer metal interconnect.

6. The memory device of claim 1, wherein the first polysilicon gate and the second polysilicon gate are connected by a first layer metal interconnect.

7. The memory device of claim 1, wherein the MIM capacitor is characterized by an area that is 50% to 90% of an area of the floating-node memory device.

8. A non-volatile memory device, comprising: a floating-node memory cell disposed in an integrated circuit (IC), including: a floating-node; a control node; an erase node; a source node; and a drain node; a high-voltage input node for coupling to an external programmable high-voltage source external to the IC; and a high-voltage switch circuit coupled to the high-voltage input node for providing a voltage signal for performing: hot-electron programming of charges to the floating node; and tunneling erase of charges from the floating node; wherein the high-voltage switch circuit comprises: PMOS transistors M1, M2, M3, and M4; NMOS transistors M5, M6, M7, M8, and M9; wherein: M1, M3, M5, M7, and M9 are coupled in series between the high-voltage input node and a ground node, a drain node of M9 coupled to a source node of M9; M2, M4, M6, and M8 are coupled in series between the high-voltage input node and the ground node, a node between M4 and M6 providing an high-voltage signal to the memory device; M1 and M2 are coupled to form a current mirror; a gate node of M3 is coupled to a gate node of M4; a gate note of M3 and gate node M4 is coupled to a power supply; a gate node of M5 and a gate node of M6 are coupled to a power supply voltage; and a gate node of M7 and a gate node of M8 are coupled to a control signal and a complement of the control signal, respectively.

9. The memory device of claim 8, wherein the power supply voltage is lower than the voltage at the high-voltage input node.

10. The memory device of claim 8, wherein the floating-node memory cell, includes: a P-type metal-oxide-semiconductor (PMOS) transistor having a first polysilicon gate; a tunneling device having a second polysilicon gate; and a metal-insulator-metal (MIM) capacitor including a conductive top plate and a bottom plate formed in a metal interconnect layer, wherein the first polysilicon gate, the second polysilicon gate, and the conductive top plate of the MIM capacitor are coupled together to form the floating-node.

11. The memory device of claim 10, wherein the floating-node device comprises: a control node at the bottom plate of the MIM capacitor; an erase node at a well region of the tunneling device; a source node at a source region of the PMOS transistor; and a drain node at a drain region of the PMOS transistor.

12. The memory device of claim 10, wherein the first polysilicon gate and the second polysilicon gate are connected in the second layer metal interconnect.

13. The memory device of claim 10, wherein the first polysilicon gate and the second polysilicon gate are connected in the first layer metal interconnect.

14. The memory device of claim 10, wherein the MIM capacitor is disposed over the PMOS transistor and the tunneling device.

15. A method for operating a non-volatile memory device, comprising: providing a floating-node memory cell, including: a P-type metal-oxide-semiconductor (PMOS) transistor having a first polysilicon gate; a tunneling device having a second polysilicon gate; and a metal-insulator-metal (MIM) capacitor including a conductive top plate and a bottom plate formed in a metal interconnect layer, wherein the first polysilicon gate, the second polysilicon gate, and the conductive top plate of the MIM capacitor are coupled together to form a floating-node; coupling a programmable high-voltage source to a high-voltage input node, which is coupled to a high-voltage switch circuit for providing a high-voltage signal; coupling an output of the high-voltage switch circuit to an erase node; ramping the programmable high-voltage source to a first high voltage in a first ramp time; maintaining the first high voltage for a first duration to perform an erase operation; coupling an output of the high-voltage switch circuit to a program node; ramping the programmable high-voltage source to a second high voltage in a second ramp time; and maintaining the second high voltage for a second duration to perform a program operation.

16. The method of claim 15, wherein the high-voltage switch circuit comprises: PMOS transistors M1, M2, M3, and M4; NMOS transistors M5, M6, M7, M8, and M9; wherein: M1, M3, M5, M7, and M9 are coupled in series between the high-voltage input node and a ground node, a drain node of M9 coupled to a source node of M9; M2, M4, M6, and M8 are couple in series between the high-voltage input node and the ground node, a node between M4 and M6 providing an high-voltage signal to the memory device; M1 and M2 are coupled to form a current mirror; a gate node of M3 is coupled to a gate node of M4; a gate node of M5 and a gate node of M6 are coupled to a power supply voltage; and a gate node of M7 and a gate node of M8 are coupled to a control signal and a complement of the control signal, respectively.

17. The method of claim 16, wherein the memory device is disposed in an integrated circuit (IC), and the programmable high-voltage source is disposed external to the IC.

18. The method of claim 16, wherein the power supply voltage is lower than the voltage at the high-voltage input node.

19. The method of claim 16, further comprising selecting the first ramp time and the second ramp time in the programmable high-voltage source to avoid overstressing the memory device.

20. The method of claim 16, further comprising selecting the first high voltage and the second high voltage in the programmable high-voltage source to avoid overstressing the memory device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] A further understanding of the nature and advantages of the present invention may be realized by reference to the following drawings. In the appended figures, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description can be applicable to any one of the similar components having the same first reference label irrespective of the second reference label.

[0016] FIG. 1 is a simplified cross-sectional view of a floating-node memory device according to some embodiments;

[0017] FIG. 2 is a simplified flowchart illustrating a method for forming a floating node memory cell according to some embodiments;

[0018] FIG. 3 is a simplified schematic diagram illustrating part of a nonvolatile memory array according to some embodiments;

[0019] FIG. 4 and FIG. 5 are waveform diagrams illustrating simulated waveforms of signals for programming the memory array according to some embodiments;

[0020] FIG. 6 is a schematic diagram illustrating a high-voltage (HV) transfer switch circuit according to some embodiments;

[0021] FIG. 7 is a schematic diagram illustrating a y-decoder column select pass transistor and a column bias circuit according to some embodiments;

[0022] FIG. 8 is a simplified schematic diagram illustrating a sense amplifier read circuit according to some embodiments; and

[0023] FIG. 9 is a waveform diagram illustrating simulated waveforms for signals associated with the current comparator 810 in the sense amplifier read circuit 800 in FIG. 8.

DETAILED DESCRIPTION OF THE INVENTION

[0024] Aspects of the disclosure are described more fully hereinafter with reference to the accompanying drawings, which form a part hereof, and which show, by way of illustration, example features. The features can, however, be embodied in many different forms and should not be construed as limited to the combinations set forth herein; rather, these combinations are provided so that this disclosure will be thorough and complete, and will convey the scope. Among other things, the features of the disclosure can be facilitated by methods, devices, and/or embodied in articles of commerce. The following detailed description is, therefore, not to be taken in a limiting sense.

[0025] FIG. 1 is a simplified cross-sectional view of a floating-node memory device according to some embodiments. As shown in FIG. 1, a floating-node memory device 100 is disposed in a p-type substrate, for example, a silicon substrate. The floating-node memory device 100 includes a P-type metal-oxide-semiconductor (PMOS) transistor 110 that includes a first polysilicon gate 111 over a gate oxide 112 over a first N-well region 113. Floating-node memory device 100 also includes a tunneling device 120 including a second polysilicon gate 121 over a tunneling oxide 122 over a second N-well region 123. Floating-node memory device 100 further includes a metal-insulator-metal (MIM) capacitor 130, which includes a conductive top plate 131 and a bottom plate 132 that is part of an (N−1)st layer metal interconnect M(N−1). As used herein, N is an integer greater than or equal to 3. A standard CMOS process is often characterized by the number of interconnect metal layers above the devices formed in the substrate and the polysilicon gate or interconnect layers. For example, an N-layer metal CMOS process includes a first layer metal M1, a second layer metal M2, . . . , and a top layer metal MN, where N is an integer. The layer of metal interconnect immediately below the top layer metal MN is often referred to as the top-minus-1 layer, or M(N−1).

[0026] In floating-node memory device 100, the first polysilicon gate 111, the second polysilicon gate 121, and the conductive top plate 131 of the MIM capacitor 130 are coupled together to form a floating node of the memory device 100. In FIG. 1, the floating node is designated with labels FG, and the voltage associated with the floating node is labeled V.sub.FG. In the embodiment in FIG. 1, the first polysilicon gate 111, the second polysilicon gate 121, and the conductive top plate 131 of the MIM capacitor 130 are coupled together through a portion 141 of the N.sup.st layer metal interconnect MN to form the floating node of the memory device. The connection of the conductive top plate 131 of the MIM capacitor 130 to the polysilicon gates 111 and 121 also includes the first, second, . . . , and the (N−1).sup.st layers of metal interconnect.

[0027] The memory device 100 in FIG. 1 is configured to be programmed by hot-electron injection in the PMOS transistor 110 and erased by tunneling in the tunneling device 120, with the bottom plate 132 of the MIM capacitor 130 as a control gate CG, with associated voltage V.sub.CG.

[0028] In some embodiments, as shown in FIG. 1, the first polysilicon gate 111 and the second polysilicon gate 121 are connected by a second layer metal interconnect 142. In some embodiments, as shown in FIG. 1, the first polysilicon gate 111 and the second polysilicon gate 121 are connected by a first layer metal interconnect (not shown). In some embodiments, the floating-node memory device is characterized by a single polysilicon layer, and both the first polysilicon gate 111 and the second polysilicon gate 121 are formed in the single polysilicon layer. In this case, the first polysilicon gate is a first portion of the single polysilicon layer, and the second polysilicon gate is a second portion of the single polysilicon layer. In some cases, the first polysilicon gate 111 and the second polysilicon gate 121 are connected by a polysilicon line formed in the single polysilicon layer.

[0029] In some embodiments, the MIM capacitor 130 is disposed over the PMOS transistor 110 and the tunneling device 120. The MIM capacitor can be made as large as the combined area of the PMOS transistor 110 and the tunneling device 120 without increasing the size of the memory cell. In some embodiments, the MIM capacitor is characterized by an area that is 50% to 90% of an area of the floating-node memory device.

[0030] In some embodiments, the conductive top plate 131 of the MIM capacitor is made of a titanium nitride (TiN) material disposed between the (N−1).sup.st layers of metal interconnect and the N.sup.st layers of metal interconnect. For example, in an embodiment, the CMOS process is a four-layer metal process with N=4. The conductive top plate 131 of the MIM capacitor is made of a titanium nitride (TiN) material disposed between the third layers of metal interconnect and the fourth layers of metal interconnect.

[0031] In some embodiments, the memory device described above can be fabricated using a standard single polysilicon CMOS process. The MIM capacitor is often offered as an option of a standard CMOS process by foundries. As described above, in some embodiments, the MIM capacitor is characterized by an area that is 50% to 90% of an area of the floating-node memory device. Therefore, the floating device described here can be fabricated using a simpler process and can provide substantially greater charge storage capacity than standard non-volatile memory technology, such as the Flash EEPROM process. In some embodiments, the tunneling oxide 122 and gate oxide 112 can be formed in the same gate oxide process, further simplifying the fabrication process.

[0032] FIG. 2 is a simplified flowchart 200 illustrating a method for forming floating node memory cell according to some embodiments. As shown in FIG. 2, the method can be summarized as follows. [0033] Process 210—forming a first N-well region and a second N-well region in a P-type substrate; [0034] Process 220—forming P-type source and drain regions and N-type contact regions in the first N-well region; [0035] Process 230—forming N-type contact regions in the second N-well region; [0036] Process 240—depositing a polysilicon layer over the gate oxide layer; [0037] Process 250—patterning the polysilicon layer to form a first polysilicon gate in the first N-well region and a second polysilicon gate in the second N-well region; [0038] Process 260—forming interconnect structures including N layers of metal interconnects, where N is an integer greater than or equal to 3; [0039] Process 270—forming a bottom plate of a metal-insulator-metal (MIM) capacitor in an (N−1)st layer of metal interconnect; and [0040] Process 280—forming a top plate of the MIM capacitor between the (N−1)st layer and an Nst layer of metal interconnect.

[0041] The above sequence of processes provides a method for forming a floating node memory cell according to an embodiment of the present invention. As shown, the method uses a combination of steps. Other alternatives can also be provided where steps are added, one or more steps are removed, or one or more steps are provided in a different sequence without departing from the scope of the claims herein. Further details of the present method can be found throughout the present specification and more particularly below.

[0042] In some embodiments, the method also includes forming a connection through the Nst layer of metal interconnect between the top plate of the MIM capacitor and the first polysilicon gate and a second polysilicon gate.

[0043] In some embodiments, the method also includes forming a connection between the first polysilicon gate and a second polysilicon gate in a second layer metal interconnect.

[0044] In some embodiments, the method also includes forming a connection between the first polysilicon gate and a second polysilicon gate in a first layer metal interconnect.

[0045] In some embodiments, the method also includes forming the top plate of the MIM capacitor using a titanium nitride (TiN) material.

[0046] In some embodiments, the method also includes forming P-type source and drain regions in the first N-well region for a p-type metal-oxide-semiconductor (PMOS) transistor.

[0047] In some embodiments, the method also includes forming an N-type contact region in the second N-well region for a tunneling device.

[0048] In some embodiments, the method also includes forming an N-type contact region in the second N-well region for a tunneling device as a tunneling node for the floating node memory cell.

[0049] Referring back to FIG. 1, the floating-node memory device 100 includes a floating-node FG comprising the first polysilicon gate 111, the second polysilicon gate 121, and the conductive top plate 131 of the MIM capacitor 130 coupled together, a control node CG at the bottom plate 132 of the MIM capacitor 130, an erase node 125 with a voltage V.sub.TUN in the second well region 123, a source node 115 at the source region of the PMOS transistor 110, and a drain node 116 at the drain region of the PMOS transistor 110. The memory device 100 is configured to be programmed by hot-electron injection in the MOS transistor and erased by tunneling in the tunneling device, with the bottom plate of the MIM capacitor as a control gate. More details are described below.

[0050] As shown in FIG. 1, the polysilicon gate 111 of the PMOS 110 is the floating node that connects to the charge storage capacitor and the tunneling device 120. In this example, the MOS tunneling device 120 is an N+ poly gate over an N-Well bottom plate. The charge storage capacitor is the Metal-Insulator-Metal (MIM) capacitor 130 that is formed in the metal layers of the CMOS process. The MIM capacitor is typically formed between the top metal layer and the metal layer below. For some processes, the MIM capacitor may be formed between lower adjacent metal layers. In some embodiments, the top plate 131 of MIM the is a thin metallic layer, for example, a TiN layer, deposited on top of a thin dielectric layer 133. For this case, the capacitor can cover the entire cell, providing more charge storage than the typical floating gate memory cell of the same size.

[0051] In FIG. 1, the source of the PMOS transistor 110, also referred to as PFET 110, is connected to a voltage V.sub.SRC, the drain is connected to a voltage VD and the gate to the floating gate to a voltage V.sub.FG. In FIG. 1, the bulk of the PFET 110 is also connected to V.sub.SRC in this embodiment. This is because the V.sub.SRC voltage can rise to 5V while, typically, the bulk of the PFET is normally connected to the VDDA which is much lower than V.sub.SRC Hence, if V.sub.SRC>VBulk, the parasitic diode formed between the p+ junction on the source of the PFET and its N+ bulk region would become forward biased.

[0052] In some embodiments, to erase the floating node FG, the voltages on the V.sub.SRC and V.sub.CG are set to 0V and apply 7V on the V.sub.TUN, which is the voltage on the tunneling node in the second N-well region 123. At the same time, the drain 115, is left floating. The electrons are pulled off the FG by Fowler-Nordheim tunneling, leaving behind a net positive charge on the FG capacitor. Typically, multiple cells can be erased at the same time. Normally, a memory is first erased to set the starting point of the cells. Then, only cells that need to be written to the opposite state need to be programmed.

[0053] In some embodiments, to write the FG cell, the voltage on the V.sub.SRC is set to 5V, V.sub.CG to 3.3V, and 0V on the V.sub.TUN. At the same time, the drain 115, is left floating. Under these conditions, the high electric field between the V.sub.SRC and polysilicon gate 111 of PFET 110 induces hot-electron injection and electrons are pulled onto the polysilicon gate 111. This leaves a net negative charge on the floating-gate MIM capacitor, which includes all the capacitances associated with the components of the floating node as described above. Writing to the memory is typically on a Byte (8-bit) or Word (16-bit) basis. To write the cells, the data to be written is loaded into the data buffers and then applied to the memory cells being addressed. Assuming erased cells are logic “1”, then only cells that need to be written to logic “0” are programed since the other cells are already in the correct state.

[0054] In some embodiments, to read the FG cell, the V.sub.SRC voltage is set to 2V, and V.sub.TUN and VCG set to 0V. A sense amplifier connected to the drain of PFET 110, is then used to compare the current of the PFET 110 with a reference current. The current of the PFET 110 is a function of the charge stored on the floating gate and is proportional to (V.sub.FG−V.sub.SRC)−Vtp, where V.sub.FG is the voltage on the floating gate and Vtp is the threshold voltage of the pFET 110. If the I.sub.CELL current is greater than I.sub.REF of the sense amplifier, the Vout is a logic “1” and if I.sub.CELL current is less than I.sub.REF of the sense amplifier the Vout is a logic “0.”

[0055] FIG. 3 is a simplified schematic diagram illustrating part of a nonvolatile memory array according to some embodiments. For simplicity, this diagram only shows one row and two of sixteen columns, but this pattern can be repeated for n×m rows and columns to define the size of the memory array, where n and m are integers. The floating gate cell in column 1 is labeled Fgcell<0>, with associated column bias Col_bias<0>, column voltage Vcol<0>, drain voltage Vrd<0>, and read signal Fgm_rd<0>. Similarly, the floating gate cell in column 15 is labeled Fgcell<15>, with associated column bias Col_bias<15>, drain voltage Vrd<15>, column voltage Vcol<15>, and read signal Fgm_rd<15>. The common voltage lines are tunneling node voltage V.sub.TUN, control node voltage VCG, and source node voltage V.sub.SRC. FIG. 3 also shows a Y-decoder signal Ysel<15:0> to select 1 of 16 columns to connect to the V.sub.SRC line through multiplexers 301 and 302, respectively. Similarly, for row select, there would be an X-decoder to select 1 of n rows, which is not shown.

[0056] According to some embodiments, a method for operating a non-volatile memory device includes providing a floating-node memory cell, including a P-type metal-oxide-semiconductor (PMOS) transistor having a first polysilicon gate, a tunneling device having a second polysilicon gate, and a metal-insulator-metal (MIM) capacitor including a conductive top plate and a bottom plate formed in a metal interconnect layer. The first polysilicon gate, the second polysilicon gate, and the conductive top plate of the MIM capacitor are coupled together to form a floating-node. The method also includes coupling a programmable high-voltage source to a high-voltage input node, which is coupled to a high-voltage switch circuit for providing a high-voltage signal. The method also includes coupling an output of the high-voltage switch circuit to an erase node, ramping the programmable high-voltage source to a first high voltage in a first ramp time, and maintaining the first high voltage for a first duration to perform an erase operation. The method further includes coupling an output of the high-voltage switch circuit to a program node, ramping the programmable high-voltage source to a second high voltage in a second ramp time, and maintaining the second high voltage for a second duration to perform a program operation. More details are provided below with reference to FIGS. 4-9.

[0057] FIGS. 4 and 5 are waveform diagrams illustrating simulated waveforms of signals for programming the memory array according to some embodiments. In FIGS. 4 and 5, the horizontal axis is time, and the vertical axes show voltage waveforms for various signals. Waveform diagram (A) shows the waveform for a voltage VPP from an adjustable high-voltage line. Waveform diagram (B) shows the waveforms of the tunneling node voltage Vtun and the source node voltage V.sub.SRC. Waveform diagram (C) shows the waveform for Erase, Write, and Read signals. Waveform diagram (D) is the waveform for the column select signal Vcol.

[0058] In some embodiments, the program sequence is as follows: [0059] 1. Start programming cycle [0060] 2. Enable program mode (erase or write) [0061] 3. Set control gate voltage VCG=V.sub.SRC=0V [0062] 4. Enable Erase mode [0063] 5. Ramp VPP voltage to 7V in 1 ms [0064] 6. Keep VPP=7V for 1 mS (for erase) [0065] 7. At time T1, Disable Erase mode [0066] 8. Set Data for write [0067] 9. Select column address for write [0068] 10. Set control gate voltage VCG=3.3V [0069] 11. Ramp VPP=5V (=V.sub.TUN) [0070] 12. Keep VPP=5V for 1 mS (for write) [0071] 13. Ramp VPP=0V in 1 mS(=V.sub.SRC) [0072] 14. End programming cycle [0073] 15. At time T2, enter read mode

[0074] In this example, the ramp time was chosen to be 1 mS, but this can be varied as required. The voltage on Vcol is determined by the data to be written. As shown in FIG. 4, if data=1, the Vcol voltage is <0.5V, and no hot-electron injection can occur. On the other hand, as shown in FIG. 5, if data=0, then Vcol=V.sub.SRC=5V, and hot-electron injection can occur on the cells connected on that column.

[0075] The above sequence of processes provides a method for operating a non-volatile memory device according to an embodiment of the present invention. As shown, the method uses a combination of steps. Other alternatives can also be provided where steps are added, one or more steps are removed, or one or more steps are provided in a different sequence without departing from the scope of the claims herein. Further details of the present method can be found throughout the present specification.

[0076] FIG. 6 is a schematic diagram illustrating a high-voltage (HV) transfer switch circuit according to some embodiments. A first HV switch circuit 610 is a VPP HV switch circuit, and is used to transfer the VPP high-voltage to the V.sub.TUN or V.sub.SRC for inducing either Fowler-Nordheim tunneling or hot-electron injection on the floating-gate. HV switch circuit 610 includes a high-voltage input node 612 for coupling to a high-voltage VPP from a programmable voltage source. In some embodiments, the high-voltage VPP is provided by an external programmable voltage source, for example, a tester, such as a memory tester.

[0077] HV switch circuit 610 includes transistors M1, M2, M3, M4, M5, M6, M7, M8, and M9, and voltage signals VPP, VCCH, erase, eraseb (erase bar, the complement of signal erase), and a high-voltage output signal Vhv. In HV switch circuit 610, when erase=1, eraseb=0, the transistor nFET M7 is ON and nFET M8 is OFF. The VPP voltage is transferred to the high-voltage output signal Vhv, which can be connected to V.sub.TUN or V.sub.SRC.

[0078] The transistors M5 and M6 in HV switch circuit 610 limit the voltage on the drain of transistors M7 and M8 from being overstressed and keep their drain voltage limited to VCCH−V.sub.TN, where VCCH is a supply voltage to the memory chip and, in an example, VCCH=3.3V, and V.sub.TN is the threshold of the nFET transistor. Similarly, the gate of transistors M3 and M4 is also connected to VCCH=3.3V to limit overstress of M1 and M2 when VHV follows VPP and goes to a high voltage ≥5V.

[0079] A second HV switch circuit 620 is a y-decoder select column switch and includes transistors M1, M2, and M3. In the erase mode, when the signal gdin=0, all ycol-sel lines will get VPP. This will block the y-select pass gate transferring V.sub.SRC to the columns. At the same time, the column gets pulled to 0V by the column bias circuits. The gdin signal is generated by a control logic circuit 630 with an AND gate receiving an input data signal and the erase signal through an inverter.

[0080] In HV switch circuit 620, the y-decoder select column switch, the high voltage VPP is transferred to the output in write mode depending on the data. The control logic 630, sets state of the output voltage signal, gdin. If the data=0, the AND gate output, gdin=0 and ycol_sel=VPP. If the data=1, then gdin=1 (erase=0 in write mode), and the ycol_sel is pulled low.

[0081] FIG. 7 is a schematic diagram illustrating a y-decoder column select pass transistor 710 and a column bias circuit 720 according to some embodiments. The y-sel column select transistor 710 includes a transistor M0 having a gate node receiving the ysel signal, a drain node coupled to the Vcol signal, a source node coupled to the V.sub.SRC signal, and a substrate node coupled to the source node V.sub.SRC. The y-sel column select transistor 710 passes the V.sub.SRC voltage to the columns via the Vcol signal and to cells to be written via hot-electron injection by forcing the V.sub.SRC of the cell to 5V.

[0082] The column bias circuit 720 includes transistors M1, M2, M3, and M4 receiving signals readb, VCCH, VCCH, and erase, respectively. The column bias circuit 720 is used to force 0V on the column during the erase cycle (readb=1, erase=1) or 2V during read mode (readb=0, erase=0).

[0083] FIG. 8 is a simplified schematic diagram illustrating a sense amplifier read circuit according to some embodiments. As shown in FIG. 8, sense amplifier read circuit 800 includes a current comparator 810 formed by transistors M1 and M2, two pass gates (MX1, MX2), and three inverters (I1, I2, I3). The pass gate MX1 is ON in read mode and passes voltage V1 to the inverter I1, which drives the output buffer I3. The pass gate MX2 is OFF in the read mode. A reset signal is connected to transistor M3, and pulls down voltage on node V2 to 0V on chip power-up. The voltage on node V2 drives inverter I1. The inverter I1 drives the output buffer I3 and the feedback inverter I2. After the sense amplifier exits the read mode, the pass gate MX1 turns OFF, and pass gate MX2 turns ON and latches the data on node V2. The operation of the sense amplifier read circuit 800 is further explained with reference to the waveforms in FIG. 9.

[0084] FIG. 9 is a waveform diagram illustrating simulated waveforms for signals associated with the current comparator 810 in the sense amplifier read circuit 800 in FIG. 8. In FIG. 9, the horizontal axis is read column voltage (Vrd), and the vertical axis is voltage for various signals. In read mode, the transistor M1 is on and connects the read column voltage (Vrd) to the sense amplifier. The gate of transistor M2 is connected to the output of a current mirror, which sets the sense amplifier reference current I.sub.REF. This reference current can be adjusted from 2 uA to 16 uA in some embodiments. FIG. 9 shows two waveforms for V1: waveform 901 with Ibias at 2.5 uA (with signal ctrl=0) and waveform 902 for Ibias at 16 uA (with signal ctrl=7). This plot shows the sense amplifier trip-point vs. the voltage on the floating gate V.sub.FG, which is swept from 0V to 1.8V.

[0085] The cell current I.sub.CELL is a function of the charge on the floating gate. This charge is converted to a voltage by virtue of the MIM capacitor on the floating gate. The sense amplifier subtracts the I.sub.REF current from the I.sub.CELL current. The output of the sense amplifier is then determined as follows: [0086] If I.sub.CELL>I.sub.REF, V1=“1” and hence, Vout=“1” [0087] If I.sub.CELL<I.sub.REF, V1=“0” and hence, Vout=“0”

[0088] The sense amplifier reads the state of the charge on the floating gate. If the cell was erased, there would be a net positive charge on the floating gate, and the I.sub.CELL current would be low; hence the sense amplifier output voltage Vout=0. If the cell was written, there would be a net negative charge on the floating gate, and the I.sub.CELL current would be high. Hence, the sense amplifier output voltage Vout=1.

[0089] As described above with reference to FIGS. 1-9, a non-volatile memory device includes one or more of floating-node memory cells. An example of the memory device is non-volatile memory device 300 in FIG. 3. An example of a floating-node memory cell is floating node memory device 100 in FIG. 1. As shown in FIG. 1, floating node device 100 includes a P-type metal-oxide-semiconductor (PMOS) transistor 110 having a first polysilicon gate 111, a tunneling device 120 having a second polysilicon gate 121, and a metal-insulator-metal (MIM) capacitor 130 including a conductive top plate 131 and a bottom plate 132 formed in a metal interconnect layer. The first polysilicon gate 111, the second polysilicon gate 121, and the conductive top plate 131 of the MIM capacitor are coupled together to form a floating-node FG. The non-volatile memory device 300 also includes a high-voltage input node for coupling to a programmable high-voltage source. As shown in FIG. 6, non-volatile memory device 300 also includes a high-voltage switch circuit 610 coupled to the high-voltage input node 612 for providing a voltage signal Vhv. Voltage signal Vhv is a high-voltage signal for performing hot-electron programming of the first polysilicon gate 111 in the PMOS transistor, and tunneling to erase, the second polysilicon gate 121 in the tunneling device 120.

[0090] In some embodiments, the memory device is disposed in an integrated circuit (IC), and the programmable high-voltage source is disposed external to the IC. For example, the programmable high-voltage source can be an external tester.

[0091] As mentioned previously, using an internal charge pump and ramp generator to control the VPP voltage rise/fall time and pulse-width (PW) is very costly in terms of chip area and power dissipation. Therefore, in some embodiments, an external tester is used to provide complete control of the VPP pulse. In order to reduce voltage overstress across the drain-gate interface of the pFET in the floating-gate transistor, it is desirable to drive the VPP high-voltage slowly (step/ramp) and keep it applied for a certain time (pulse-width) to allow charge transfer to occur, but prevent oxide damage. The VPP can either be (a) a test pin on the chip or simply (b) a metal pad that is not bonded out for wafer-level access. A dedicated test pin provides more flexibility to program the floating-gate memory at the package level. For case (b), a probe card can be used to perform the programming at the wafer level.

[0092] By using an external tester to drive the VPP pulse, a user can adjust the rise/fall time or the pulse width and find the best procedure to program the cells with good reliability. Since the pulse shape can be easily modified by a simple code change on the tester, it gives the user more flexibility to shape the VPP pulse for best programming results. The ramp on the VPP pulse is controlled by the external tester with either course or fine steps. In some embodiments, the VPP signal can be driven by a Chroma 3380P ATE tester with rise/fall/PW=2 mS. It is understood that other testers or external programmable voltage sources can also be used.

[0093] Certain embodiments have been described. However, various modifications to these embodiments are possible, and the principles presented herein may be applied to other embodiments as well. In addition, the various components and/or method steps/blocks may be implemented in arrangements other than those specifically disclosed without departing from the scope of the claims. Other embodiments and modifications will occur readily to those of ordinary skill in the art in view of these teachings. Therefore, the following claims are intended to cover all such embodiments and modifications when viewed in conjunction with the above specification and accompanying drawings.