HIGH ELECTRON MOBILITY TRANSISTOR AND FABRICATING METHOD OF THE SAME

Abstract

A fabricating method of a high electron mobility transistor includes providing a substrate. Then, a channel layer, an active layer, a P-type group III-V compound material layer, a metal compound material layer, a hard mask material layer and a patterned photoresist are formed to cover the substrate. Later, a dry etching process is performed to etch the hard mask material layer and the metal compound material layer to form a hard mask and a metal compound layer by taking the patterned photoresist as a mask. During the dry etching process, a spacer generated by by-products is formed to surround the patterned photoresist, the hard mask and the metal compound layer. After the dry etching process, the P-type group III-V compound material layer is etched by taking the spacer and the patterned photoresist as a mask.

Claims

1. A fabricating method of a high electron mobility transistor, comprising: providing a substrate; forming a channel layer, an active layer, a P-type group III-V compound material layer, a metal compound material layer, a hard mask material layer and a photoresist from bottom to top to cover the substrate; patterning the photoresist to form a patterned photoresist; performing a dry etching process to etch the hard mask material layer and the metal compound material layer to transform the hard mask material layer into a hard mask and the metal compound material layer into a metal compound layer by taking the patterned photoresist as a first mask, wherein a spacer surrounds the patterned photoresist, the hard mask and the metal compound layer, and the spacer is generated by by-products which are formed during the dry etching process; and after the dry etching process, etching the P-type group III-V compound material layer by taking the spacer and the patterned photoresist as a second mask; and removing the spacer, the patterned photoresist and the hard mask.

2. The fabricating method of a high electron mobility transistor of claim 1, further comprising: after removing the spacer, the patterned photoresist and the hard mask, forming a source electrode, a drain electrode and a gate electrode on the substrate.

3. The fabricating method of a high electron mobility transistor of claim 1, wherein the etching gas used during the dry etching process comprises C.sub.4F.sub.8, SF.sub.6, CF.sub.4, CH.sub.xF.sub.4-x, BCl.sub.3 or Cl.sub.2, and X is a positive number which is smaller than 4.

4. The fabricating method of a high electron mobility transistor of claim 3, wherein an operational power of the dry etching process is greater than 100 W, and an operational pressure of the dry etching process is greater than 50 mTorr.

5. The fabricating method of a high electron mobility transistor of claim 1, wherein the spacer comprises carbon, silicon, fluorine, titanium or chlorine.

6. The fabricating method of a high electron mobility transistor of claim 1, wherein while etching the P-type group III-V compound material layer, the active layer serves as an etching stop layer.

7. The fabricating method of a high electron mobility transistor of claim 1, wherein the channel layer comprises gallium nitride, gallium indium nitride, aluminum gallium nitride, aluminum indium nitride, aluminum indium gallium nitride or aluminum nitride.

8. The fabricating method of a high electron mobility transistor of claim 1, wherein the active layer comprises aluminum gallium nitride, aluminum indium nitride, aluminum indium gallium nitride or aluminum nitride.

9. The he fabricating method of a high electron mobility transistor of claim 1, wherein the P-type group III-V compound material layer comprises P-type gallium nitride.

10. The he fabricating method of a high electron mobility transistor of claim 1, wherein the hard mask comprises silicon nitride and the metal compound layer comprises titanium nitride or tantalum nitride.

11. A high electron mobility transistor, comprising: a substrate; a channel layer, an active layer, a P-type group III-V gate and a metal compound layer disposed on the substrate, wherein the channel layer, the active layer, the P-type group III-V gate and the metal compound layer are disposed from bottom to top, the metal compound layer contacts the P-type group III-V gate, the metal compound layer has two sidewalls which are opposed to each other, two acute angles are respectively formed between one of the two sidewalls and a top surface of the P-type group III-V gate and between the other of the two sidewalls and the top surface of the P-type group III-V gate; and a source electrode, a drain electrode and a gate electrode disposed on the active layer.

12. The high electron mobility transistor of claim 11, wherein each of the two acute angles is between 30 and 80 digresses.

13. The high electron mobility transistor of claim 11, wherein the metal compound layer only covers part of the P-type group III-V gate.

14. The high electron mobility transistor of claim 11, wherein the metal compound layer comprises titanium nitride or tantalum nitride.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1, FIG. 2, FIG. 3A, FIG. 3B, FIG. 4 to FIG. 6 depict a fabricating method of a high electron mobility transistor according to a preferred embodiment of the present invention, wherein:

[0009] FIG. 1 shows a substrate with a channel layer, an active layer, a P-type group III-V compound material layer, a metal compound material layer, a hard mask material layer and a photoresist thereon;

[0010] FIG. 2 is a fabricating stage following FIG. 1;

[0011] FIG. 3A is a fabricating stage following FIG. 2;

[0012] FIG. 3B depicts a top view of FIG. 3A;

[0013] FIG. 4 is a fabricating stage following FIG. 3A;

[0014] FIG. 5 is a fabricating stage following FIG. 4; and

[0015] FIG. 6 is a fabricating stage following FIG. 5.

DETAILED DESCRIPTION

[0016] FIG. 1, FIG. 2, FIG. 3A, FIG. 3B, FIG. 4 to FIG. 6 depict a fabricating method of a high electron mobility transistor according to a preferred embodiment of the present invention, wherein FIG. 3B depicts a top view of FIG. 3A.

[0017] As shown in FIG. 1, a substrate 10, a channel layer 12, an active layer 14, a P-type group III-V compound material layer 16, a metal compound material layer 18, a hard mask material layer 20 and a photoresist 22 are formed to cover the substrate 10 in sequence. The substrate 10, the channel layer 12, the active layer 14, the P-type group III-V compound material layer 16, the metal compound material layer 18, the hard mask material layer 20 and the photoresist 22 are stacked from bottom to top. Next, as shown in FIG. 2, the photoresist 22 is etched to be transformed into a patterned photoresist 22a. The pattern which will be patterned into the metal compound material layer 18 is defined on the patterned photoresist 22a. The P-type group III-V compound material layer 16 includes P-type gallium nitride. The metal compound material layer 18 includes titanium nitride or tantalum nitride. The hard mask material layer 20 includes silicon nitride. The metal compound material layer 18 used in this embodiment is titanium nitride.

[0018] As shown in FIG. 2, FIG. 3A and FIG. 3B, a dry etching process 24 is performed. The dry etching process 24 includes dry etching the hard mask material layer 20 and the metal compound material layer 18 by taking the patterned photoresist 22a as a first mask. It is noteworthy that when the hard mask material layer 20 and the metal compound material layer 18 are dry etched, by-products generated during the dry etching process 24 attach on the hard mask material layer 20 and the metal compound material layer 18. As the dry etching process 24 is processing, the by-products are getting thicker, and a spacer 26 will be formed by by-products when the dry etching process 24 is completed. After the dry etching process 24, the hard mask material layer 20 is transformed into a hard mask 20a, the metal compound material layer 18 is transformed into a metal compound layer 18a, and the spacer 26 formed by by-products surrounds the patterned photoresist 22a, the hard mask 20a and the metal compound layer 18a. The composition of the spacer 26 includes C, Si, F, Ti or Cl. If different etching gas is used during the dry etching process 24, compositions of the spacer 26 will become different. For example, the spacer 26 could be polymers containing C, F and Cl.

[0019] According a preferred embodiment of the present invention, the etching gas used during the dry etching process 24 includes C.sub.4F.sub.8, SF.sub.6, CF.sub.4, CH.sub.xF.sub.4-x, BCl.sub.3 or Cl.sub.2. X is a positive number which is smaller than 4. Furthermore, gas such as He can be used to dilute the concentration of the etching gas. Moreover, an operational power of the dry etching process is preferably greater than 100 W, and an operational pressure of the dry etching process is greater than 50 mTorr. The spacer 26 can be formed more easily when the operational pressure is greater. In addition, a thickness of the spacer 26 can be adjusted by changing parameters of the dry etching process 24 such as changing the flow rate of etching gas, using different etching gas, adjusting the operational pressure or adjusting the operational power. For example, etching gas used during the dry etching process 24 may include CHF.sub.3 and SF.sub.6, and the etching gas is diluted by He. Concentration of SF.sub.6 is between 3 and 20 standard cubic centimeter per minute (sccm). Concentration of CHF.sub.3 is between 20 and 80 sccm. Concentration of He is between 50 and 200 sccm. The operational pressure of the dry etching process 24 is between 700 and 1300 mTorr. The operational pressure of the dry etching process 24 is between 200 and 800 W.

[0020] As shown in FIG. 3A and FIG. 4, another dry etching process 28 is performed. The dry etching process 28 includes etching the P-type group III-V compound material layer 16 by taking the spacer 26 and the patterned photoresist 22a as a second hard mask and taking the active layer 14 as an etching stop layer. The P-type group III-V compound material layer 16 which is etched becomes a P-type group III-V gate 16a. Because the spacer 26 serves as the second hard mask when defining the P-type group III-V gate 16a, the width W of the P-type group III-V gate 16a is influenced by the thickness T of the spacer 26. When the thickness T of the spacer 26 increases, the width W of the P-type group III-V gate 16a increases as well. The width W of the P-type group III-V gate 16a and the thickness T of the spacer 26 are respectively parallel to the top surface of the substrate 10. The width W of the P-type group III-V gate 16a have an influence on the threshold voltage of a high electron mobility transistor. The thickness T of the spacer 26 can adjust the width W of the P-type group III-V gate 16a. Therefore, the threshold voltage can be modulated by controlling the thickness T of the spacer 26.

[0021] As shown in FIG. 5, the spacer 26, the patterned photoresist 22a and the hard mask 20a are removed. It is noteworthy that the metal compound layer 18a is formed by the dry etching process 24. As shown in FIG. 5, under a sectional view, an acute angle A is formed between a sidewall of the metal compound layer 18a and a top surface of the P-type group III-V gate 16a. In details, the metal compound layer 18a has two opposed sidewalls. Two acute angles A are respectively formed between one of the sidewalls and the top surface of the P-type group III-V gate 16a and between another sidewall and the top surface of the P-type group III-V gate 16a. Each of the acute angles A is between 30 and 80 degrees. The range of the acute angles A is a feature specially formed by the fabricating process of the present invention. If the metal compound layer 18a is formed by a wet etching process, the angle between the sidewall of the metal compound layer 18a and the top surface of the P-type group III-V gate 16a will be a right angle or will be larger than 80 degrees.

[0022] As shown in FIG. 6, a source electrode 30, a drain electrode 32 and a gate electrode 34 are formed on the substrate 10. In details, the source electrode 30 and the drain electrode 32 are formed to contact the channel layer 12. Then, a protective layer 36 is formed conformally to cover the source electrode 30, the drain electrode 32, the active layer 14, the P-type group III-V gate 16a and the metal compound layer 18a. Later, the protective layer 36 is etched to form an opening therein. Subsequently, the gate electrode 34 is formed to cover the opening and contact the metal compound layer 18a. Now, a high electron mobility transistor 100 of present invention is completed.

[0023] FIG. 6 depicts a high electron mobility transistor fabricated by a fabricating method provided in the present invention. The high electron mobility transistor 100 includes a substrate 10, a channel layer 12, an active layer 14, a P-type group III-V gate 16a and a metal compound layer 18a disposed on the substrate 10. The channel layer 12, the active layer 14, the P-type group III-V gate 16a and the metal compound layer 18a are disposed from bottom to top. The metal compound layer 18a contacts the P-type group III-V gate 16a. The metal compound layer 18a has two sidewalls which are opposed to each other, two acute angles A are respectively formed between one of the sidewalls and a top surface of the P-type group III-V gate 16a and between another sidewall and the top surface of the P-type group III-V gate 16a. The aforesaid sidewalls face toward the metal compound layer 18a itself. The metal compound layer 18a only covers part of the P-type group III-V gate 16a. A source electrode 30, a drain electrode 32 and a gate electrode 34 are disposed on the active layer 14.

[0024] P-type group III-V gate 16a includes P-type gallium nitride. The metal compound layer 18a includes titanium nitride or tantalum nitride. The channel layer 12 includes gallium nitride, indium gallium nitride, aluminum gallium nitride, aluminum indium nitride, aluminum indium gallium nitride or aluminum nitride. The active layer 14 includes aluminum gallium nitride, aluminum indium nitride, aluminum indium gallium nitride or aluminum nitride. The high electron mobility transistor is a normally-off transistor. Two dimensional electron gas 38 generates at the interface between the active layer 14 and the channel layer 12.

[0025] The present invention takes by-products (spacer) which is formed during dry etching the metal compound material layer and the hard mask material layer as a mask to etch the P-type group III-V compound material layer so as to form the P-type group III-V gate. Traditionally, the P-type group III-V gate is formed by taking a hard mask as a mask to dry etch the P-type group III-V compound material layer and the metal compound material layer so as to form the P-type group III-V gate and the metal compound layer which are with the same width. Later, the P-type group III-V gate and the metal compound layer are moved to a wet etching chamber to perform a wet etching. During the wet etching, the width of the metal compound layer is decreased. Comparing to the traditional way, the method of the present invention does not need the wet etching. Furthermore, by using by-products as a mask, an extra mask is not needed. After etching the metal compound material layer, the P-type group III-V compound material layer is etched in the same chamber by adjusting several operational parameters. Therefore, the fabricating method of the present invention is simpler than the traditional method.

[0026] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.