Power semiconductor device

Abstract

Disclosed is a power semiconductor device comprising a semiconductor wafer having a first main side and second main side. The semiconductor wafer comprises parallel thyristor cells, which each comprises (a) a cathode electrode and gate electrode on the first main side; (b) a cathode layer comprising a cathode region of a first conductivity type, forming an ohmic contact with the cathode electrode; (c) a first base layer of a second conductivity type, wherein the cathode region forms a p-n junction between the first base layer and cathode region; (d) a second base layer of the first conductivity type forming a second p-n junction with the first base layer; (e) an anode layer of the second conductivity type separated from the first base layer by the second base layer. The gate electrodes of the plurality of thyristor cells form a gate design comprising multiple polygons each comprising at least four struts.

Claims

1. A power semiconductor device comprising a semiconductor wafer having a first main side and a second main side opposite to the first main side (1), the semiconductor wafer comprising a plurality of parallel thyristor cells, wherein each thyristor cell comprises in an order from the first main side to the second main side: (a) a cathode electrode and a gate electrode arranged on the first main side; (b) a cathode layer comprising a cathode region of a first conductivity type, forming an ohmic contact with the cathode electrode; (c) a first base layer of a second conductivity type different from the first conductivity type, wherein the cathode region is formed as a well in the first base layer and forms a first p-n junction between the first base layer and the cathode region; (d) a second base layer of the first conductivity type forming a second p-n junction with the first base layer; (e) an anode layer of the second conductivity type separated from the first base layer by the second base layer; wherein the gate electrode forms an ohmic contact with the first base layer, and an anode electrode is arranged on the second main side and forms an ohmic contact with the anode layer; wherein the gate electrodes of the plurality of thyristor cells form a gate design comprising multiple polygons each comprising at least four struts, wherein the cathode regions are of hexagonal shape, and the cathode layers comprise cathode short areas of the second conductivity type connecting the cathode electrodes with the first base layers, wherein the cathode short areas are of polygonal shape or circular shape or stripe shape and the cathode short areas are placed along a hexagonal gate-cathode boundary within the hexagonal cathode region.

2. The power semiconductor device according to claim 1, wherein the multiple polygons are connected via a central gate contact.

3. The power semiconductor device according to claim 1, wherein the multiple polygons are connected via a peripheral gate contact.

4. The power semiconductor device according to claim 1, wherein a lateral width of the struts is in a range of 0.1 mm to 1 mm, or in a range of 0.1 mm to 0.5 mm.

5. The power semiconductor device according to claim 2, wherein a lateral width of the struts of the polygons decreases with growing distance from the central gate contactor the peripheral gate contact.

6. The power semiconductor device according to claim 1, wherein the power semiconductor device is a high-power reverse blocking thyristor or a reverse conducting thyristor.

7. The power semiconductor device according to claim 1, comprising first cathode metal layers contacting the cathode regions and second cathode metal layers contacting the first cathode metal layers of all of the cathode regions of the plurality of thyristor cells.

8. The power semiconductor device according to claim 7, comprising gate-cathode insulations laterally between the gate electrodes and the first cathode metal layers on the first main side of the wafer.

9. The power semiconductor device according to claim 8, comprising gate insulations on the gate electrodes and on the gate-cathode insulations.

10. The power semiconductor device according to claim 7, wherein the first cathode metal layers form a substance-to-substance bond to the cathode regions and the second cathode metal layers form a removable connection to the first cathode metal layers which second cathode metal layers contact the first cathode metal layers of all thyristor cells as one single common disk.

11. The power semiconductor device according to claim 1, wherein the cathode regions comprise top sections vertically extending above a top surface of the first base layer and bottom sections within the wafer.

12. The power semiconductor device according to claim 11, wherein an area of the top section is smaller than an area of the bottom section.

13. The power semiconductor device according to claim 11 comprising gate-cathode insulations laterally between the gate electrodes and the top sections of the cathode regions and on top of the gate electrodes and cathode electrodes on top of the gate-cathode insulations and the top sections of the cathode regions contacting the top sections of the cathode regions.

14. The power semiconductor device according to claim 1, wherein the plurality of thyristor cells form a honeycombed gate design comprising multiple hexagons each comprising six struts.

15. The power semiconductor device according to claim 14, wherein the diameter of each of the hexagons is in a range of 1 mm to 20 mm or in a range of 2 mm to 10 mm.

16. A method for manufacturing the power semiconductor device according to claim 1 comprising the following steps: a step of providing the wafer having a first main side; a step of generating cathode regions within a cathode layer in the first base layer by diffusing a dopant pre-deposited at the first main side or implanting into the first main side; a step of generating cathode short areas in the cathode layer by diffusing a dopant pre-deposited at the first main side or implanting into the first main side; a step of forming ohmic contacts of the gate electrodes through a structured metal mask; a step of forming gate-cathode insulations through a structured mask layer, wherein this mask layer is etched on the cathode regions; a step of forming ohmic contacts of the cathode electrodes with the cathode regions.

17. The power semiconductor device according to claim 3, wherein a lateral width of the struts of the polygons decreases with growing distance from the central gate contact or the peripheral gate contact.

18. The power semiconductor device according to claim 2, comprising first cathode metal layers contacting the cathode regions and second cathode metal layers contacting the first cathode metal layers of all of the cathode regions of the plurality of thyristor cells.

19. The power semiconductor device according to claim 3, comprising first cathode metal layers contacting the cathode regions and second cathode metal layers contacting the first cathode metal layers of all of the cathode regions of the plurality of thyristor cells.

20. The power semiconductor device according to claim 4, comprising first cathode metal layers contacting the cathode regions and second cathode metal layers contacting the first cathode metal layers of all of the cathode regions of the plurality of thyristor cells.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The subject matter of embodiments will be explained in more detail in the following detailed description with reference to the attached drawings in which

(2) FIG. 1 shows an example of the basic structure of a power semiconductor device, exemplarily a thyristor;

(3) FIG. 2A, 2B disclose examples for a gate design of a power semiconductor device according to an embodiment;

(4) FIG. 3A, 3B, 3C show examples of shapes of cathode short areas;

(5) FIG. 3D shows an example of a cathode contact structure of a power semiconductor device according to an embodiment;

(6) FIG. 4 discloses mesa cathode segments of a power semiconductor device according to an embodiment;

(7) FIG. 5 shows a specific design of cathode regions and cathode short areas of a power semiconductor device according to an embodiment.

(8) The reference signs used in the Figures are summarized in the List of Reference Signs at the end of this specification. The described embodiments are meant as examples and shall not confine the invention. The invention is solely defined by the claims.

DETAILED DESCRIPTION OF EMBODIMENTS AND EXAMPLES

(9) Embodiments will now be explained in detail on the basis of several examples in association with appended drawings 1 to 5.

(10) FIG. 1 shows an example of a power semiconductor device 1, exemplarily a phase controlled thyristor with a four-layer structure (pnpn or npnp). The power semiconductor device 1 comprises a semiconductor wafer having a top surface on a first main side 2 and a bottom surface on a second main side 3 opposite to the first main side 2. The power semiconductor device 1 comprises a plurality of parallel thyristor cells, wherein each thyristor cell comprises in a sequential order from the first main side 2 to the second main side 3 a cathode electrode 9 and a gate electrode 8 arranged on the first main side 2, a cathode layer comprising a cathode region 4 of a first conductivity type and forming an ohmic contact with the cathode electrode 9, e.g. n.sup.+-type, a first base layer 5 of a second conductivity type, e.g. p-type, different from the first conductivity type, wherein the cathode region 4 is formed as a well in the first base layer 5 to form a first p-n-junction between the first base layer 5 and the cathode region 4, a second base layer 6 of the first conductivity type, e.g. n.sup.-type, forming a second pn-junction with the first base layer 5, and an anode layer 7 of the second conductivity type, e.g. p.sup.+-type, separated from the first base layer 5 by the second base layer 6, wherein the gate electrode 8 forms an ohmic contact with the first base layer 5 and an anode electrode 10 is arranged on the second main side 3 and forms an ohmic contact with the anode layer 7.

(11) To maximize the dI/dt and dV/dt capability and at the same time to lower the commutation turn-off time t.sub.q, the power semiconductor device 1 according to an embodiment requires a design of the gate electrodes 8 of the plurality of thyristor cells formed by multiple polygons each comprising at least four (4) struts as shown e.g. in FIGS. 2A and 2B. Due to the closed cell structure by multiple polygons, thyristor segments are created which are operating in parallel.

(12) In another embodiment, as shown e.g. in FIG. 2A, the multiple polygons of the gate electrode are connected via a central gate contact 11.

(13) In another embodiment, as shown e.g. in FIG. 2B, the gate contact 12 is moved to the periphery of the silicon wafer to turn-ON the thyristor starting from a longer gate-cathode boundary towards center to minimize the effect of stray inductance.

(14) In another embodiment, a lateral width of the struts is in a range of 0.1 mm to 1 mm, exemplarily in a range of 0.1 mm to 0.5 mm to maximize the number of thyristor segments in parallel. The term lateral in this context refers to an inplane direction when viewed in plan view onto the top surface of the first main side 2.

(15) In another embodiment, a lateral width of the struts decreases with growing distance from the central gate contacts 11 or peripheral gate contacts 12 to minimize the cathode area consumption (bringing a lower ON-state voltage VT) in the areas with decreasing amount of cathode polygons to be supplied by the gate current during turn-on.

(16) According to specific embodiments, the power semiconductor device according to an embodiment is a high-power reverse blocking thyristor or a reverse conducting thyristor.

(17) According to another embodiment, the cathode regions 4 are of hexagonal shape and the cathode layers comprise cathode short areas 13 of the second conductivity type connecting the cathode electrodes 9 with the first base layers 5 to improve the dV/dt behavior of the power semiconductor device by allowing a part of the electrons flowing directly to the emitter electrode via the cathode short areas without giving rise to an emission of charge carriers from the emitter zone.

(18) According to another embodiment, the cathode short areas 13 are of polygonal shape or circular shape or stripe shape and the cathode short areas 13 are placed along a hexagonal gate cathode boundary within the hexagonal cathode regions 4. Some embodiments of shapes of the cathode short areas 13 are shown as examples in FIGS. 3A-3C. In this respect, FIG. 3A discloses a cathode short area 13 of hexagonal shape, which is a specific type of polygonal shape comprising six struts.

(19) In another embodiment, as shown e.g. in FIG. 3C, the cathode short areas 13 are of circular shape and are placed along the hexagonal gate-cathode boundary within the hexagonal cathode region 4.

(20) In another embodiment, as shown e.g. in FIG. 3B, the cathode short areas 13 are of stripe shape and are placed along the hexagonal gate-cathode boundary within the hexagonal cathode region 4. Eventually, the cathode short areas of stripe shape may be placed perpendicularly to the gate-cathode boundary (not shown in the Figures).

(21) When the cathode short areas of polygonal shape, e.g. of hexagonal shape, are placed along the hexagonal gate-cathode boundary as shown e.g. in FIG. 3A, where the p.sup.+-type cathode short region is located in the hexagonal cathode region, the distance L.sub.NP from the gate-cathode boundary is a design parameter to achieve the required dV/dt rating. When viewed in plan view on the first main side 2, the width L.sub.P of the cathode short is limited by the resolution of available photolithography process (minimal feature size) and the efficiency of the cathode short itself. A reasonable range of diameter is 80 m to 150 m. As it is evident e.g. from FIG. 3D, the width of the cathode hexagon
L.sub.N=2L.sub.NP+2L.sub.P+x,

(22) where x may correspond to the inner diameter of the cathode short areas 13 and is in a range of a distance between the cathode short areas, e.g. 300 m to 900 m. This results e.g. in L.sub.N=500 m to 1300 m. To compensate corner effects of a polygonal structure of the cathode short areas, the cathode short areas also may be of circular shape or stripe shape as shown in e.g. in FIGS. 3C and 3B. One difference from prior art designs is that the cathode regions are so small that there is no need for a shorting pattern of spatially positioned cathode short areas like for example the triangular or trapezoidal one known from prior art. There is only a single line or row of cathode short areas in order to minimize the area of the cathode segment in order to gain the maximal length of the gate-cathode boundary providing the maximal dI/dt capability. To maximize the dI/dt capability, the present embodiment provides several measures to maximize the number of cathode segments as e.g. reducing the size of the polygons or reducing the width of the gate metal. In an extreme case of a very small cathode area 4 there may be only a single cathode short in the center of the cathode area.

(23) To improve the thermal performance of the device, the area between the gate electrode 8 and the cathode electrode 9 may be filled by polyimide or any other insulator which has a higher thermal conductivity than air.

(24) In another embodiment as shown e.g. in FIG. 3D, representing the thyristor with a flat cathode region (planar device), the cathode electrode 9 of the power semiconductor device according to an embodiment comprises first cathode metal layers 101 contacting the cathode regions 4 and second cathode metal layers 102 contacting the first cathode metal layers 101 of all of the cathode regions 4 of the plurality of thyristor cells.

(25) In another embodiment, the second cathode metal 102 is a disk comprising molybdenum and which is not fixed permanently to the power semiconductor device, but is mechanically pressed by e.g. of a pole piece of a package of the power semiconductor device.

(26) According to another embodiment, the power semiconductor device comprises gate-cathode insulations 14 laterally between the gate electrodes and the first cathode metal layers 101 on the first main side 2 of the wafer. The gate-cathode insulation 14 may be e.g. polyimide, oxide or any other insulator which has a higher thermal conductivity than air to improve the thermal performance of the device.

(27) In another embodiment, the power semiconductor device furthermore comprises gate insulations 15 on the gate electrodes 8 and on the gate-cathode insulations 14. This option is advantageous for the case of the gate electrode placed at the periphery. This option is advantageous for the case of the gate electrode placed at the periphery.

(28) According to another embodiment, the first cathode metal layers 101 form a substance-to-substance bond to the cathode regions 4 and the second cathode metal layers 102 form a removable connection to the first cathode metal layers 101 which second cathode metal layers (102) contact the first cathode metal layers 101 of all thyristor cells as one single common disk. The first cathode metal layers 101 may comprise aluminum and the second metal layers 102 may be formed by a molybdenum disk.

(29) FIG. 4 discloses another embodiment, exemplarily a power semiconductor device wherein cathode regions 4 comprise top sections vertically extending above a top surface of the first base layer on the first main side 2 and bottom sections within the wafer. By the interdigitation of the gate and cathode by means of mesa cathode segments as shown in FIG. 4, the length of the gate-cathode boundary may be further maximized to achieve a high dI/dt and dV/dt. To optimize the electrical performance of the device and to lower the production costs, the size and shape of cathode segments may be adapted to achieve the desired effects.

(30) According to another embodiment, the cathode region 4 is one of hexagonal shape, stripe shape or circular shape and an area of the top section is smaller than an area of the bottom section.

(31) According to another embodiment, the cathode electrode 9 may comprise molybdenum. As already mentioned above, the cathode electrode 9 at least may be partially formed as molybdenum disk which is not permanently fixed to the power semiconductor device but is e.g. mechanically pressed by a pole piece of the package of the power semiconductor device.

(32) According to another embodiment, the power semiconductor device comprises gate-cathode insulations 14 laterally between the gate electrodes 8 and the top sections of the cathode regions 4 and on top of the gate electrodes 8 and cathode electrodes 9 on top of the gate-cathode insulations 14 and the top sections of the cathode regions 4 contacting the top sections of the cathode regions 4. By the gate-cathode insulations 14 which are arranged laterally between the gate electrodes and the vertical extending cathode regions 4 and which are formed on top of the gate electrodes 8, a planar surface is formed as it is evident e.g. from FIG. 4, which therefore simplifies a subsequent packaging process and also avoids eventual reliability issues caused by small particles shorting the gate with cathode.

(33) According to another embodiment, the cathode electrode 9 may comprise aluminum.

(34) According to another embodiment and as disclosed e.g. in FIGS. 2A and 2B, the plurality of thyristor cells of the power semiconductor device according to an embodiment form a honeycomb gate design comprising multiple hexagons each comprising six struts.

(35) According to another embodiment, the diameter of each of the hexagons is in a range of 1 mm to 20 mm or in a range of 2 mm to 10 mm.

(36) It is also an object of embodiments to provide a method of manufacturing a Power semiconductor device according to embodiments. The method comprises a step of providing the wafer having a first main side 2, a step of generating cathode regions 4 within a cathode layer in the first base layer 5 by diffusing a dopant pre-deposited at the first main side 2 or implanting into the first main side 2, a step of generating cathode short areas 13 in the cathode layer by diffusing a dopant pre-deposited at the first main side or implanting into the first main side 2, a step of forming ohmic contacts of the gate electrodes 8 through a structured metal mask, a step of forming a gate-cathode insulations 14 through a structured mask layer, wherein this mask layer is etched on the cathode regions 4, a step of forming ohmic contacts of cathode electrodes 9 with the cathode regions 4.

LIST OF REFERENCE SIGNS

(37) 1 power semiconductor device 2 first main side 3 second main side 4 cathode region 5 first base layer 6 second base layer 7 anode layer 8 gate electrode 9 cathode electrode 10 anode electrode 11 central gate contact 12 peripheral gate contact 13 cathode short area 14 gate-cathode insulation 15 gate insulation 101 first cathode metal layer 102 second cathode metal layer