SEMICONDUCTOR CIRCUIT STRUCTURE AND METHOD FOR FORMING THE SAME

Abstract

A semiconductor circuit structure includes a semiconductor substrate with an original semiconductor surface, an active region within the semiconductor substrate, and a transistor formed based on the active region. The transistor includes a gate structure, a first spacer neighboring to a first sidewall of the gate structure, and a second spacer neighboring to a second sidewall of the gate structure. Wherein a thermal conductivity of the first spacer or the second spacer includes is higher than the thermal conductivity of silicon nitride (Si.sub.3N.sub.4).

Claims

1. A semiconductor circuit structure comprising: a semiconductor substrate with an original semiconductor surface; an active region within the semiconductor substrate; and a transistor formed within the active region, the transistor comprising: a gate structure; a first spacer neighboring to a first sidewall of the gate structure; and a second spacer neighboring to a second sidewall of the gate structure; wherein a thermal conductivity of the first spacer or the second spacer is higher than that of silicon nitride (Si.sub.3N.sub.4).

2. The semiconductor circuit structure according to claim 1, wherein the wherein the first spacer or the second spacer is made of a material selected from a group consisting of silicon carbide (SIC), hexagonal boron nitride (h-BN), aluminum nitride (AlN) and the arbitrary combinations thereof.

3. The semiconductor circuit structure according to claim 1, wherein the transistor further comprising: a channel region covered by the gate structure; a source structure coupled to a first terminal of the channel region; and a drain structure coupled to a second terminal of the channel region; wherein the first spacer is between the gate structure and the source structure, and the second spacer is between the gate structure and the drain structure.

4. The semiconductor circuit structure according to claim 3, wherein the source structure comprises a first lightly doped drain (LDD) region and a first heavily doped region, and the first spacer covers the first LDD region or the first heavily doped region of the source structure.

5. The semiconductor circuit structure according to claim 4, wherein the drain structure comprises a second LDD region and a second heavily doped region, and the second spacer covers the second LDD region or the second heavily doped region of the drain structure.

6. The semiconductor circuit structure according to claim 1, wherein the transistor is a fin field-effect transistor (FinFET), a gate-all-around (GAA) transistor, a recessed gate (RG) transistor or a complementary field-effect transistor (CFET).

7. The semiconductor circuit structure according to claim 1, further comprising a first isolation region next to the action region, wherein the first isolation region includes a first heat removing layer, and the material of the heat removing layer is different from silicon dioxide (SiO.sub.2).

8. The semiconductor circuit structure according to claim 7, wherein the first isolation region is a shallow trench isolation (STI) region surrounds the transistor, and the first isolation region further includes a SiO.sub.2 layer under the first heat removing layer.

9. The semiconductor circuit structure according to claim 7, wherein the first isolation region further includes a second heat removing layer above the first heat removing layer, and the material of the second heat removing layer is different from that of the first heat removing layer.

10. The semiconductor circuit structure according to claim 7, wherein the first heat removing layer is positioned under the original semiconductor surface.

11. The semiconductor circuit structure according to claim 7, wherein the first spacer, the second spacer and the first heat removing layer are within a front end of line (FEOL) region of the semiconductor circuit structure.

12. The semiconductor circuit structure according to claim 7, wherein a top surface of the first isolation region is higher than the original semiconductor surface of the semiconductor substrate.

13. A semiconductor circuit structure comprising: a semiconductor substrate with an original semiconductor surface; an active region within the semiconductor substrate; and a transistor within the active region, the transistor comprising: a gate structure; a channel region covered by the gate structure; a source region electrically connected to one end of the channel region; a drain region electrically connected to another end of the channel region; a first heat removing spacer next to the gate structure and covering the source region; and a second heat removing spacer next to the gate structure and covering the drain region.

14. The semiconductor circuit structure according to claim 13, wherein a thermal conductivity of the first heat removing spacer or the second heat removing spacer is higher than 2.0 W/m.K.

15. The semiconductor circuit structure according to claim 13, further comprising a shallow trench isolation (STI) region surrounds the transistor, wherein the STI region comprises a heat removing layer, and a thermal conductivity of the heat removing layer is higher than that of silicon dioxide (SiO.sub.2).

16. The semiconductor circuit structure according to claim 15, wherein a top surface of the heat removing layer is close to the source region or the drain region.

17. The semiconductor circuit structure according to claim 13, wherein the first heat removing spacer or the second heat removing spacer is made of a material selected from a group consisting of SiC, h-BN, AlN and the arbitrary combinations thereof.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other aspects of the disclosure will become better understood with regard to the following detailed description of the preferred but non-limiting embodiment(s). The following description is made with reference to the accompanying drawings:

[0023] FIG. 1 is a top view illustrating the structure of a DRAM circuit (the semiconductor circuit structure) according to one embodiment of the present disclosure;

[0024] FIG. 2A(1) is a top view illustrating the structure after the at least one trench is formed to define a fin island serving as an active area in the semiconductor substrate; FIGS. 2A(2) and 2A(3) are cross-sectional views respectively taken along the cutting-lines C2A1 and C2A2 as depicted in FIG. 2A(1);

[0025] FIG. 2B(1) is a top view illustrating the structure after the opening is formed in the patterned pad layer over the at least one active area; FIGS. 2B(2) and 2B(3) are cross-sectional views respectively taken along the cutting-lines C2B1 and C2B2 as depicted in FIG. 2B(1);

[0026] FIG. 2C(1) is a top view illustrating the structure after the gate trench is formed in the patterned pad layer; FIGS. 2C(2) and 2C(3) are i cross-sectional views respectively taken along the cutting-lines C2C1 and C2C2 as depicted in FIG. 2C(1);

[0027] FIG. 2D(1) is a top view illustrating the structure after the gate structure is formed; FIGS. 2D(2) and 2D(3) are cross-sectional views taken along the cutting-lines C2D1 and C2D2 as depicted in FIG. 2D(1);

[0028] FIG. 2E(1) is a top view illustrating the structure after the at least one spacer is formed; FIGS. 2E(2) and 2E(3) are cross-sectional views respectively taken along the cutting-lines C2E1 and C2E2 as depicted in FIG. 2E(1);

[0029] FIG. 2F(1) is a top view illustrating the structure after the source recess and the drain recess are formed; FIGS. 2F(2) and FIG. 2F(3) are cross-sectional views respectively taken along the cutting-lines C2F1 and C2F2 as depicted in FIG. 2F(1);

[0030] FIG. 2G(1) is a top view illustrating the structure after the source structure and the drain structure are formed; FIGS. 2G(2) and 2G(3) are cross-sectional views respectively taken alone the cutting-lines C2G1 and C2G2 as depicted in FIG. 2G(1);

[0031] FIG. 2H is a partial perspective view illustrating the a semiconductor circuit structure including a FinFET according to one embodiment of the present disclosure;

[0032] FIG.2I is a partial perspective view illustrating a semiconductor circuit structure including a GAA transistor according to another embodiment of the present disclosure;

[0033] FIG. 2J is a partial perspective view illustrating a semiconductor circuit structure including a CFET structure according to yet another embodiment of the present disclosure;

[0034] FIG. 3A is a perspective view illustrating a partial structure of semiconductor circuit structure according to another embodiment of the present disclosure;

[0035] FIG. 3BFIG. 3E are cross-sectional views taken along the cutting-line C31, C32, C33, and C34 as depicted in FIG. 3A, respectively; FIG. 4A is a perspective view illustrating a partial structure of

[0036] semiconductor circuit structure according to another embodiment of the present disclosure;

[0037] FIG. 4BFIG. 4E are cross-sectional views taken along the cutting-line C41, C42, C43, and C44 as depicted in FIG. 4A, respectively;

DETAILED DESCRIPTION OF THE DISCLOSURE

[0038] The present disclosure provides a semiconductor circuit structure 100 for effectively reducing the junction temperatures of transistors included in the semiconductor circuit structure 100. The above and other aspects of the disclosure will become better understood by the following detailed description of the preferred but non-limiting embodiment(s). The following description is made with reference to the accompanying drawings:

[0039] Several embodiments of the present disclosure are disclosed below with reference to accompanying drawings. However, the structure and contents disclosed in the embodiments are for exemplary and explanatory purposes only, and the scope of protection of the present disclosure is not limited to the embodiments. It should be noted that the present disclosure does not illustrate all possible embodiments, and anyone skilled in the technology field of the disclosure will be able to make suitable modifications or changes based on the specification disclosed below to meet actual needs without breaching the spirit of the disclosure. The present disclosure is applicable to other implementations not disclosed in the specification.

[0040] The present embodiment discloses a semiconductor circuit structure 100 with innovation structure to improve its thermal dissipation capability. In the embodiments of the present disclosure, semiconductor circuit structure 100 includes a plurality of transistors disposed different areas, and the innovation structure as described below can be applied for effectively reducing the junction temperatures thereof.

[0041] For example, the semiconductor circuit structure 100 may be a dynamic random access memory (DRAM) circuit. FIG. 1 is a top view illustrating the structure of the DRAM circuit (the semiconductor circuit structure 100) according to one embodiment of the present disclosure. The DRAM circuit includes a plurality memory cells 100C and a peripheral circuit which may include a logic area 100L having a logic circuit and a peripheral area 100P having a peripheral I/O circuit. Wherein, each of the memory cell 100C, the logic circuit and the peripheral I/O circuit includes at least one transistor T11, T12 and T13 within active regions or active areas, respectively. In some embodiments, each of the transistors T11, T12 and T13 can be a FinFET, a GAA transistor, a recess gate (RG) transistor, or a complementary field-effect transistor (CFET); and the innovation structure as described below can be applied both to the transistors T11, T12 and T13 for effectively reducing the junction temperatures thereof.

Embodiment 1

[0042] Detailed steps of the manufacturing method of the semiconductor circuit structure 100 as follows: [0043] Step S11: A semiconductor substrate 101 with an original surface 101S is provided; [0044] Step S12: At least one active area 101A is defined in the semiconductor substrate 101; wherein the Step S12 for defining the active area 101A includes Sub-steps S121-S122: [0045] Sub-step S121: An etching process using a patterned pad layer 110 (including a pad oxide layer 110A and a pad nitride layer 110B stacked in sequence) as an etching mask is performed to form at least one trench 101T extending into the semiconductor substrate 101 from an original surface 101S of the semiconductor substrate 101 along a direction D1 and defined a fin island 101L serving as the at least one active area [0046] Sub-step S122: A shallow trench isolation (STI) region filled with a STI structure 102 is formed in the at least one trench 101T to surround the fin island 101L; [0047] Step S13: A gate structure 103 is formed within the at least one active area 101A, and the Step S13 for forming the gate structure 103 includes Sub-steps S131-S134: [0048] Sub-step S131: An opening 110O is formed in the patterned pad layer 110 over the at least one active area 101A; [0049] Sub-step S132: At least one dummy spacer (such as, a first dummy spacer 114A and a second dummy spacer 114B) is formed on the sidewall of the opening 110O; [0050] Sub-step S133: A gate trench 110T connecting with the opening 110O is formed in the patterned pad layer 110 to exposing a portion of the at least one active area 101A; and [0051] Sub-step S134: A gate dielectric layer 103D, a barrier layer 103B, a work function layer 103F are formed in sequence to cover the bottom and sidewalls of the gate trench 110T; and a gate electrode 103E is formed to full-fill the gate trench 110T; [0052] Step S14: At least one spacer (such as, a first spacer 104A and a second spacer 104B) is formed neighboring to at least on sidewall of the gate structure 103, wherein the least one spacer (the first spacer 104A or the second spacer 104B) has a thermal conductivity higher than the thermal conductivity of silicon nitride (Si.sub.3N.sub.4), SiOCN or SiO.sub.2; and the Step S14 for forming the at least one spacer includes Sub-steps S141-S142: [0053] Sub-step S141: The at least one dummy spacer (e.g., the first dummy spacer 114A and the second dummy spacer 114B) is removed; and [0054] Sub-step S142: A material having a thermal conductivity higher than the thermal conductivity of silicon nitride (Si.sub.3N.sub.4), SiOCN or SiO.sub.2 is formed to take the place of the removed dummy spacer (e.g., the first dummy spacer 114A and the second dummy spacer 114B); [0055] Step S15: A source structure 105 and a drain structure 106 are formed in the at least one active area 101A and neighboring to the gate structure 103; wherein the Step S15 for forming the source structure 105 and the drain structure 106 includes Sub-steps S151-S15: [0056] Sub-step S151: A source recess 117A and a drain recess 117B extending into the semiconductor substrate 101 from the original surface 101S of the semiconductor substrate 101 are formed in the active area 101A; [0057] Sub-step S152: A first lightly doped drain (LDD) region 105A and a second LDD region 106A are formed from the portions of the semiconductor substrate 101 exposed by the source recess 117A and the drain recess 117B; and [0058] Sub-step S153: A first heavily doped region 105B and a second heavily doped region 106B respectively based on the first LDD region 105A and the second LDD region 106A are formed in the source recess 117A and the drain recess 117B.

[0059] Referring to Step S11: A semiconductor substrate 101 having an original surface 101S is provided. In some embodiments of the present disclosure, the semiconductor substrate 101 may be a silicon-containing substrate, such as a silicon (Si) wafer or a silicon-on-insulator (SOI) substrate. In some other embodiments of the present disclosure, the semiconductor substrate 101 may be made of other types of semiconductor materials, such as germanium (Ge), or compound semiconductor materials, such as gallium arsenide (GaAs), SiC, or GaN, etc. In the present embodiment, the semiconductor substrate 101 may be a silicon wafer.

[0060] Referring to Step S12: At least one active area 101A is defined in the semiconductor substrate 101; wherein the Step S12 for defining the active area 101A includes Sub-steps S121-S122:

[0061] Referring to Sub-step S121: A pad layer 110 including a pad oxide layer 110A and a pad nitride layer 110B is formed on the original surface 101S of the semiconductor substrate 101. The pad layer 110 is then patterned to remove a portion of the pad layer 110. Next, an etching process using the remained portion of the pad layer 110 as an etching mask is performed to form at least one trench 101T extending into the semiconductor substrate 101 from an original surface 101S of the semiconductor substrate 101 along a direction D1 and defined the at least one active area 101A. In one embodiment, the one active area 101A includes a fin island 101L for a FinFET transistor.

[0062] FIG. 2A(1) is a top view illustrating the structure after the at least one trench 101T is formed to define a fin island 101L serving as an active area 101A in the semiconductor substrate 101; FIG. 2A(2) is a cross-sectional view take along the cutting-line C2A1 as depicted in FIG. 2A(1); FIG. 2A(3) is a cross-sectional view take along the cutting-line C2A2 as depicted in FIG. 2A(1).

[0063] Referring to Sub-step S122: A STI region filled with the STI structure 102 is formed in the at least one trench 101T to surround the fin island 101L. The forming of the STI region filled with the STI structure 102 includes performing a deposition process to deposit dielectric material filling the at least one trench 101T; and then performing an etch back process or a planarization process to remove the portion of the dielectric material over the patterned pad layer 110 (i.e., the patterned pad nitride layer 110B), so as to make the STI structure 102 having a top surface 102S higher than the original surface 101S of the semiconductor substrate 101, and the top surface 102S of the STI structure 102 could be leveled up to the top of the patterned pad layer 110. In some embodiment of the present disclosure, the dielectric material used for forming the STI structure 102 may be silicon oxide (such as, SiO.sub.2), Si.sub.3N.sub.4, or the combinations thereof or other suitable dielectric material.

[0064] In some embodiments of the present disclosure, prior to forming the STI structure 102, a silicon oxide thin layer 112 is formed on the bottom and the sidewalls of the at least one trench 101T (covering on the sidewalls of the fin island 101L) by a thermal oxidation; and a silicon nitride film 113 is then formed to cover the silicon oxide thin layer 112 (as shown in FIG. 2B(2)).

[0065] Referring to Step S13: A gate structure 103 is formed on the at least one active area 101A. The forming of the gate structure 103 includes Sub-steps S131-S134:

[0066] Referring to Sub-step S131: An opening 110O is formed in the patterned pad layer 110 over the at least one active area 101A. In some embodiment of the present disclosure, the opening 110O is formed by an etching process using a patterned photoresist layer 111 and a patterned amorphous silicon-carbon (a-SiC) layer 115 as an etching mask to remove a portion of the patterned pad nitride layer 110B disposed on the active area 101A and expose a portion of the patterned pad oxide layer 110A (as shown in FIG. 2B(2)).

[0067] FIG. 2B(1) is a top view illustrating the structure after the opening 110O is formed in the patterned pad layer 110 over the at least one active area 101A; FIG. 2B(2) is a cross-sectional view take along the cutting-line C2B1 as depicted in FIG. 2B(1); FIG. 2B(3) is a cross-sectional view take along the cutting-line C2B2 as depicted in FIG. 2B(1).

[0068] Referring to Sub-step S132: At least one dummy spacer (such as, a first dummy spacer 114A and a second dummy spacer 114B) is formed on the sidewall of the opening 110O. In some embodiments of the present disclosure, the forming of the at least one dummy spacer (e.g., the first dummy spacer 114A and the second dummy spacer 114B) includes steps as follows: The STI structure 102 not covered by the a-SiC layer 115 is etched down (such as etched to the top of the patterned pad oxide layer 110A). Then, a deposition process is performed to formed silicon nitride cover the sidewalls of the opening 110O, and an etching back process is then performed to remove the portion of the deposited silicon nitride covering the patterned a-C layer 115 and the bottom of the opening 110O to expose a portion of the pad oxide layer 110A.

[0069] Referring to Sub-step S133: A gate trench 110T connecting with the opening 110O is formed in the patterned pad layer 110 to expose a portion of the at least one active area 101A. In the present embodiment, the gate trench 110T is formed by an etching process, using the patterned a-SiC layer 115 and the dummy spacer (e.g., the first dummy spacer 114A and the second dummy spacer 114B) as an etching mask, and removing a portion of the patterned pad oxide layer 110A, so as to expose a portion of the at least one active area 101A.

[0070] FIG. 2C(1) is a top view illustrating the structure after the gate trench 110T is formed in the patterned pad layer 110; FIG. 2C(2) is a cross-sectional view take along the cutting-line C2C1 as depicted in FIG. 2C(1); FIG. 2C(3) is a cross-sectional view take along the cutting-line C2C2 as depicted in FIG. 2C(1). Referring to Sub-step S134: A gate dielectric layer 103D, a barrier layer 103B, a work function layer 103F are formed in sequence to cover the bottom and sidewalls of the gate trench 110T; and a gate electrode 103E is formed to full-fill the gate trench 110T. Before forming the gate dielectric layer 103D, the STI structure 102 not covered by the a-SiC layer 115 is further etched down (such as etched below the bottom of the fin island 101L). Then, the silicon oxide thin layer 112 and the silicon nitride film 113 are removed to reveal the fin island 101L. Thereafter, a plurality of deposition/etching back processes are performed to respectively form the gate dielectric layer 103D, the barrier layer 103B, the work function layer 103F and the gate electrode 103E, and the combination thereof form the gate structure 103. In the present embodiment the gate electrode 103E includes metal, and the work function layer 103F includes a multi-layer structure.

[0071] FIG. 2D(1) is a top view illustrating the structure after the gate structure 103 is formed; FIG. 2D(2) is a cross-sectional view take along the cutting-line C2D1 as depicted in FIG. 2D(1); FIG. 2D(3) is a cross-sectional view take along the cutting-line C2D2 as depicted in FIG. 2D(1).

[0072] Referring to Step S14: At least one spacer (e.g., a first spacer 104A and a second spacer 104B) is formed neighboring to at least on sidewall of the gate structure 103, wherein the least one spacer (the first spacer 104A or the second spacer 104B) has a thermal conductivity higher than the thermal conductivity of Si.sub.3N.sub.4, SiOCN or SiO.sub.2; and the Step S14 for forming the at least one spacer includes Sub-steps S141-S142:

[0073] Referring to Sub-step S141: The at least one dummy spacer (e.g., the first dummy spacer 114A and the second dummy spacer 114B) is removed.

[0074] In some embodiments of the present disclosure, an etching process using the patterned a-SiC layer 115 and the gate structure 103 (including the gate dielectric layer 103D, the barrier layer 103B, the work function layer 103F and the gate electrode 103E) as an etching mask to remove the at least one dummy spacer (e.g., the first dummy spacer 114A and the second dummy spacer 114B), meanwhile the portion of the pad oxide layer 110A beneath the at least one dummy spacer (e.g., the first dummy spacer 114A and the second dummy spacer 114B) can be also removed. Then, the STI structure 102 originally below the dummy spacer 114A and 114B is etched down to the bottom of the fin island 101L, such that at least one spacer recess 116 next to the aforesaid gate structure is formed to expose a portion of the fin island 101L within the active area 101A.

[0075] Referring to Sub-step S142: A material having a thermal conductivity higher than the thermal conductivity of Si.sub.3N.sub.4, SiOCN or SiO.sub.2 is formed to take the place of the removed dummy spacer (e.g., the first dummy spacer 114A and the second dummy spacer 114B). For example, silicon carbide (SiC with thermal conductivity of 20 W/m.K), hexagonal boron nitride (h-BN) with thermal conductivity of 444 W/m.K), aluminum nitride (AlN), or other dielectric material having a thermal conductivity higher than the thermal conductivity of Si.sub.3N.sub.4and/or SiOCN could be deposited to full-fill the at least one spacer recess 116, so as to form the least one spacer (such as, a first spacer 104A and a second spacer 104B).

[0076] FIG. 2E(1) is a top view illustrating the structure after the at least one spacer (e.g., the first spacer 104A and the second spacer 104B, or called heat removing spacer) is formed; FIG. 2E(2) is a cross-sectional view take along the cutting-line C2E1 as depicted in FIG. 2E(1); FIG. 2E(3) is a cross-sectional view take along the cutting-line C2E2 as depicted in FIG. 2E(1).

[0077] Referring to Step S15: A source structure 105 and a drain structure 106 are formed in the at least one active area 101A and neighboring to the gate structure 103; wherein the Step S15 for forming the source structure 105 and the drain structure 106 includes Sub-steps S151-S15:

[0078] Referring to Sub-step S151: A source recess 117A and a drain recess 117B extending into the semiconductor substrate 101 from the original surface 101S of the semiconductor substrate 101 are formed in the active area 101A. In some embodiments of the present disclosure, the forming of the source recess 117A and the drain recess 117B includes steps as follows: The patterned a-SiC layer 115 is removed to reveal the patterned pad layer 110, then an etching process using the gate structure 103 and the heat removing spacer (such as, a first spacer 104A and a second spacer 104B) as an etching mask to remove the revealed pad layer 110 and a portion of the semiconductor substrate 101 (the fin island 101L) of the active area 101A, so as to form a source recess 117A and a drain recess 117B extending into the semiconductor substrate 101 from the original surface 101S of the semiconductor substrate 101 along the direction D1, and to expose sidewalls and/or bottom of the fin island 101L.

[0079] In some embodiments of the present disclosure, the etching process for forming the source recess 117A and the drain recess 117B may further remove portions of the STI structure 102 not covered by the gate structure 103 and the heat removing spacer, the silicon oxide thin layer 112 and the silicon nitride film 113. In other embodiment, the STI structure 102 not covered by the gate structure 103 and the heat removing spacer is not etched down such that the top of the STI structure 102 is higher than the top of the original surface 101S of the silicon substrate 101.

[0080] FIG. 2F(1) is a top view illustrating the structure after the source recess 117A and the drain recess 117B are formed; FIG. 2F(2) is a cross-sectional view take along the cutting-line C2F1 as depicted in FIG. 2F(1); FIG. 2F(3) is a cross-sectional view take along the cutting-line C2F2 as depicted in FIG. 2F(1).

[0081] Referring to Sub-step S152: A first lightly doped drain (LDD) region 105A and a second LDD region 106A are formed in the portions of the semiconductor substrate 101 exposed from the source recess 117A and the drain recess 117B. In some embodiments of the present disclosure, at least one ion implantation process or selectively epitaxial growth (SEG) process is performed to form the first LDD region 105A and the second LDD region 106A. In one embodiment, the first LDD region 105A and the second LDD region 106A are formed under the heat removing spacer (e.g., respectively beneath the first spacer 104A and a second spacer 104B), and the edge of the LDD region (the edge of the first LDD region 105A or the edge of the second LDD region 106A) could be aligned with the sidewall of the gate structure 103.

[0082] Referring to Sub-step S153: A first heavily doped region 105B and a second heavily doped region 106B respectively based on the first LDD region 105A and the second LDD region 106A are formed in the source recess 117A and the drain recess 117B. In some embodiments of the present disclosure, a selective epitaxy growth (SEG) method or an atomic layer deposition (ALD) method is applied to form the first heavily doped region 105B and the second heavily doped region 106B respectively based on the first LDD region 105A and the second LDD region 106A exposed from the source recess 117A and the drain recess 117B. The combination of the first LDD region 105A and the first heavily doped region 105B form the source structure 105; and the combination of the second LDD region 106A and the second heavily doped region 106B form the drain structure 106. The gate structure 102, the source structure 105 and the drain structure 106 together form the transistor T11 (T12 or T13).

[0083] FIG. 2G(1) is a top view illustrating the structure after the source structure 105 and the drain structure 106 are formed; FIG. 2G(2) is a cross-sectional view taken alone the cutting-line C2G1 as depicted in FIG. 2G(1); FIG. 2G(3) is a cross-sectional view taken alone the cutting-line C2G2 as depicted in FIG. 2G(1).

[0084] After a series steps of down-stream process are performed to form, such as a ILDs 119 full-filling the source recess 117A and the drain recess 117B and metal interconnections 120 (including metal layers MO and/or M1) connecting to the transistor T11 (T12 or T13), thereby the forming of the semiconductor circuit structure 100 as shown FIG. 2H can be implemented. In the present embodiment, the transistor T11 of the semiconductor circuit structure 100 can be a FinFET. Since the heat removing spacer (e.g., the first spacer 104A and the second spacer 104B) is configured very close to the hot spot H1 (as shown in FIG. 2H) in the interface between the channel region 118 and the first LDD region 105A (or the interface between the channel region 118 and the second LDD region 106A), and has a thermal conductivity higher than that of Si.sub.3N.sub.4 or SiOCN applied by the conventional gate spacers, thus the heat removing spacer (e.g., the first spacer 104A and the second spacer 104B) can serves as an effective knob for cooling the transistor T11 (T12 or T13). In the present embodiment, the heat removing spacer made of SiC with a thermal conductivity of 20 W/m.K can cool down the transistor T11 (T12 or T13) around 24 C.30 C., in comparison with a conventional transistor using a Si.sub.3N.sub.4 spacer (having a thermal conductivity of 2 W/m.K).

[0085] Of course, the heat removing spacer with high thermal conductivity will reduce junction temperature of other types of transistor (such as a recess gate (RG) transistor, a CFET or a GAA transistor) and improve its performance. For example, FIG. 2I is a partial perspective view illustrating a semiconductor circuit structure 100 including a GAA transistor T2 according to another embodiment of the present disclosure. The structure of the semiconductor circuit structure 100 as depicted in FIG. 2I is similar to that of the semiconductor circuit structure 100 as depicted in FIG. 2H except that the GAA transistor T2 has a plurality of channel regions 118G totally surrounded by the gate structure (including gate dielectric layer, the barrier layer, the work function layer (not shown) and the gate electrode 103GE).

[0086] In the present embodiment, the first spacer 104A and the second spacer 104B are also very close to the hot spot H2 in the interface between the narrow sheet/channel region 118G and the source structure 105 (or the interface between the sheet/channel region 118G and the drain structure 106), thus the first spacer 104A and the second spacer 104B can serves as an effective knob for cooling the GAA transistor T2.

[0087] FIG. 2J is a partial perspective view illustrating a semiconductor circuit structure 100 including a CFET structure according to yet another embodiment of the present disclosure. The structure of the semiconductor circuit structure 100 as depicted in FIG. 2J is similar to that of the semiconductor circuit structure 100 as depicted in FIG. 2H except that the CFET structure of the semiconductor circuit structure 100 includes an N-type GAA transistor T3 (with a ore more N-type channel 118N) and a P-type GAA transistor T4 (with a or more P-type channel 118P).

[0088] In the present embodiment, the first spacer 104A and the second spacer 104B are also very close to the hot spots H3 and H4 respectively in the interface between the channel region 118N and the source structure 105N (or the interface between the channel region 118N and the drain structure 106N) and in the interface between the channel region 118P and the source structure 105P (or the interface between the channel region 118P and the drain structure 106P), thus the first spacer 104A and the second spacer 104B can serves as an effective knob for cooling the CFET transistor.

[0089] In another embodiment of the present invention, all or portion of the STI structure 102 in the STI region may be replaced by an isolation region 332 which includes a heat removing layer 332A, and the material of the heat removing layer 332A is different from silicon dioxide (SiO.sub.2). Thus, there is heat removing layer within the STI region. For example, FIG. 3A is a perspective view illustrating a partial structure of semiconductor circuit structure 300 according to another embodiment of the present disclosure. FIG. 3B is a cross-sectional view taken along the cutting-line C31 as depicted in FIG. 3A; FIG. 3C is a cross-sectional view taken along the cutting-line C32 as depicted in FIG. 3A; FIG. 3D is a cross-sectional view taken along the cutting-line C33 as depicted in FIG. 3A; and FIG. 3E is a cross-sectional view taken along the cutting-line C34 as depicted in FIG. 3A.

[0090] In the present embodiment, the semiconductor circuit structure 300 includes a RG transistor T3R embedded in the active area 301A of the semiconductor substrate 301, and the bottom of the gate of the RG transistor T3R is beneath the original surface 301S of the semiconductor substrate 301. Wherein the active area 301A is surrounded by the STI region 332 extending along a first direction D3. Similar to the transistor T11 of the semiconductor circuit structure 100, the RG transistor T3R of the semiconductor circuit structure 300 includes a gate structure 303 (including a gate dielectric layer 303D and a gate electrode 303E) formed in the active area 301A of the semiconductor substrate 301, at least one heat removing spacer 304 neighboring to a sidewall of the gate structure 303 or sidewall of the source/drain regions 305/306, a channel region 318 under the gate structure 303, and the source/drain regions 305/306 connected to the channel region 318. Wherein the heat removing spacer 304 made of a material with a thermal conductivity higher than the thermal conductivity of Si.sub.3N.sub.4.

[0091] Furthermore, the STI region 332 includes a heat removing layer 332A mad of a material having a thermal conductivity higher than a thermal conductivity of silicon oxide and electrically isolated both from the semiconductor substrate 301 and a word line 330 connected to the gate structure 303. In some embodiments of the present disclosure, the STI region 332 include a heat removing layer 332A made by a material different from silicon dioxide (SiO.sub.2), a dielectric lying layer 332B used to electrically isolated the heat removing layer 332A from the semiconductor substrate 301, and a dielectric isolation layer 332C used to electrically isolated the heat removing layer 332A from the word line 330 (or covering the top of the heat removing layer 332A).

[0092] In the present embodiment, the heat removing layer 332A is made of poly-silicon (or large-grain silicon) used to take the place of a portion of the STI region 332. In other words, the heat removing layer 332A is positioned in a front end of line (FEOL) region of the semiconductor circuit structure 300, and extends along the direction D3 under the original surface 301S of the semiconductor substrate 301. The dielectric lying layer 332B could be made of SiO.sub.2; and the dielectric isolation layer 332C could be made of SiO.sub.2. In order to electrically isolate the heat removing layer 332A from the semiconductor substrate 301, the dielectric lying layer 332B is neighboring to the sidewalls and the bottom of the heat removing layer 332A. The top of the heat removing layer 332A could be close to the top of the source/drain regions 305/306.

[0093] By using the heat removing layer 332A to take the place of the large portions of the conventional SiO.sub.2 within the STI region 332 can further cool the transistor T3R and improve the heat dissipation of the semiconductor circuit structure 300. In some embodiments of the present disclosure, merely applying the heat removing layer 332A made of undoped polysilicon (or large-grain silicon) to take portions of the SiO.sub.2 (without applying the heat removing spacer 304) can cool the transistor T3R down by dropping 24 C.59 C., in comparison with the conventional transistor without applying the heat removing layer 332A and the heat removing spacer 304. For example, merely applying the heat the heat removing layer 332A made of polysilicon to take portions of the SiO.sub.2 STI region 332 can cool the transistor T3R from 122.2 C. to 93.6 C. In addition, while the heat removing spacer 304 and the heat removing layer 332A are applied together, the temperature of the transistor T3R can be further reduced about 29 C.

[0094] FIG. 4A is a perspective view illustrating a partial structure of semiconductor circuit structure 400 according to another embodiment of the present disclosure. FIG. 4B is a cross-sectional view taken along the cutting-line C31 as depicted in FIG. 4A; FIG. 4C is a cross-sectional view taken along the cutting-line C42 as depicted in FIG. 4A; FIG. 4D is a cross-sectional view taken along the cutting-line C43 as depicted in FIG. 4A; and FIG. 4E is a cross-sectional view taken along the cutting-line C44 as depicted in FIG. 4A. The structure of the semiconductor circuit structure 400 is similar to that of the semiconductor circuit structure 300 as depicted in FIGS. 3A-3E, except that the isolation region 432 of the transistor T4R further includes a high thermal dissipation region 432D under the heat removing layer 432A.

[0095] In some embodiments of the present disclosure, the high thermal dissipation region 432D is formed by using a material with a thermal conductivity higher than the thermal conductivity of silicon to take the place of another portion of the STI region 432 (a portion of the dielectric lying layer 432B). For example, in the present embodiment, the high thermal dissipation region 432D is made of metal (such as tungsten (W), TiN or the combination thereof) and could be electrically isolated from the heat removing layer 432A by another dielectric isolation layer 432C. In some embodiments of the present disclosure, the material for forming the dielectric isolation layer 432C and the high thermal dissipation region 432D may be the same.

[0096] By using the combination of the heat removing layer 432A and the high thermal dissipation region 432D can further cool down the transistor T4R (such as further reducing about 3.8 C., as compared with merely the heat removing layer 432A in the transistor T3R) and improve the heat dissipation of the semiconductor circuit structure 400.

[0097] Moreover, since the process and material for forming the heat removing spacer 304, the heat removing layer 432A and the high thermal dissipation region 432D can be provided from and integrated in the standard processing flow of the semiconductor circuit structure, thus the thermal dissipation capability of the semiconductor circuit structure can be effectively improve without adding expensive cost.

[0098] While the disclosure has been described by way of example and in terms of the exemplary embodiment(s), it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures. Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.