TRENCH-GATE SIC MOSFET DEVICE AND MANUFACTURING METHOD THEREFOR

Abstract

The present invention relates to a trench-gate SiC MOSFET device and a manufacturing method therefor. The trench-gate SiC MOSFET device of the present invention comprises: a gate oxide film covering a gate trench formed in a SiC substrate (e.g., an n-type 4H-SiC substrate); a doped well (e.g., BPW) formed in a bottom region of the gate trench; a gate electrode formed in the gate trench covered by the gate oxide film; an interlayer insulating film formed on the gate electrode; a source electrode covering the top surface of a doping layer for a source area formed on the entire surface of an epitaxial layer of the substrate and the top surface of the interlayer insulating film; and a drain electrode formed on the rear surface of the substrate.

Claims

1. A trench-gate SiC MOSFET device, comprising: a gate oxide film covering a gate trench formed in a SiC substrate; a doped well formed in a region of the gate trench; a gate electrode formed within the gate trench covered with the gate oxide film; an interlayer dielectric formed on the gate electrode; a source electrode covering an upper surface of a doping layer for a source region formed in a front surface of an epitaxial layer of the substrate and an upper surface of the interlayer dielectric; and a drain electrode formed on a back surface of the substrate.

2. The trench-gate SiC MOSFET device of claim 1, wherein the substrate with the trench structure is annealed in a H.sub.2 atmosphere before the formation of the gate electrode.

3. The trench-gate SiC MOSFET device of claim 1, wherein, before the formation of the gate electrode, a carbon capping layer is formed on the substrate with the trench structure, followed by annealing in an Ar atmosphere and removal of the carbon capping layer, and then the substrate with the trench structure is annealed in a H.sub.2 atmosphere.

4. The trench-gate SiC MOSFET device of claim 1, wherein, before the formation of the gate electrode, a sacrificial oxidation process (SOP) is performed in which dry oxidation is conducted at 800-1200° C. for 30-50 minutes.

5. The trench-gate SiC MOSFET device of claim 4, wherein when the the substrate with the trench structure is annealed in a H.sub.2 atmosphere before the formation of the gate electrode, a carbon compound generated in a SiC interface by the annealing is oxidized or removed by the SOP.

6. The trench-gate SiC MOSFET device of claim 1, wherein before the formation of the gate electrode, a TEOS gate oxide film is formed on the substrate with the trench structure, followed by annealing in a NO atmosphere.

7. The trench-gate SiC MOSFET device of claim 1, wherein the substrate is a 4H-SiC substrate.

8. The trench-gate SiC MOSFET device of claim 1, wherein the doping layer of the source region formed in the front surface of the epitaxial layer of the substrate includes doping layers on each of the left and right sides of the gate electrode.

9. The trench-gate SiC MOSFET device of claim 1, wherein when the substrate is a substrate having an N-type epitaxial layer, the doping layer of the source region includes an n+ layer and a p+ layer adjacent to each other in parallel on a p-base layer, on each of the left and right sides of the gate electrode.

10. A method for manufacturing a trench-gate SiC MOSFET device, the method comprising: forming a gate trench by etching a SiC substrate having a doped layer for a source region deeper than the doped layer for a source region; performing ion implantation to form a doped well in a bottom region of the gate trench; performing annealing; forming a gate oxide film; forming a gate electrode within the gate trench; forming an interlayer dielectric on the substrate with the gate electrode; patterning the gate oxide film and the interlayer dielectric; a source electrode covering an upper surface of the doping layer for the source region formed in a front surface of an epitaxial layer of the substrate and an upper surface of the interlayer dielectric; and forming a drain electrode on a back surface of the substrate.

11. The method of claim 10, wherein the annealing is performed in a H.sub.2 atmosphere.

12. The method of claim 10, further comprising, before the performing of the annealing, forming a carbon capping layer on the substrate with the trench structure, followed by annealing in an Ar atmosphere and removal of the carbon capping layer.

13. The method of claim 10, further comprising, before the forming of the gate electrode, performing a sacrificial oxidation process (SOP) in which dry oxidation is conducted at 800-1200° C. for 30-50 minutes.

14. The method of claim 13, wherein a carbon compound generated in a SiC interface by the annealing in a H.sub.2 atmosphere is oxidized or removed by the SOP.

15. The method of claim 14, wherein a reverse leakage current is reduced by the SOP process, the reverse leakage current being caused by a leaky interfacial layer formed by the carbon compound in the trench-gate SiC MOSFET device.

16. The method of claim 14, wherein the carbon compound includes a graphitic carbon layer.

17. The method of claim 10, further comprising, before the forming of the gate electrode, forming a TEOS oxide film for the formation of the gate oxide film, followed by annealing in a NO atmosphere.

18. The method of claim 10, wherein the substrate is a 4H-SiC substrate.

19. The method of claim 10, wherein the doping layer of the source region formed in the front surface of the epitaxial layer of the substrate includes doping layers on each of the left and right sides of the gate electrode.

20. The method of claim 10, wherein when the substrate is a substrate having an N-type epitaxial layer, the doping layer of the source region includes an n+ layer and a p+ layer adjacent to each other in parallel on a p-base layer, on each of the left and right sides of the gate electrode.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0025] The accompanying drawings, which are included as a part of the description to help the understanding of the present disclosure, provide embodiments of the present disclosure and, together with the description, explain the technical spirit of the present disclosure.

[0026] FIG. 1 illustrates a structure of a trench-gate SiC MOSFET device of the present disclosure.

[0027] FIG. 2 illustrates an exemplary SEM image for a sectional structure of the trench-gate SiC MOSFET device of the present disclosure.

[0028] FIG. 3 illustrates a manufacturing method for the trench-gate SiC MOSFET device of the present disclosure.

[0029] FIGS. 4A and 4B illustrate exemplary SEM images for a trench shape before and after H.sub.2 annealing in a trench-gate SiC MOSFET device of the present disclosure.

[0030] FIGS. 5A and 5B illustrate examples of reverse leakage current characteristics and breakdown voltage characteristics in the reverse bias in trench-gate SiC MOSFET devices of the present disclosure manufactured with and without SOP.

[0031] FIG. 6 illustrates images showing transmission microscope observation results according to whether a trench-gate SiC MOSFET device of the present disclosure is manufactured with or without SOP.

BEST MODE FOR CARRYING OUT THE INVENTION

[0032] Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings. In each drawing, like elements are denoted by like reference numerals. Further, the detailed description of well-known functions and/or configurations will be omitted. The following disclosed contents mainly describe portions required to understand operations according to various embodiments and the description of elements which make the gist of the description obscure will be omitted. Further, some of elements of the drawings may be exaggerated, omitted, or schematically illustrated. A size of each element does not completely reflect a real size, and therefore the contents disclosed herein are not limited by a relative size or interval of the elements illustrated in the drawings.

[0033] In describing embodiments of the present disclosure, when it is determined that a detailed description with respect to known technology related to the present disclosure may unnecessarily obscure a gist of the present disclosure, a detailed description thereof will be omitted. The terminology used hereinafter is terms defined by considering functions in embodiments of the present disclosure, and their meaning may be changed according to intentions of a user and an operator, customs, or the like. Accordingly, the term shall be defined based on the contents throughout this specification. The term used in the detailed description is used for describing embodiments of the present disclosure, and is not used for limiting the present disclosure. The singular forms are intended to include the plural forms as well unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising”, “includes”, and/or “including”, when used herein, specify the presence of stated features, figures, steps, operations, elements, or some or combinations thereof, but do not preclude the presence or possibility of one or more other features, figures, steps, operations, elements, or some or combinations thereof.

[0034] The terms first, second, and the like may be used herein to describe various elements, but these elements shall not be limited by these terms, and these terms are only used to distinguish one element from another element.

[0035] FIG. 1 illustrates a structure of a trench-gate SiC MOSFET device 1000 of the present disclosure. FIG. 2 illustrates an exemplary SEM image for a sectional structure of the trench-gate SiC MOSFET device 1000 of the present disclosure.

[0036] Referring to FIGS. 1 and 2, the trench-gate SiC MOSFET device 1000 of the present disclosure includes: a gate oxide film 240 covering a gate trench 230 formed in a substrate (e.g., n-type 4H-SiC substrate) having an epitaxial layer 222; a doped well (e.g., bottom p-well (BPW)) 225 formed below the gate oxide film 240 in a region of the gate trench 230; a gate electrode 250 formed inside the gate trench 230 covered with the gate oxide film 240; an interlayer dielectric 260 formed on the gate electrode 250; a source electrode 270 covering upper surfaces of doping layers 224, 226, and 228 for a source region formed in the front surface of the epitaxial layer of the SiC substrate 200 and an upper surface of an interlayer dielectric 260; and a drain electrode 280 formed on the back surface of the SiC substrate 200.

[0037] The source region formed in the front surface of the epitaxial layer 222 of the SiC substrate 200 includes the doping layers 224, 226, and 228 at each of the left and right sides of the gate electrode 250.

[0038] When the SiC substrate 200 is a substrate having an n-type epitaxial layer as shown in the drawing, the doping layers 224, 226, and 228 of the source region include an n+ layer 228 as a high-concentration n-type doping layer and a p+ layer 226 as a high-concentration p-type doping layer, which are adjacent to each other in parallel, on a p-base layer 224 s a low-concentration p-type doping layer.

[0039] Hereinafter, a manufacturing method for the trench-gate SiC MOSFET device 1000 of the present disclosure will be described in detail with reference to FIG. 3.

[0040] FIG. 3 illustrates a manufacturing method for the trench-gate SiC MOSFET device 1000 of the present disclosure.

[0041] Referring to FIG. 3, for example, a substrate 200 is first prepared in which an n-type (e.g., doped at a concentration of 7×10.sup.15 cm.sup.−3) epitaxial layer 222 is formed on a substrate 210 (e.g., 6-inch n-type 4° off-axis <0001> aligned 4H-SiC substrate) and doping layers 224, 226, and 228 for a source region are formed in a front surface of the epitaxial layer 222 (S110). When the substrate 200 is a substrate having an n-type epitaxial layer as shown in the drawing, the doping layers 224, 226, and 228 of the source region include an n+ layer 228 as a high-concentration n-type doping layer and a p+ layer 226 as a low-concentration p-type doping layer, which are adjacent to each other in parallel, on a p-base layer 224 as a high-concentration p-type doping layer. For example, the p-base layer 224 and the p+ layer 226 may be formed by injection of Al ions and the n+ layer 228 may be formed by injection of N (nitrogen) ions.

[0042] Then, a gate trench 230 is formed by etching deeper than the doping layers 224, 226, and 228 of the source region (S210). For example, SiO.sub.2 deposited by a plasma-enhanced chemical vapor deposition (PECVD) system is patterned with respect to an area corresponding to a region where a gate electrode 250 is to be formed, and a dry etcher using inductive coupled plasma (ICP) is used while the pattern is used as an etching mask, thereby forming a trench (e.g., a trench depth of about 2 μm). For example, trenches with a trench cell pitch of 6.5 μm were formed in an active region of 5×5 mm.sup.2.

[0043] Then, an oxide film is formed (S130). For example, an insulating film of SiO.sub.2 with a thickness of 50-110 nm may be formed on the entire region of the substrate with the trench structure including the side wall and bottom surface of the gate trench. In an embodiment, the thickness of the oxide film on the side wall of the trench was about 80 nm.

[0044] Below the oxide film, in the bottom region of the gate trench 230, a doped well (e.g., BPW) 225 is formed by ion implantation of, for example, Al ions (S140).

[0045] After the doped well (e.g., BPW) 225 is formed, the oxide film is removed, a carbon capping layer is formed on the substrate with the trench structure, followed by annealing at a temperature of 1500-1900° C. (e.g., 1700° C.) for 50-70 minutes (e.g., 60 minutes) in an Ar atmosphere, and then the carbon capping layer may be removed by O.sub.2 plasma asking (S150).

[0046] After the annealing in the Ar atmosphere, the annealing of the substrate with the trench structure is conducted in a H.sub.2 atmosphere at a temperature of 1200-1600° C. (e.g., 1400° C.) for 10-30 minutes (e.g., 20 minutes) to control the shape of the gate trench 230 and smoothen the side wall of the gate trench 230 (S160).

[0047] In addition, before a gate electrode 250 is formed, a sacrificial oxidation process (SOP) is performed. For example, dry oxidation may be conducted on the gate trench of the substrate with the trench structure 230 at 800-1200° C. (e.g., 1000° C.) for 30-50 minutes (e.g., 40 minutes). For comparison, a sample manufactured without SOP is also prepared.

[0048] After the sacrificial oxidation process (SOP) is performed, a tetraethoxysilane (TEOS) oxide film for the formation of gate oxide film (240) is formed at for example 720° C. by a low pressure chemical vapor deposition (LPCVD) system, and oxidation and annealing in a NO atmosphere, that is, nitriding annealing, may be conducted at 800-1200° C. (e.g., 1175° C.) for 60-180 minutes (e.g., 120 minutes). For comparison, a sample manufactured without SOP is also prepared.

[0049] Then, a gate electrode 250 is formed in the gate trench 230 by using a conductive material, such as a metal or polycrystalline Si (S180). For example, highly doped n-type polycrystalline Si may be deposited using a CVD system or the like, followed by patterning, thereby forming the gate electrode 250. An upper surface of the gate electrode 250 is preferably made to be the same plane as the surfaces of the doping layers 224, 226, and 228 of the epitaxial layer 222.

[0050] Then, an interlayer dielectric 260 is formed on the substrate with the gate electrode 250 (S190). The interlayer dielectric 260 may be composed of an insulating film such as SiO.sub.2.

[0051] Then, the gate oxide film 240 and the interlayer dielectric 260 may be simultaneously subjected to patterning through an exposure process using one mask (S200).

[0052] Then, a source electrode 270 is formed using a metal such as a conductive material (e.g., Ti) (S210). For example, a source electrode 270 is formed that covers the upper surfaces of the doping layers 224, 226, and 228 for the source region formed in the front surface of the epitaxial layer 222 of the substrate 200 and the upper surface of the interlayer dielectric 260.

[0053] Then, a drain electrode 280 is formed on a back surface of the substrate 200 by using a conductive material such as a metal (e.g., Ni/Ti alloy) (S220).

[0054] Ohmic layers may be formed before the formation of the source electrode 270 and the drain electrode 280.

[0055] Last, input and output pad metals, respectively, connected to the gate electrode 250, the source electrode 270, and the drain electrode 280, may be formed of Al.

[0056] FIGS. 4A and 4B illustrate exemplary SEM images for a trench shape before and after H.sub.2 annealing in the trench-gate SiC MOSFET device 1000 of the present disclosure.

[0057] FIG. 4A illustrates an exemplary SEM image before H.sub.2 annealing after the formation of the gate oxide film 240, and FIG. 4B illustrates an exemplary SEM image after H.sub.2 annealing after the formation of the gate oxide film 240. After H.sub.2 annealing, the upper and lower corners of the trench 230 were rounded, and the surface of the side wall of the trench 230 was more smoothened.

[0058] FIGS. 5A and 5B illustrate examples of reverse leakage current characteristics and breakdown voltage characteristics in the reverse bias with and without SOP in a trench-gate SiC MOSFET device 1000 of the present disclosure.

[0059] As shown in FIG. 5A, the trench MOSFET manufactured without SOP showed three times higher reverse leakage current in the gate reverse bias than the trench MOSFET manufactured with SOP. It is expected that in the MOSFET manufactured without SOP, the interfacial layer would react with the gate oxide film 240 in the SiC interface to form a carbon compound (a graphitic carbon layer or the like) during the H.sub.2 annealing process by which the surface layer may be chemically transformed. It is therefore assumed that the carbon compound is oxidized and removed during the SOP treatment. The breakdown voltage of the MOSFET manufactured with or without SOP was measured in 800 to 900 V as shown in FIG. 5B. It can be seen that SOP had no great influence on breakdown voltage characteristics.

[0060] FIG. 6 illustrates images showing transmission microscope observation results according to the SOP treatment in a trench-gate SiC MOSFET device of the present disclosure.

[0061] Referring to FIG. 6, the reason why the reverse leakage current characteristics were improved through the sacrificial oxidation process (SOP) can be confirmed by TEM, which shows that a thick interfacial layer was observed at the interface of the gate oxide film in the device manufactured without SOP. This interfacial layer was considered to be a layer formed during the process for the gate oxide film after hydrogen annealing and was assumed to be a leaky interfacial layer. According to the reported results (Y. Kawada et al., Jpn. J. appl. Phys. 48 (2009), p. 116508), a carbon layer may be formed on a SiC surface at 1700° C. in an Ar atmosphere during annealing, and the reason has been reported to be that the carbon remaining after sublimation of Si in the high-temperature SiC surface forms a graphitic carbon layer. Similarly, the graphitic carbon layer remaining in the SiC surface is considered to be effectively removed in the sacrificial oxidation process. In the interface of the trench-gate oxide film of the device manufactured without the sacrificial oxidation process, a carbon compound is highly likely to be generated, and the interfacial layer containing the resultant graphitic carbon with high conductivity causes a high leakage current.

[0062] As set forth above, the trench-gate SiC MOSFET device 1000 according to the present disclosure can provide a trench-gate SiC MOSFET device having a high-quality, stable gate oxide film through H.sub.2 annealing and SOP after the formation of the gate oxide film 240. Through excellent properties, such as low intrinsic carrier concentrations, high dielectric breakdown characteristics, high thermal conductivity and electron drift velocity, and low ON-resistance in SiC, the trench-gate SiC MOSFET device 1000 enables the micronization of devices, that is, the downsizing of cell pitches, and can be operated as a power device for ensuring a high withstand voltage.

[0063] The specified matters and limited embodiments and drawings such as specific elements in the present disclosure have been disclosed for broader understanding of the present disclosure, but the present disclosure is not limited to the embodiments, and various modifications and changes are possible by those skilled in the art without departing from an essential characteristic of the present disclosure. Therefore, the spirit of the present disclosure is defined by the appended claims rather than by the description preceding them, and all changes and modifications that fall within metes and bounds of the claims, or equivalents of such metes and bounds are therefore intended to be embraced by the range of the spirit of the present disclosure.