Method for manufacturing a super flash memory

Abstract

The present application discloses a method for manufacturing a semiconductor device, which includes the following steps: step 1: forming first gate structures on a semiconductor substrate; step 2: performing a first etching process to etch the semiconductor substrate on at least one side of each first gate structure to a certain depth and form a first groove; step 3: performing a stress memorization process, including step 31: forming a stress dielectric layer, the stress dielectric layer covering a peripheral surface of each first gate structure and being filled in the first groove; step 32: performing annealing to transfer the stress of the stress dielectric layer to a channel region; step 33: removing the stress dielectric layer. The present application can increase the effect of transferring the stress of the stress dielectric layer to the channel region, thereby increasing the mobility of channel carriers.

Claims

1. A method for manufacturing a semiconductor device super flash memory, comprising steps of: step 1: providing a semiconductor substrate, forming first gate structures on the semiconductor substrate, and forming a channel region in the semiconductor substrate covered by the first gate structures; step 2: performing a first etching process to etch the semiconductor substrate on at least one side of each first gate structure to a certain depth and form a first groove, wherein a bottom surface of each first gate structure, a top surface of the semiconductor substrate, a top surface of the channel region, and a top surface of the first groove are flat, a bottom surface of the first groove is located below the top surface of the semiconductor substrate, and a bottom surface of the channel region is located below the top surface of the semiconductor substrate; and step 3: performing a stress memorization process, comprising the following sub-steps: step 31: forming a stress dielectric layer, the stress dielectric layer covering a peripheral surface of each first gate structure and being filled in the first groove; step 32: performing annealing to transfer a stress of the stress dielectric layer to the channel region, the stress in the channel region after stress transfer being increased in the process of stress transfer by using a characteristic that the stress dielectric layer located in the first groove laterally acts on the channel region; and step 33: removing the stress dielectric layer, wherein, in step 1, each first gate structure is a word line gate of a flash memory cell of the super flash memory; and in step 2, the first groove is located in a source region side of the first gate structure, the first etching process is an over-etching process of a source contact etching process, the source contact etching process firstly etches a first dielectric layer between adjacent first gate structures to form a source contact opening and then over-etches the semiconductor substrate at a bottom of the source contact opening to form the first groove, and the first groove is used as a part of the source contact opening, wherein, after step 3, the method for manufacturing the super flash memory further comprises the following steps: forming a source region in the semiconductor substrate at a bottom of the first groove; and forming a floating gate and a source line in the source contact opening, wherein in a transverse direction, the floating gate is located between the first gate structure and the source line; the floating gate and a side surface of the source region side of the first gate structure are isolated by a first inter-gate dielectric layer, and the first inter-gate dielectric layer comprises the first dielectric layer; the floating gate and the source line are isolated by a second inter-gate dielectric layer; a bottom of the source line is in direct contact with the source region; a bottom section of the floating gate is located in the first groove, and the bottom surface of the floating gate and the semiconductor substrate are isolated by a floating gate dielectric layer; during writing, the source line is simultaneously used as a control gate, and under the control of the control gate, electrons in the channel region are implanted into the bottom section of the floating gate under an effect of a transverse electric field; and a top surface of the floating gate is higher than a top surface of the source line.

2. The method for manufacturing the super flash memory according to claim 1, wherein the semiconductor substrate comprises a silicon substrate.

3. The method for manufacturing the super flash memory according to claim 1, wherein each first gate structure comprises a first gate dielectric layer and a first polysilicon gate superposed sequentially.

4. The method for manufacturing the super flash memory according to claim 1, wherein, in step 2, two sides of each first gate structure are respectively a source region side and a drain region side; the first groove is located in the source region side of the first gate structure; or the first groove is located in the source region side and the drain region side of the first gate structure.

5. The method for manufacturing the super flash memory according to claim 1, wherein a depth of the first groove is 200{acute over ()}.

6. The method for manufacturing the super flash memory according to claim 1, wherein the method for manufacturing the super flash memory further comprises: forming an erase gate, wherein the erase gate covers tops of the floating gate and the source line, and the erase gate, and the floating gate and the source line at the bottom are isolated by a third inter-gate dielectric layer.

7. The method for manufacturing the super flash memory according to claim 1, wherein the floating gate consists of a TiN layer.

8. The method for manufacturing the super flash memory according to claim 1, wherein the annealing in step 32 is rapid thermal annealing.

9. The method for manufacturing the super flash memory according to claim 1, wherein, in step 31, the stress dielectric layer has tensile stress, the super flash memory is an N-type device, and the channel region is a P-type doped region.

10. The method for manufacturing the super flash memory according to claim 9, wherein the stress dielectric layer is a first silicon nitride layer with tensile stress.

11. The method for manufacturing the super flash memory according to claim 10, wherein, before forming the stress dielectric layer, the method for manufacturing the super flash memory further comprises a step of forming a stress blocking layer, and in the first groove, the stress blocking layer is located between the stress dielectric layer and the semiconductor substrate to prevent stress damage caused by the stress dielectric layer to the semiconductor substrate.

12. The method for manufacturing the super flash memory according to claim 11, wherein a material of the stress blocking layer comprises silicon dioxide.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present application will be described below in detail in combination with the embodiments with reference to the drawings.

(2) FIG. 1 illustrates a schematic diagram of a structure of an existing 38 super flash memory.

(3) FIG. 2 illustrates a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application.

(4) FIG. 3A to FIG. 3F illustrate schematic diagrams of structures of devices in each step of a method for manufacturing a semiconductor device according to an embodiment of the present application.

(5) FIG. 4A to FIG. 4B illustrate schematic diagrams of structures of devices in each step of a method for manufacturing a semiconductor device according to a preferred embodiment of the present application.

DETAILED DESCRIPTION

(6) Referring to FIG. 2, it illustrates a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application. Referring to FIG. 3A to FIG. 3F, they illustrate schematic diagrams of structures of devices in each step of a method for manufacturing a semiconductor device according to an embodiment of the present application. The method for manufacturing the semiconductor device according to the embodiment of the present application includes the following steps:

(7) In step 1, referring to FIG. 3A, a semiconductor substrate 201 is provided, first gate structures 202 are formed on the semiconductor substrate 201, and a channel region is formed in the semiconductor substrate 201 covered by the first gate structures 202.

(8) In the method according to the embodiment of the present application, the semiconductor substrate 201 includes a silicon substrate.

(9) Each first gate structure 202 includes a first gate dielectric layer and a first polysilicon gate superposed sequentially.

(10) The formation area of the channel region is as illustrated by a dotted box 301.

(11) In step 2, referring to FIG. 3A, a first etching process is performed to etch the semiconductor substrate 201 on at least one side of each first gate structure 202 to a certain depth and form a first groove 303a.

(12) In FIG. 3A, two adjacent first gate structures 202 are illustrated. An area between the two first gate structures 202 is an area shared by the two first gate structures 202, such as the shaped formation area on the source region side. In other embodiments, a first groove 303a may also be formed in the formation area on the drain region side of the first gate structure 202.

(13) In the embodiment of the present application, before the first etching process, the method further includes a step of forming a first dielectric layer 302. The material of the first dielectric layer 302 may be an oxide layer. The first etching process will form an opening 303 in the first dielectric layer 302. The first groove 303a is a part of the opening 303, that is, a bottom part.

(14) In step 3, a stress memorization process is performed, which includes the following sub-steps:

(15) In step 31, referring to FIG. 3C, a stress dielectric layer 305 is formed. The stress dielectric layer 305 covers a peripheral surface of each first gate structure 202 and is filled in the first groove 303a.

(16) In the embodiment of the present application, the stress dielectric layer 305 in step 31 has tensile stress, the semiconductor device is an N-type device, and the channel region is a P-type doped region. In some embodiments, the stress dielectric layer 305 is a first silicon nitride layer with tensile stress.

(17) Returning to FIG. 3B, before forming the stress dielectric layer 305, the method further includes a step of forming a stress blocking layer 304. In the first groove 303a, the stress blocking layer 304 is located between the stress dielectric layer 305 and the semiconductor substrate 201 to prevent stress damage caused by the stress dielectric layer 305 to the semiconductor substrate 201. In some embodiments, the material of the stress blocking layer 304 is silicon dioxide.

(18) In step 32, referring to FIG. 3D, annealing is performed to transfer the stress of the stress dielectric layer 305 to the channel region. The stress in the channel region after stress transfer is increased in the process of stress transfer by using the characteristic that the stress dielectric layer 305 located in the first groove 303a laterally acts on the channel region. In FIG. 3D, the annealing process is represented by a reference sign 306.

(19) In the embodiment of the present application, the annealing is rapid thermal annealing.

(20) It can be seen from FIG. 3D that the effect of the stress dielectric layer 305 located in the first groove 303a on the channel region is obviously higher than that of the stress dielectric layer 305 above the first groove 303a on the channel region. Therefore, the embodiment of the present application can increase the stress transfer effect on the channel region by adding the first groove 303a, thus increasing the stress in the channel region.

(21) In step 33, the stress dielectric layer 305 is removed.

(22) In the embodiment of the present application, the stress dielectric layer 305 is removed by chemical-mechanical polishing, dry etching or wet etching, that is, the stress dielectric layer 305 can be removed by combining chemical-mechanical polishing, dry etching and wet etching processes. For example:

(23) First, referring to FIG. 3E, the stress dielectric layer 305 on the surface of the stress blocking layer 304 outside the opening 303 is removed by using the chemical-mechanical polishing process by directly using the stress blocking layer 304 as a stop layer. The stress dielectric layer 305 on the surface of the stress blocking layer 304 outside the opening 303 may also be removed by combining dry etching and chemical-mechanical polishing.

(24) Secondly, referring to FIG. 3F, the stress dielectric layer 305 is removed through a wet etching process; Since the stress dielectric layer 305 is a first silicon nitride layer, the etching solution for wet etching that can remove the stress dielectric layer 305 is hot phosphoric acid.

(25) Then, the stress blocking layer 304 is removed through wet etching. In this way, the structure of the device returns to the structure illustrated in FIG. 3A, but the stress in the channel region in the structure illustrated in FIG. 3F is changed.

(26) In the existing Stress Memorization Technique (SMT), the stress dielectric layer 305, such as silicon nitride with tensile stress, is directly formed after the formation of the gate structure. Using the characteristic that the stress dielectric layer 305 covers the gate structure, the stress in the stress dielectric layer 305 is transferred to the channel region covered by the gate structure through annealing. Based on the existing SMT, in the embodiment of the present application, the semiconductor substrate 201 on at least one side of the first gate structure 202 is further etched after the formation of the first gate structure 202 to form a first groove 303a, so that the stress dielectric layer 305 will not only cover the first gate structure 202, but also is formed in the first groove 303a. During annealing for stress transfer, the stress dielectric layer 305 located in the first groove 303a will have a lateral direct effect on the channel region, which is better than the effect of the stress dielectric layer 305 covering the peripheral side of the first gate structure 202 on the channel region. Therefore, the present application can finally increase the stress in the channel region, thus increasing the mobility of channel carriers and finally improving the performance of the device.

(27) In addition, the present application can be implemented by combining the etching and SMT process of the semiconductor substrate 201 on the side of the gate structure, and has the characteristic of simple process. Therefore, the embodiment of the present application can be easily added to the manufacturing process of the super flash memory and effectively improve the reading and writing operation performance of the flash memory cell.

(28) The method for manufacturing the semiconductor device according to the preferred embodiment of the present application will be described below with reference to FIGS. 3A-3F, 4A and 4B. The method for manufacturing the semiconductor device according to the preferred embodiment of the present application is formed by applying the method according to the embodiment of the present application corresponding to FIG. 3A-3F to a method for manufacturing super flash memory. The method for manufacturing the semiconductor device according to the preferred embodiment of the present application includes the following steps:

(29) Firstly, step 1 to step 3 corresponding to FIG. 3A to FIG. 3F are completed.

(30) In step 1, the first gate structure 202 is a word line gate of a flash memory cell of a super flash memory.

(31) In step 2, the first groove 303a is located on a source region side of the first gate structure 202, the opening 303 is a source contact opening, and the first etching process is an over-etching process of a source contact etching process. The source contact etching process firstly etches the first dielectric layer 302 between the adjacent first gate structures 202 to form a source contact opening, and then etches the semiconductor substrate 201 at a bottom of the source contact opening to form the first groove 303a which is a part of the source contact opening.

(32) In some embodiments, the depth of the first groove 303a is 200 {acute over ()}.

(33) In step 31, the thickness of the stress blocking layer 304 is 50 {acute over ()}.

(34) The thickness of the stress dielectric layer 305 is 650 {acute over ()}.

(35) After step 3, the method further includes the following steps:

(36) Referring to FIG. 4A, a source region 209 is formed in the semiconductor substrate 201 at the bottom of the first groove 303a.

(37) A floating gate 204 and a source line 206 are formed in the source contact opening.

(38) In a transverse direction, the floating gate 204 is located between the first gate structure 202 and the source line 206.

(39) The floating gate 204 and a side surface of the source region side of the first gate structure 202 are isolated by a first inter-gate dielectric layer 203. The first inter-gate dielectric layer 203 includes the first dielectric layer 302.

(40) The floating gate 204 and the source line 206 are isolated by a second inter-gate dielectric layer.

(41) A bottom of the source line 206 is in direct contact with the source region 209.

(42) A bottom section of the floating gate is located in the first groove 303a, and the bottom surface of the floating gate 204 and the semiconductor substrate 201 are isolated by a floating gate dielectric layer; during writing, the source line 206 is simultaneously used as a control gate, and under the control of the control gate, electrons in the channel region are implanted into the bottom section of the floating gate 204 under the effect of a transverse electric field.

(43) A top surface of the floating gate 204 is higher than a top surface of the source line 206.

(44) The floating gate 204 consists of a TiN layer.

(45) The method further includes the following steps:

(46) Referring to FIG. 4B, an erase gate 208 is formed.

(47) The erase gate 204 covers tops of the floating gate 208 and the source line 206, and the erase gate 208 and the floating gate 204 and the source line 206 at the bottom are isolated by a third inter-gate dielectric layer 207.

(48) FIG. 4B does not illustrate the structure of the drain region end of the flash memory cell. The drain region of the flash memory cell is formed in the drain region side of the first gate structure. Since the drain region process will not affect the process of the source region side, it will not be described in detail here.

(49) In the manufacturing process of the super flash memory, the semiconductor substrate 201 is often etched in the existing source contact etching process of the super flash memory, so the technical effect of increasing the stress in the channel region can be achieved by adding the SMT process after the source contact etching process is completed. Therefore, the preferred embodiment of the present application can be implemented by only specially setting the time of the SMT process. Compared with the existing method in which the SMT process is performed after the formation of the gate structure, the SMT process is performed after the source contact etching process in the preferred embodiment of the present application. Therefore, the preferred embodiment of the present application can significantly increase the stress in the channel region of the flash memory cell of the super flash memory without adding additional process and time cost, thus improving the reading-writing performance of the flash memory cell.

(50) The present application has been described in detail through specific embodiments, which, however, do not constitute limitations to the present application. Without departing from the principle of the present application, those skilled in the art can also make many modifications and improvements, which should also be considered as include in the scope of protection of the present application.