Manufacturing method of forming semiconductor device and semiconductor device

Abstract

A method of forming a semiconductor device and the structure of the semiconductor device are provided. The manufacturing method includes the following steps of: providing a native substrate; sequentially forming a first nucleation layer, a thick GaN substrate layer, a second nucleation layer, an AlGaN barrier layer, a GaN channel layer and a leakage current stop layer; forming an aperture area through the leakage current stop layer; forming a GaN buffer layer; implanting Mg ions to the GaN buffer layer to form a current blocking layer; forming a GaN drift layer; forming a metallic interlayer on the GaN drift layer and transferring the GaN drift layer on a transferred substrate through the metallic interlayer; removing a semiconductor stack; forming a source contact, a gate contact and a drain contact.

Claims

1. A manufacturing method of forming a semiconductor device, the manufacturing method comprising: providing a native substrate, the native substrate having a lattice mismatch with GaN less than 3.6%; sequentially forming a first nucleation layer, a thick GaN substrate layer, a second nucleation layer, an AlGaN barrier layer, a GaN channel layer and a leakage current stop layer on the native substrate, the first nucleation layer, the thick GaN substrate layer, the second nucleation layer, the GaN channel layer and the leakage current stop layer being un-doped; forming an aperture area through the leakage current stop layer; forming a GaN buffer layer on the leakage current stop layer and the aperture area; implanting Mg ions to the GaN buffer layer to form a current blocking layer on the leakage current stop layer; forming a GaN drift layer on the current blocking layer and the GaN buffer layer; forming a metallic interlayer on the GaN drift layer and transferring the GaN drift layer on a transferred substrate through the metallic interlayer; removing a semiconductor stack, the semiconductor stack comprising the second nucleation layer, the thick GaN substrate layer, the first nucleation layer and the native substrate; forming a source contact through the AlGaN barrier layer, the source contact contacting the GaN channel layer; forming a gate contact on the AlGaN barrier layer; forming a drain contact on the transferred substrate.

2. The manufacturing method of claim 1, wherein the native substrate comprises GaN, AlN or SiC.

3. The manufacturing method of claim 1, wherein the first nucleation layer comprises an AlN layer or an AlN/AlGaN superlattice layer.

4. The manufacturing method of claim 3, wherein the AlN/AlGaN superlattice layer is composed of Al.sub.(x)Ga.sub.(1-x)N and mole fraction x of the Al.sub.(x)Ga.sub.(1-x)N is above 0.6.

5. The manufacturing method of claim 1, wherein the thick GaN substrate layer has a thickness and the thickness is above 1 m.

6. The manufacturing method of claim 1, wherein the second nucleation layer comprises an AlN layer or an AlN/AlGaN superlattice layer.

7. The manufacturing method of claim 6, wherein the AlN/AlGaN superlattice layer is composed of Al.sub.(y)Ga.sub.(1-y)N and mole fraction y of the Al.sub.(y)Ga.sub.(1-y)N is above 0.6.

8. The manufacturing method of claim 1, wherein the leakage current stop layer comprises AlN or Ga.sub.2O.sub.3.

9. The manufacturing method of claim 1, wherein the current blocking layer is formed by selective Mg ion implantation.

10. The manufacturing method of claim 1, wherein the semiconductor stack is removed by mechanical thinning, chemical etching, photoelectrochemical etching or laser lift-off.

11. The manufacturing method of claim 1, wherein the transferred substrate comprises Si, GaAs, Al.sub.2O.sub.3 or Ga.sub.2O.sub.3.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The technical features, detail structures, advantages and effects of the present disclosure will be described in more details hereinafter with reference to the accompanying drawings that show various embodiments of the invention as follows.

(2) FIG. 1A to FIG. 1J are schematic diagrams of the manufacturing process of forming the semiconductor device in accordance with the embodiment of the present disclosure.

(3) FIG. 2 is schematic diagram of the semiconductor device in accordance with the embodiment of the present disclosure.

(4) FIG. 3A to FIG. 3J are schematic diagrams of the manufacturing process of forming the semiconductor device in accordance with another embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(5) In order to facilitate the understanding of the technical features, the contents and the advantages of the present disclosure, and the effectiveness thereof that can be achieved, the present disclosure will be illustrated in detail below through embodiments with reference to the accompanying drawings. The diagrams used herein are merely intended to be schematic and auxiliary to the specification, but are not necessary to be true scale and precise to the configuration after implementing the present disclosure. Thus, it should not be interpreted in accordance with the scale and the configuration of the accompanying drawings to limit the scope of the present disclosure on the practical implementation.

(6) As those skilled in the art would realize, the described embodiments may be modified in various different ways. The exemplary embodiments of the present disclosure are for explanation and understanding only. The drawings and description are to be regarded as illustrative in nature and not restrictive. Similar reference numerals designate similar elements throughout the specification.

(7) It is to be acknowledged that, although the terms first, second, third, and so on, may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only for the purpose of distinguishing one component from another component. Thus, a first element discussed herein could be termed a second element without altering the description of the present disclosure. As used herein, the term or includes any and all combinations of one or more of the associated listed items.

(8) It will be acknowledged that when an element or layer is referred to as being on, connected to or coupled to another element or layer, it can be directly on, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being directly on, directly connected to or directly coupled to another element or layer, there are no intervening elements or layers present.

(9) Please refer to FIG. 1A and FIG. 1J, which are schematic diagrams of the manufacturing process of forming the semiconductor device in accordance with the embodiment of the present disclosure.

(10) In FIG. 1A, the manufacturing process provides a native substrate 11, the native substrate 11 having a lattice mismatch with GaN less than 3.6%. The manufacturing process provides a native substrate 11 and the native substrate 11 may be the substrate for disposing the semiconductor layers formed by the following steps. The native substrate 11 does not limited by the specific material. For example, the native substrate 11 may include GaN, AlN or SiC.

(11) In FIG. 1B, the manufacturing process sequentially forms a first nucleation layer 121, a thick GaN substrate layer 122, a second nucleation layer 123, an AlGaN barrier layer 13, a GaN channel layer 14 and a leakage current stop layer 15 on the native substrate 11. The first nucleation layer 121, the thick GaN substrate layer 122, the second nucleation layer 123, the GaN channel layer 14 and the leakage current stop layer 15 are un-doped. The semiconductor device does not need to consider the doping concentration problem in the manufacturing processes. Continued from the previous step, the several semiconductor layers are sequentially formed on the native substrate 11. Since the native substrate 11 may be low lattice mismatched substrate, the present step forms the thick GaN substrate layer 122 to enhance the reliability of the later active GaN based epitaxial growth.

(12) Firstly, the first nucleation layer 121 is formed on the native substrate 11. The first nucleation layer 121 may be an AlN layer or an AlN/AlGaN superlattice layer. If the first nucleation layer 121 is the AlN/AlGaN superlattice layer, the AlN/AlGaN superlattice layer is composed of Al.sub.(x)Ga.sub.(1-x)N and the mole fraction x of the Al.sub.(x)Ga.sub.(1-x)N is above 0.6. For example, x may be 0.7 or 0.8. Then the thick GaN substrate layer 122 is formed on the first nucleation layer 121. The thick GaN substrate layer 122 may have a thickness and the thickness is above 1 m. The thick GaN substrate layer 122 should be thick enough to ensure that the lattice is neatly arranged and the surface of the thick GaN substrate layer 122 is the almost defect-free surface.

(13) The second nucleation layer 123 is formed on the thick GaN substrate layer 122. Similar to the first nucleation layer 121, the second nucleation layer 123 may be an AlN layer or an AlN/AlGaN superlattice layer. If the second nucleation layer 123 is the AlN/AlGaN superlattice layer, the AlN/AlGaN superlattice layer is composed of Al.sub.(y)Ga.sub.(1-y)N and the mole fraction y of the Al.sub.(y)Ga.sub.(1-y)N is above 0.6. For example, y may be 0.7 or 0.8. Based on the thick GaN substrate layer 122 and the second nucleation layer 123, the lattice is neatly arranged. The active region formed on the above stacked layer may be the low defect active region.

(14) After forming the low defect layer, the AlGaN barrier layer 13 and the GaN channel layer 14 are sequentially formed on the second nucleation layer 123. The AlGaN barrier layer 13 is disposed on the second nucleation layer 123 and the GaN channel layer 14 is disposed on the AlGaN barrier layer 13. The AlGaN barrier layer 13 and the GaN channel layer 14 may be the active region. The two dimensional electron gas 2DEG is occurred at the GaN channel layer 14 and the carrier transport of the two dimensional electron gas 2DEG may generate a current flow for the semiconductor device.

(15) When the semiconductor device drives to generate the current flow, some current leakage paths may be generated from source to drain. In order to prevent the current leakage, the blocking layer is used to block the leakage path. However, the conventional epi-growth method is not easy to form the block layer at predetermined area. The lattice stacked at the location of current flow may also be influenced. Therefore, the present disclosure forming the leakage current stop layer 15 on the GaN channel layer 14. The leakage current stop layer 15 may include AlN or Ga.sub.2O.sub.3. The leakage current stop layer 15 is the ultra-wide bandgap interlayer, for example, the AlN is 6.2 eV. The leakage current stop layer 15 is grown on the entire area of the channel structure, that is, the GaN channel layer 14. Compared to partial growth process, the present manufacture process may have higher process reliability and better product quality.

(16) In FIG. 1C, the manufacturing process forms an aperture area 151 through the leakage current stop layer 15. The leakage current stop layer 15 is etched by a hard mask to form the aperture area 151. The aperture area 151 is corresponding to the gate area. The etching process may expose the top surface of the GaN channel layer 14.

(17) In FIG. 1D, the manufacturing process forms a GaN buffer layer 16 on the leakage current stop layer 15 and the aperture area 151. The GaN layer buffer layer 16 is growing from the GaN channel layer 14 and to fill up the aperture area 151. The GaN layer buffer layer 16 is further growing form the surface of the leakage current stop layer 15 and the aperture area 151.

(18) In FIG. 1E, the manufacturing process implants Mg ions to the GaN buffer layer 16 to form a current blocking layer 161 on the leakage current stop layer 15. The Mg ion implantation can be conducted on the GaN buffer layer 16. For example, the selective Mg ion implantation. Using the implantation process instead of the GaN buffer regrowth layer process may form the planar surface. The gate current leakage caused by the non-planar surface can be avoided.

(19) In FIG. 1F, the manufacturing process forms a GaN drift layer 17 on the current blocking layer 161 and the GaN buffer layer 16. In the previous process, the Mg ions are implanted in the GaN buffer layer 16. The surface of the GaN buffer layer 16 and the surface of the current blocking layer 161 are flat. The GaN buffer layer 16 is formed on the planar surface and the quality of the GaN growth will be better. The GaN growing process may be the metal organic chemical vapor phase deposition (MOCVD) process.

(20) In FIG. 1G, the manufacturing process forms a metallic interlayer 181 on the GaN drift layer 17 and transferring the GaN drift layer 17 on a transferred substrate 18 through the metallic interlayer 181. In order to transfer the semiconductor device formed by the previous processes, the metallic interlayer 181 is formed on the GaN drift layer 17. At the same time, the transferred substrate 18 also has a metallic interlayer 181 disposed on the surface of the transferred substrate 18. The transferred substrate 18 may include Si, GaAs, Al.sub.2O.sub.3 or Ga.sub.2O.sub.3. The above material for forming the transferred substrate 18 is not easy to combine with the GaN drift layer 17. Therefore, the metallic interlayer 181 is used as the buffer layer for combining the transferred substrate 18 and the GaN drift layer 17.

(21) In FIG. 1H, the manufacturing process removes a semiconductor stack, the semiconductor stack includes the second nucleation layer 123, the thick GaN substrate layer 122, the first nucleation layer 121 and the native substrate 11. Since the transferred substrate 18 is disposed on the GaN drift layer 17, the transferred substrate 18 is regarded as the main substrate of the semiconductor device. In the present step, the semiconductor stacked is removed to expose the AlGaN barrier layer 13. The semiconductor stack may be removed by mechanical thinning, chemical etching, photoelectrochemical etching or laser lift-off.

(22) The semiconductor stack includes the second nucleation layer 123, the thick GaN substrate layer 122, the first nucleation layer 121 and the native substrate 11. Since the semiconductor stack is removed, the thick GaN substrate layer 122 and the native substrate 11 can be recycled and used at different manufacturing processes. The manufacturing cost can be reduced by saving the substrate material. In addition, the material of the transferred substrate 18 can be selected according to needs. The process flexibility can be increased.

(23) In FIG. 1I, the manufacturing process forms source contacts 191 through the AlGaN barrier layer 13, the source contacts 191 contact the GaN channel layer 14. In the previous process, the semiconductor stack is removed. The remained semiconductor device can be flipped over. That is, the transferred substrate 18 is on the bottom and the AlGaN barrier layer 13 is on the top. The transferred substrate 18 has a rear surface 182 and the AlGaN barrier layer 13 has a tops surface 131. The AlGaN barrier layer 13 can be etched from the tops surface 131 to form the voids. The source contacts 191 are formed by filling up the voids with the conductive material, for example, the material can be copper. The source contacts 191 may pass through the AlGaN barrier layer 13 and contact the GaN channel layer 14. In some embodiments, the source contacts 191 may pass through the GaN channel layer 14 with predetermined depth.

(24) In FIG. 1J, the manufacturing process forms a gate contact 192 on the AlGaN barrier layer 13 and forms drain contact 193 on the transferred substrate 18. After forming the source contacts 191, the gate contact 192 is formed on the top surface 131 of the AlGaN barrier layer 13 and the drain contact 193 is formed on the rear surface 182 of the transferred substrate 18. In the present embodiment, the drawing only shows the single gate contact structure and single drain contact structure. However, the present disclosure is not limited to the single contact structure. In other embodiment, the gate contact 192 and the drain contact 193 can be plural. The gate contact 192 is disposed at the location corresponding to the aperture area 151, that is, the GaN buffer layer 161. The drain contact 193 may be overlapped to the leakage current stop layer 15 and the current blocking layer 161. Based on the leakage current stop layer 15 and the current blocking layer 161, the current leakage path from the source contacts 191 to the drain contact 193 can be blocked. The parasitic leakage current penetrating the current blocking layer 161 can be avoided, so as to form the high speed power current aperture vertical electron transistor (CAVET) with excellent reliability.

(25) Please refer to FIG. 2, which is the schematic diagram of the semiconductor device in accordance with the embodiment of the present disclosure.

(26) As shown in FIG. 2, the semiconductor device 20 includes a transferred substrate 21, a metallic interlayer 22, a GaN drift layer 23, a current blocking layer 241, a GaN buffer layer 242, a leakage current stop layer 25, a GaN channel layer 26 and an AlGaN barrier layer 27. The transferred substrate 21 has a drain contact 211 formed on a rear surface 212 of the transferred substrate 21. The AlGaN barrier layer 27 has source contacts 271 and gate contact 272. The source contacts 271 are disposed through the AlGaN barrier layer 27 for contacting the GaN channel layer 26 and the gate contact 272 is disposed on a top surface 273 of the AlGaN barrier layer 27.

(27) The transferred substrate 21 may include Si, GaAs, Al.sub.2O.sub.3 or Ga.sub.2O.sub.3. The metallic interlayer 22 is disposed on the transferred substrate 21. The GaN drift layer 23 is disposed on the metallic interlayer 22. Similar to the previous embodiment, the semiconductor device can be manufactured to a semiconductor layers group first and then transferred the semiconductor layers group to the transferred substrate 21. In the present disclosure, the semiconductor layers group include the GaN drift layer 23, the current blocking layer 241, the GaN buffer layer 242, the leakage current stop layer 25, the GaN channel layer 26 and the AlGaN barrier layer 27. The transferred process uses metallic interlayer 22 to combine the transferred substrate 21 with the GaN drift layer 23.

(28) In the semiconductor layers group, the current blocking layer 241 is disposed on the GaN drift layer 23 and the current blocking layer 241 is formed by Mg ion implantation to a GaN layer. The GaN buffer layer 242 is disposed on an aperture area of the GaN layer. The leakage current stop layer 25 is disposed on the current blocking layer 241. The GaN channel layer 26 is disposed on the GaN buffer layer 242 and the leakage current stop layer 25. The AlGaN barrier layer 27 is disposed on the GaN channel layer 26.

(29) The GaN layer is disposed on the GaN drift layer 23. This GaN layer may have two parts, one is the current blocking layer 241 and the other one is the GaN buffer layer 242. The GaN buffer layer 242 is the original GaN layer. The current blocking layer 241 is formed by Mg ion implantation to the GaN layer at the current leakage path location. The current blocking layer 241 may be formed by selective Mg ion implantation. The leakage current stop layer 25 is disposed on the current blocking layer 241. The leakage current stop layer 25 is also at the current leakage path location. The leakage current stop layer 25 may include AlN or Ga.sub.2O.sub.3. The leakage current stop layer 25 is the ultra-wide bandgap interlayer, for example, the AlN is 6.2 eV. Based on the leakage current stop layer 25 and the current blocking layer 241, the current leakage path from the source contacts 271 to the drain contact 211 can be blocked. The parasitic leakage current penetrating the current blocking layer 241 can be avoided, so as to form the high speed power current aperture vertical electron transistor (CAVET) with excellent reliability.

(30) The channel layer is disposed on the GaN layer. The channel layer includes the GaN channel layer 26 and the AlGaN barrier layer 27. The GaN channel layer 26 is disposed on the GaN buffer layer 242 and the leakage current stop layer 25. The AlGaN barrier layer 27 is disposed on the GaN channel layer 26. Based on the heterostructure of the GaN layer and the AlGaN layer, the two dimensional electron gas 2DEG is occurred at the GaN channel layer. The carrier transport of the two dimensional electron gas 2DEG may generate a current flow for the semiconductor device 20.

(31) The transferred substrate 21 has the drain contact 211 formed on a rear surface 212 of the transferred substrate 21. The drain contact 211 may be overlapped to the leakage current stop layer 15 and the current blocking layer 161. The AlGaN barrier layer 27 has source contacts 271 and gate contact 272. The source contacts 271 are disposed through the AlGaN barrier layer 27 for contacting the GaN channel layer 26 and the gate contact 272 is disposed on a top surface 273 of the AlGaN barrier layer 27. In the present embodiment, the drawing only shows the single gate contact structure and single drain contact structure. However, the present disclosure is not limited to the single contact structure. In other embodiment, the gate contact 272 and the drain contact 211 can be plural.

(32) In the present embodiment, the GaN channel layer 26, the leakage current stop layer and the GaN buffer layer may be un-doped. The semiconductor device 20 does not need to consider the doping concentration problem in the manufacturing processes.

(33) Please refer to FIG. 3A to FIG. 3H, which are the schematic diagrams of the manufacturing process of forming the semiconductor device in accordance with another embodiment of the present disclosure.

(34) In FIG. 3A, the manufacturing process provides a thick GaN substrate 31. In the present embodiment, the first substrate may select the GaN substrate with predetermined thickness. The thickness is above 1 m. The thick GaN substrate 31 may ensure that the lattice is neatly arranged and the surface of the thick GaN substrate layer 31 is the almost defect-free surface. The thick GaN substrate 31 may also prevent the defect caused by the substrate with the lattice mismatch with GaN less than 3.6%.

(35) In FIG. 3B, the manufacturing process sequentially forms a nucleation layer 32, an AlGaN barrier layer 33, a GaN channel layer 34 and a leakage current stop layer 35 on the thick GaN substrate 31. The nucleation layer 32, the GaN channel layer 34 and the leakage current stop layer 35 are un-doped. Continue from the previous step, the several semiconductor layers are sequentially formed on the thick GaN substrate 31. Since the thick GaN substrate 31 is used, the nucleation layer 32 is formed on the GaN layer once.

(36) The nucleation layer 32 is formed on the GaN substrate 31. The nucleation layer 32 may be an AlN layer or an AlN/AlGaN superlattice layer. If the nucleation layer 32 is the AlN/AlGaN superlattice layer, the AlN/AlGaN superlattice layer is composed of Al.sub.(x)Ga.sub.(1-x)N and the mole fraction x of the Al.sub.(x)Ga.sub.(1-x)N is above 0.6. For example, x may be 0.7 or 0.8. Based on the thick GaN substrate layer 31 and the nucleation layer 32, the lattice is neatly arranged. The active region formed on the above stacked layer may be the low defect active region.

(37) After forming the low defect layer, the AlGaN barrier layer 33 and the GaN channel layer 34 are sequentially formed on the nucleation layer 32. The AlGaN barrier layer 33 is disposed on the nucleation layer 32 and the GaN channel layer 34 is disposed on the AlGaN barrier layer 33. The AlGaN barrier layer 33 and the GaN channel layer 34 may be the active region. The two dimensional electron gas 2DEG is occurred at the GaN channel layer 34 and the carrier transport of the two dimensional electron gas may generate a current flow for the semiconductor device.

(38) When the semiconductor device drives to generate the current flow, some current leakage paths may be generated from source to drain. In order to prevent the current leakage, the blocking layer is used to block the leakage path. However, the conventional epi-growth method is not easy to form the block layer at predetermined area. The lattice stacked at the location of current flow may also be influenced. Therefore, the present disclosure forming the leakage current stop layer 35 on the GaN channel layer 34. The leakage current stop layer 35 may include AlN or Ga.sub.2O.sub.3. The leakage current stop layer 35 is the ultra-wide bandgap interlayer, for example, the AlN is 6.2 eV. The leakage current stop layer 35 is grown on the entire area of the channel structure, that is, the GaN channel layer 34. Compared to partial growth process, the present manufacture process may have higher process reliability and better product quality.

(39) In FIG. 3C, the manufacturing process forms an aperture area 351 through the leakage current stop layer 35. The leakage current stop layer 35 is etched by a hard mask to form the aperture area 351. The aperture area 351 is corresponding to the gate area. The etching process may expose the top surface of the GaN channel layer 34.

(40) In FIG. 3D, the manufacturing process forms a GaN buffer layer 36 on the leakage current stop layer 35 and the aperture area 351. The GaN layer buffer layer 36 is growing from the GaN channel layer 34 and to fill up the aperture area 351. The GaN layer buffer layer 36 is further growing form the surface of the leakage current stop layer 35 and the aperture area 351.

(41) In FIG. 3E, the manufacturing process implants Mg ions to the GaN buffer layer 36 to form a current blocking layer 361 on the leakage current stop layer 35. The Mg ion implantation can be conducted on the GaN buffer layer 36. For example, the selective Mg ion implantation. Using the implantation process instead of the GaN buffer regrowth layer process may form the planar surface. The gate current leakage caused by the non-planar surface can be avoided.

(42) In FIG. 3F, the manufacturing process forms a GaN drift layer 37 on the current blocking layer 361 and the GaN buffer layer 36. In the previous process, the Mg ions are implanted in the GaN buffer layer 36. The surface of the GaN buffer layer 36 and the surface of the current blocking layer 361 are flat. The GaN buffer layer 36 is formed on the planar surface and the quality of the GaN growth will be better. The GaN growing process may be the metal organic chemical vapor phase deposition (MOCVD) process.

(43) In FIG. 3G, the manufacturing process forms a metallic interlayer 381 on the GaN drift layer 37 and transferring the GaN drift layer 37 on a transferred substrate 38 through the metallic interlayer 381. In order to transfer the semiconductor device formed by the previous processes, the metallic interlayer 381 is formed on the GaN drift layer 37. At the same time, the transferred substrate 38 also has a metallic interlayer 381 disposed on the surface of the transferred substrate 38. The transferred substrate 18 may include Si, GaAs, Al.sub.2O.sub.3 or Ga.sub.2O.sub.3. The above material for forming the transferred substrate 38 is not easy to combine with the GaN drift layer 37. Therefore, the metallic interlayer 381 is used as the buffer layer for combining the transferred substrate 38 and the GaN drift layer 37.

(44) In FIG. 3H, the manufacturing process removes a semiconductor stack, the semiconductor stack includes the nucleation layer 32 and the thick GaN substrate layer 31. Since the transferred substrate 38 is disposed on the GaN drift layer 37, the transferred substrate 38 is regarded as the main substrate of the semiconductor device. In the present step, the semiconductor stacked is removed to expose the AlGaN barrier layer 33. The semiconductor stack may be removed by mechanical thinning, chemical etching, photoelectrochemical etching or laser lift-off.

(45) The semiconductor stack includes the thick GaN substrate layer 31 and the nucleation layer 32. Since the semiconductor stack is removed, the thick GaN substrate layer 31 can be recycled and used at different manufacturing processes. The manufacturing cost can be reduced by saving the substrate material.

(46) In FIG. 3I, the manufacturing process forms source contacts 391 through the AlGaN barrier layer 33, the source contacts 391 contact the GaN channel layer 34. In the previous process, the semiconductor stack is removed. The remained semiconductor device can be flipped over. That is, the transferred substrate 38 is on the bottom and the AlGaN barrier layer 33 is on the top. The transferred substrate 38 has a rear surface 382 and the AlGaN barrier layer 33 has a tops surface 331. The AlGaN barrier layer 33 can be etched from the tops surface 331 to form the voids. The source contacts 391 are formed by filling up the voids with the conductive material, for example, the material can be copper. The source contacts 391 may pass through the AlGaN barrier layer 33 and contact the GaN channel layer 34. In some embodiments, the source contacts 391 may pass through the GaN channel layer 34 with predetermined depth.

(47) In FIG. 3J, the manufacturing process forms a gate contact 392 on the AlGaN barrier layer 33 and forms a drain contact 393 on the transferred substrate 38. After forming the source contacts 391, the gate contact 392 is formed on the top surface 331 of the AlGaN barrier layer 33 and the drain contact 393 is formed on the rear surface 382 of the transferred substrate 38. In the present embodiment, the drawing only shows the single gate contact structure and single drain contact structure. However, the present disclosure is not limited to the single contact structure. In other embodiment, the gate contact 392 and the drain contact 393 can be plural. The gate contact 392 is disposed at the location corresponding to the GaN buffer layer 361. The drain contact 393 may be overlapped to the leakage current stop layer 35 and the current blocking layer 361. Based on the leakage current stop layer 35 and the current blocking layer 361, the current leakage path from the source contacts 391 to the drain contact 393 can be blocked. The parasitic leakage current penetrating the current blocking layer 361 can be avoided, so as to form the high speed power current aperture vertical electron transistor (CAVET) with excellent reliability.

(48) The present disclosure disclosed herein has been described by means of specific embodiments. However, numerous modifications, variations and enhancements can be made thereto without departing from the spirit and scope of the disclosure set forth in the claims.