Power semiconductor device and a method for producing a power semiconductor device

Abstract

A power semiconductor device and method for production thereof is specified involving an electrode, a base layer of a first conductivity type provided on the electrode, at least one contact layer provided on the base layer, a gate contact provided on the base layer and on the at least one contact layer, an insulation layer between the gate contact and the base layer and between the at least one contact layer and the gate contact, and at least one zone of a second conductivity type within the base layer, wherein the at least one zone is constructed and arranged to shift away a peak electric field generated in the base layer from the insulation layer between the gate contact and the base layer.

Claims

1. A power semiconductor device comprising: an electrode; a base layer of a first conductivity type provided on the electrode; at least one contact layer provided on the base layer; a gate contact provided on the base layer and on the at least one contact layer; an insulation layer between the gate contact and the base layer and between the at least one contact layer and the gate contact, and at least one zone of a second conductivity type different from the first conductivity type within the base layer, wherein the at least one contact layer is arranged on a top surface of the base layer, facing away from the electrode, wherein the at least one contact layer is a metallic layer, wherein an interface between the metallic layer and the base layer forms a Schottky contact, wherein the at least one zone is embedded within the base layer such that an outer surface of the zone is completely covered by the base layer and such that the at least one zone is completely enclosed by the base layer in a three-dimensional manner, wherein the at least one zone is provided centred in lateral directions with respect to the gate contact and a distance between the at least one zone and the insulation layer is at most 1 m, wherein the at least one zone comprises a peak doping concentration being at least 10.sup.15l/cm.sup.3 and at most 510.sup.17l/cm.sup.3, and wherein the at least one zone shifts away a peak electric field generated in the base layer from the insulation layer between the gate contact and the base layer.

2. The power semiconductor device according to claim 1, wherein the base layer comprises a plain top surface and the at least one metallic layer does not extend into the base layer in vertical direction, or the base layer comprises at least one recessed top surface and the at least one contact layer is provided on the at least one recessed top surface.

3. The power semiconductor device according to claim 1, wherein at least one of the gate contact and the insulation layer partially overlaps with the at least one contact layer in lateral directions.

4. The power semiconductor device according to claim 1, wherein an overlap of the at least one of the gate contact and the insulation layer in lateral directions with the at least one contact layer is at least 0.001 m and at most 3 m.

5. The power semiconductor device according to claim 1, wherein the at least one zone has a main extension direction in lateral directions transverse to a main extension direction of the base layer in lateral directions.

6. The power semiconductor device according to claim 5, wherein the at least one zone has a length in lateral directions being equal to a length of the at least one contact layer.

7. The power semiconductor device according to claim 1, wherein the at least one zone comprises a peak doping concentration being one to hundred times higher than a peak doping concentration of the base layer.

8. The power semiconductor device according to claim 1, wherein a thickness of the at least one zone is at least 0.1 m and at most 1 m.

9. The power semiconductor device according to claim 1, wherein the at least one zone has a width in lateral directions along a main extension direction of the base layer, which is less than 40% of a length of the gate contact in lateral directions along the main extension direction of the base layer.

10. A method for producing a power semiconductor device comprising: providing an electrode; providing a base layer of a first conductivity type on the electrode; applying at least one contact layer on the base layer; applying a gate contact and an insulation layer on the base layer and at least one contact layer, wherein the insulation layer is applied between the gate contact and the base layer and between the at least one contact layer and the gate contact, and generating at least one zone of a second conductivity type within the base layer, wherein the at least one contact layer is arranged on a top surface of the base layer, facing away from the electrode, wherein the at least one contact layer is a metallic layer, wherein an interface between the metallic layer and the base layer forms a Schottky contact, wherein the at least one zone is embedded within the base layer such that an outer surface of the zone is completely covered by the base layer and such that the at least one zone is completely enclosed by the base layer in a three-dimensional manner, wherein the at least one zone is provided centred in lateral directions with respect to the gate contact and a distance between the at least one zone and the insulation layer is at most 1 m, wherein the at least one zone comprises a peak doping concentration being at least 10.sup.15l/cm.sup.3 and at most 510.sup.17l/cm.sup.3, and the at least one zone shifts away a peak electric field generated in the base layer from the insulation layer between the gate contact and the base layer.

Description

(1) The subject matter of the invention will be explained in more detail in the following with reference to exemplary embodiments which are illustrated in the attached drawings.

(2) FIGS. 1 and 2 schematically show sectional views of a MOSFET according to the prior art.

(3) FIG. 3 schematically shows a current-voltage characteristic of a current for different gate voltages of a MOSFET according to the prior art.

(4) FIG. 4 schematically shows a current-voltage characteristic of a current for different voltages of a MOSFET according to the prior art.

(5) FIG. 5 schematically shows a sectional view of a power semiconductor device according to an embodiment.

(6) FIG. 6 schematically shows a doping profile of a MOSFET according to the prior art.

(7) FIGS. 7 and 8 schematically shows a doping profile of a power semiconductor device according to an embodiment.

(8) FIG. 9 schematically shows an electrical field profile of a MOSFET according to the prior art.

(9) FIGS. 10 and 11 schematically shows an electrical field profile of a power semiconductor device according to an embodiment.

(10) FIG. 12 schematically shows an electrical current density profile of a MOSFET according to the prior art.

(11) FIGS. 13 and 14 schematically shows an electrical current density profile of a power semiconductor device according to an embodiment.

(12) FIGS. 15 and 16 schematically show sectional views of a power semiconductor device according to an embodiment.

(13) FIGS. 17 and 18 schematically show sectional views of a power semiconductor device according to an embodiment.

(14) FIGS. 19 and 20 schematically show sectional views of a power semiconductor device according to an embodiment.

(15) FIGS. 21 and 22 schematically show sectional views of a power semiconductor device according to an embodiment.

(16) FIG. 23 shows a flow diagram of a method for producing power semiconductor device according to an embodiment.

(17) The reference symbols used in the drawings, and their meanings, are listed in summary form in the list of reference symbols. In principle, identical parts are provided with the same reference symbols in the figures.

(18) The MOSFET according to the prior art in FIG. 1 comprises an electrode 2, a base layer 3 being arranged on the electrode 2, two contact layers 4 being arranged on the base layer 3, a gate contact 5 being arranged on the base layer 3, and an insulation layer 6 between the gate contact 5 and the base layer 3.

(19) According to FIG. 2 a cross-section P, marked in FIG. 1, through the contact layers 4 and the base layer 3 is shown. Further, a main extension direction of the base layer L3 in lateral directions is depicted in FIG. 2.

(20) The current-voltage characteristic of FIG. 3 shows a drain current Id for different gate voltages Vg of the MOSFET according to the prior art according to FIGS. 1 and 2.

(21) The current-voltage characteristic of FIG. 5 shows a drain current Id for different drain voltages Vd of the MOSFET according to the prior art according to FIGS. 1 and 2.

(22) The power semiconductor device 1 according to the embodiment of FIG. 5 comprises an electrode 2 on which a base layer 3 of a first conductivity type is provided. A top surface of the base layer 3 is plain. On this plain top surface of the base layer 3, two contact layers 4, each being a metallic layer, are arranged. In a side view of the power semiconductor device 1, the metallic layers and the base layer 3 do not overlap with one another.

(23) In addition, a gate contact 5 is provided on the base layer 3 and on the metallic layers. The gate contact 5 is enclosed by an insulation layer 6, except the region for externally contacting. The insulation layer 6 is arranged between the gate contact 5 and the base layer 3 as well as between the at least two metallic layers and the gate contact 5.

(24) The gate contact 5 and the insulation layer 6 partially overlap in lateral directions with the metallic layers. An overlap of the gate contact 5 and the insulation layer 6 with each of the metallic layers is, for example, is at least 0.2 m and at most 2 m. Furthermore, a side surface of each of the metallic layers are completely covered by the insulation layer 6.

(25) Moreover, a zone 7 of a second conductivity type is located within the base layer 3. In this sectional view an outer surface of the zone 7 is completely covered by the base layer 3 such that the zone 7 is completely enclosed by the base layer 3 in two dimensions. Further, the zone 7 is provided centred in lateral directions with respect to the gate contact 5. For example, a distance between the zone 7 and the insulation layer 6 is at most 1 m.

(26) For example, the base layer 3 of the first conductivity type comprises n-type dopants. In this case, the zone 7 of a second conductivity type comprises p-type dopants. Due to such an arrangement of the zone 7 of the second conductivity type, a peak electric field generated in the base layer 3 is shifted away from the insulation layer 6 between the gate contact 5 and the base layer 3.

(27) A simulation a doping profile according to FIG. 6 corresponds to a MOSFET according to FIGS. 1 and 2 without having a zone 7 of the second conductivity type.

(28) Simulations of doping profiles of the FIGS. 7 and 8 correspond to a power semiconductor device 1 with a zone 7 of a second conductivity type according to the embodiment of FIG. 5. In this cross sectional views, a doping concentration is represented by shaded areas. Here, shaded areas with a comparatively high density of lines corresponds to a comparatively high doping concentration. Consequently, shaded areas with a comparatively low density of lines corresponds to a comparatively low doping concentration. For example, the zone 7 of the second conductivity comprises a peak doping concentration being at least 10.sup.15l/cm.sup.3 and at most 510.sup.17 l/cm.sup.3 corresponding to the shaded area with the highest density of lines.

(29) A simulation of an electric field profile according to FIG. 9 is based on the simulated doping profile according to FIG. 6. Here, an absolute value of an electric field in V/cm is about 1.710.sup.6 V/cm directly below the gate contact 5 in a first region. An electric field of a second region, adjacent to the first region, is about 1.610.sup.6 V/cm.

(30) The simulations of an electric field profile according to FIGS. 10 and 11 are based on the doping profiles of FIGS. 7 and 8, respectively. An absolute value of an electric field directly below the gate contact 5 in a first region is reduced with respect to FIG. 9 to about 410.sup.5 V/cm and in a second region to about 110.sup.6 V/cm.

(31) A simulation of an electric current density according to FIG. 12 is based on the simulated doping profile according to FIG. 6. The simulations of the electric current density according to FIGS. 13 and 14 are based on the doping profiles of FIGS. 7 and 8, respectively. The electric current density below directly below the gate contact 5 in a first region is less for the power semiconductor device 1 according to FIGS. 13 and 14. Here, a density of lines of shown shaded areas correspond to a value of the electric current density.

(32) The base body of the power semiconductor device 1 according to the embodiment of FIGS. 15 and 16 comprise in contrast to the embodiment in connection with FIG. 5 a bar structure. The bar structure and the base body are formed in one piece. Due to the bar structure, the base body comprises two recessed top surfaces. On each of the two recessed top surfaces one contact layer 4 is arranged.

(33) Furthermore, between the electrode 2 and the base layer 3, an injecting layer 8 of the second conductivity type is arranged. In this exemplary embodiment, the power semiconductor device 1 is an IGBT.

(34) According to FIG. 16, showing a schematic top view on the power semiconductor device 1, the zone 7 has a main extension direction L7 in lateral directions being perpendicular to a main extension direction of the base layer L3. Furthermore, the zone 7 has a width in lateral directions along the main extension direction of the base layer L3, which is less than 40% of a length of the gate contact 5 in lateral directions along the main extension direction of the base layer L3.

(35) The zone 7 being arranged centred between the two contact layers 4 in lateral directions extend along the main extension direction of the zone L7 over the whole width of the base layer 3 along the main extension direction of the zone L7.

(36) In contrast to the embodiment of FIGS. 15 and 16 the base layer 3 according to FIGS. 17 and 18 comprises three zones 7. The zones 7 are arranged spaced apart from one another. Furthermore, the main extension directions of the zones L7 are running parallel to one another. In this embodiment, the zones 7 are arranged in a common plane. This is to say that each zone 7 has a same minimal distant to the gate contact 5.

(37) In contrast to the embodiment of FIGS. 17 and 18 the three zones 7 according to FIGS. 19 and 20 form a retrograde profile in a cross sectional view perpendicular to lateral directions. The retrograde profile comprises a peak facing away from the gate contact 5. The zone 7 in the middle of the three zones 7 has a minimal distance to the gate contact 5 in vertical direction than the outer two zones 7.

(38) The power semiconductor device 1 according to the embodiment of FIGS. 21 and 22 comprises five zones 7. Each zone 7 does is formed of a square in plan view. In this embodiment, each zone 7 does not extend over the whole width of the base layer 3. Rather, each zones 7 forms a single pocket within the base layer 3 being completely, e.g. three dimensionally, surrounded by the base layer 3. One of the zones 7 is arranged in centred with respect to the gate contact 5 in lateral directions. Four of the five zones 7 are arranged symmetrically around the zone 7 arranged centred. These four zones 7 are arranged on grid points of a rectangular grid, e.g. in a box-like fashion.

(39) In the method step 100, according to FIG. 23, an electrode 2 is provided and, in the method step 200, a base layer 3 of a first conductivity type is provided on the electrode 2.

(40) Subsequently, in a next method step 300 at least two contact layers 4 are applied on the base layer 3. In a next method step 400, a gate contact 5 and an insulation layer 6 are applied on the base layer 3 and at least two contact layers 4, wherein the insulation layer 6 is applied between the gate contact 5 and the base layer 3 and between the at least two contact layers 4 and the gate contact 5

(41) In the method step 500, at least one zone 7 of a second conductivity type is generated within the base layer 3, wherein the at least one zone 7 is constructed and arranged to shift away a peak electric field generated in the base layer 3 from the insulation layer 6 between the gate contact and the base layer 3.

LIST OF REFERENCE SYMBOLS

(42) 1 power semiconductor device 2 electrode 3 base layer 4 contact layer 5 gate contact 6 insulation layer 7 zone 8 injecting layer L3 main extension direction of the base layer L7 main extension direction of the zone 100 . . . 500 method steps