Semiconductor device with vertically stacked GaN complementary FETs

Abstract

This disclosure pertains to a semiconductor device comprising a substrate layer, a buffer layer arranged on the substrate layer, a channel layer arranged on the buffer layer, and a barrier layer forming a two-dimensional electron gas (2DHG) at its interface with the channel layer, a plurality of epitaxial layers arranged on the barrier layer forming a two-dimensional hole gas, a plurality of source terminals, of drain terminals, and a gate terminal arranged over a passivation layer positioned on one of the epitaxial layers, the gate terminal being configured to control electrical conduction in two-dimensional electron gas and in the a two-dimensional hole gas (2DHG).

Claims

1. A semiconductor device comprising: a substrate layer; a buffer layer disposed on the substrate layer; a channel layer disposed on the buffer layer; a barrier layer disposed on the channel layer, the barrier layer forming a two-dimensional electron gas (2DEG) at an interface with the channel layer; a plurality of epitaxial layers disposed on the barrier layer, forming a two-dimensional hole gas (2DHG) at an interface with the barrier layer; at least two source terminals, a first of the at least two source terminals, called first source terminal, being electrically connected to the two-dimensional electron gas (2DEG), and a second of the at least two source terminals, called second source terminal, being electrically connected to the two-dimensional hole gas (2DHG); at least two drain terminals, a first of the at least two drain terminals, called first drain terminal, being electrically connected to the two-dimensional electron gas (2DEG), and a second of the at least two drain terminals, called second drain terminal, being electrically connected to the two-dimensional hole gas (2DHG); and a gate terminal disposed over a passivation layer of the semiconductor device, the passivation layer being positioned over one of the epitaxial layers, wherein the gate terminal is configured to control electrical conduction in the two-dimensional electron gas (2DEG) and in the two-dimensional hole gas (2DHG).

2. The semiconductor device according to claim 1, wherein one of the epitaxial layers comprises unintentionally doped gallium nitride, UID-GaN.

3. The semiconductor device according to claim 1, wherein one of the epitaxial layers comprises p-type doped gallium nitride, p-GaN.

4. The semiconductor device according to claim 1, wherein one of the epitaxial layers comprises p++-doped gallium nitride, p++-GaN.

5. The semiconductor device according to claim 1, wherein the barrier layer is a III-N barrier layer.

6. The semiconductor device according to claim 1, wherein the barrier layer comprises aluminum gallium nitride, AlGaN.

7. The semiconductor device according to claim 1, wherein the first source terminal and the first drain terminal are disposed on a first plane extending substantially along the channel layer, and wherein the second source terminal and the second drain terminal are disposed on a second plane distinct from the first plane and extending substantially along one of the epitaxial layers.

8. The semiconductor device according to claim 7, wherein the first drain and first source terminals are positioned on a common horizontal plane, whereas the second drain and second source terminals are situated on a separate horizontal plane, with the two planes distinctly separated.

9. The semiconductor device according to claim 7, wherein the first drain terminal and the first source terminal are disposed on a first plane, and wherein the second drain terminal and the second source terminal are disposed on a second plane distinct from the first plane.

10. The semiconductor device according to claim 1, wherein the gate terminal is disposed over the passivation layer, the passivation layer being positioned between the gate terminal and one of the epitaxial layers.

11. The semiconductor device according to claim 1, wherein the first source terminal and the first drain terminal are ohmic to electrons, and wherein the second source terminal and the second drain terminal are ohmic to holes.

12. The semiconductor device according to claim 1, wherein the gate terminal consists of a single gate terminal, the single gate terminal encapsulating a plurality of fins of the semiconductor device, each fin extending into the channel layer, the plurality of fins including a first set of fins extending into a region of the formed two-dimensional electron gas (2DEG), the plurality of fins further including a second set of fins extending into a region of the formed two-dimensional hole gas (2DHG), the first set of fins and the second set of fins being disposed transversely to each other.

13. The semiconductor device according to claim 12, wherein the gate terminal extends over and along at least three sides of each fin of the plurality of fins, the plurality of fins including a first set of fins extending into a region of the formed two-dimensional electron gas (2DEG) and a second set of fins extending into a region of the formed two-dimensional hole gas (2DHG), the passivation layer being positioned between the gate terminal and the plurality of fins.

14. The semiconductor device according to claim 12, wherein the first set of fins defines a first Field Effect Transistor, called first FET, and the second set of fins defines a second Field Effect Transistor, called second FET, the number and the pitch of the fins of the first FET and the number and the pitch of the fins of the second FET being selected according to the proportionality equations: $\frac{W_n}{L_n}\frac{n_{n-\mathrm{fin}}{W}_{n-\mathrm{fin}}}{n_{p-\mathrm{fin}}{W}_{p-\mathrm{fin}}},\mathrm{and}$ $\frac{W_p}{L_p}\frac{n_{p-\mathrm{fin}}{W}_{p-\mathrm{fin}}}{n_{n-\mathrm{fin}}{W}_{n-\mathrm{fin}}},$ W.sub.n and W.sub.p denoting the effective channel widths of the first FET and the second FET, respectively, L.sub.n and L.sub.p denoting the effective channel lengths of the first FET and the second FET, respectively, n.sub.n-fin and n.sub.p-fin denoting the respective numbers of fins of the first FET and the second FET, W.sub.n-fin and W.sub.p-fin denoting the respective fin widths of the first FET and the second FET.

15. A method of manufacturing a semiconductor device, the method comprising: forming a buffer layer on a substrate; forming a channel layer on the buffer layer; forming a barrier layer on the channel layer, a two-dimensional electron gas (2DEG) being induced at an interface between the channel layer and the barrier layer; forming a plurality of epitaxial layers on the barrier layer, a two-dimensional hole gas (2DHG) being induced at an interface between the barrier layer and at least one of the epitaxial layers; forming a passivation layer over one of the epitaxial layers; forming a gate terminal over the passivation layer, the gate terminal being configured to control electrical conduction in both the two-dimensional electron gas (2DEG) and the two-dimensional hole gas (2DHG); forming at least two source terminals, a first of the at least two source terminals, called first source terminal, being electrically connected to the two-dimensional electron gas (2DEG), and a second of the at least two source terminals, called second source terminal, being electrically connected to the two-dimensional hole gas (2DHG); and forming at least two drain terminals, wherein a first of the at least two drain terminals, called first drain terminal, is electrically connected to the two-dimensional electron gas (2DEG), and wherein a second of the at least two drain terminals, called second drain terminal, is electrically connected to the two-dimensional hole gas (2DHG).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other features, embodiments, definitions and advantages will become apparent upon reading the detailed description below and analyzing the attached drawings, including the following figures.

(2) FIG. 1 is a schematic illustrating a three-dimensional view of a semiconductor device, according to an embodiment of the disclosure.

(3) FIG. 2 is a schematic illustrating a cross-section view along an AA axis of FIG. 1 according to an embodiment of the present disclosure.

(4) FIG. 3 is a schematic illustrating a cross-section view along a BB axis of FIG. 1 according to an embodiment of the present disclosure.

(5) FIG. 4 is a schematic illustrating a cross-section view along a CC axis of FIG. 1 according to an embodiment of the present disclosure.

(6) FIG. 5 is a schematic illustrating a cross-section view along a DD axis of FIG. 1 according to an embodiment of the present disclosure.

(7) FIG. 6 is a schematic illustrating a view from the top of the device according to an embodiment of the present disclosure.

(8) FIG. 7A is a schematic illustrating a first side view of the device according to an embodiment of the present disclosure.

(9) FIG. 7B is a schematic illustrating a second side view of the device according to an embodiment of the present disclosure.

(10) FIG. 8 is a schematic illustrating an equivalent circuit of the device according to an embodiment of the present disclosure.

(11) The provided figures depict one or more exemplary embodiments. Accordingly, the figures are not intended to limit the scope of the inventions. It will be apparent that apparatuses and methods are shown in block diagram form only in order to avoid obscuring the present disclosure.

(12) Unless otherwise indicated, common or analogous elements in the figures are denoted by the same reference numerals and exhibit identical or analogous features, so that common or analogous elements are generally not described again for the sake of clarity and conciseness.

DESCRIPTION OF THE EMBODIMENTS

(13) FIG. 1 represents a three-dimensional view of a semiconductor device, according to an embodiment of the disclosure.

(14) In particular, a three-dimensional schematic of the semiconductor device 100 is illustrated according to one possible embodiment.

(15) The semiconductor device 100 includes epitaxial layers including a substrate 101, for instance a silicium substrate, and a buffer layer 102 positioned on top of the substrate 101.

(16) In one embodiment, the buffer layer 102 includes one or more nucleation and strain relief layers (not represented).

(17) In one embodiment, the buffer layer 102 comprises aluminum nitride (AlN) and aluminum gallium nitride, noted Al.sub.xGa.sub.1-xN where x is strictly larger than 0 and smaller than 1, such that 0<x1.

(18) A gallium nitride, GaN, channel layer 103 is located or placed during manufacture on top of the buffer layer 102. As illustrated, a barrier layer 104 made of a III-N material is located on top of the GaN channel layer 103.

(19) Advantageously, in one possible embodiment, the vertical thickness of the barrier layer 104 ranges from 5 to 30 nanometers (nm).

(20) In one possible embodiment, the thickness of the GaN channel layer 103 is ten times larger than the thickness of the III-N barrier layer 104, i.e 10 thicker, or 1000% thicker.

(21) In one possible embodiment, the III-N barrier layer 104 comprises aluminum gallium nitride, or AlGaN. In alternatives, the III-N layer comprises Al.sub.xIn.sub.yGa.sub.1-x-yN such that a value of x and y is comprised between 0 and 1, such that 0x1 and 0y1 are fulfilled.

(22) In one possible embodiment, the GaN channel layer 103 includes a band gap and the III-N barrier layer 104 includes a band gap, such that the Ill-N barrier layer band gap is higher than the GaN channel layer band gap.

(23) Advantageously, positioning an aluminum gallium nitride, AlGaN, layer 104 on a GaN layer 103 enables the aluminum gallium nitride layer and the gallium nitride layer to form a junction, said junction being for instance a 2-dimensional electron gas, called 2DEG, channel.

(24) Herein, for the sake of clarity, any formed 2-dimensional electron gas or 2DEG will be denoted by 2DEG in the drawings.

(25) In one embodiment, the semiconductor device 100 includes additional layers, comprising a second doped gallium nitride layer 105 located atop the aluminum gallium nitride layer 104, and called UID GaN layer 105.

(26) In one embodiment, the UID GaN layer 105 is un-intentionally doped.

(27) In one embodiment, the two layers 105 and 104 form a junction that generates a 2-dimensional hole gas, called 2DHG, channel, which defines a local concentration of positively charged holes.

(28) Herein, for the sake of clarity, any formed 2-dimensional hole gas or 2DHG will be denoted by 2DHG in the drawings.

(29) In one embodiment, the semiconductor device 100 further includes a p-doped GaN layer 106, called p-GaN layer 106, positioned on the second GaN layer.

(30) In one embodiment, the semiconductor device 100 further includes a p++-doped GaN layer 107, called p++-GaN layer 107, which is positioned on the p-GaN layer.

(31) In one embodiment, the p++-GaN layer 107 has a relatively stronger p-doping than the p-GaN layer 106, which is for instance achieved by doping p++-GaN layer 107 with magnesium. Advantageously, said doping is obtained with a magnesium concentration which is around 110.sup.19 cm.sup.3, thereby achieving adequate hole concentration due to a high ionization energy of magnesium.

(32) In one embodiment, the semiconductor device 100 comprises a plurality of terminals, for example, a first drain terminal 110, a second drain terminal 112, a first source terminal 111 and a second source terminal 113.

(33) In one embodiment, one or more of the terminals of the semiconductor device 100 comprises fins, said fins being for instance formed by etching the layers down to the GaN channel layer 103.

(34) In one embodiment, the semiconductor device 100 further includes a passivation layer 108, which encapsulates and protects the underlying layers from environmental influences and contamination.

(35) Advantageously, the passivation layer 108 can be positioned over the active regions of the semiconductor device 100 and is adapted to provide electrical isolation while preventing unwanted charge accumulation.

(36) In various embodiments, various materials or combinations of materials are used for passivation and gate oxide over the fins of the terminals of the semiconductor device 100, including but not limited to HfO.sub.2, Al.sub.2O.sub.3, and others.

(37) Advantageously, in one embodiment, the passivation layer 108 comprises a dielectric material, such as silicon nitride (Si.sub.3N.sub.4), hafnium dioxide (HfO.sub.2), or aluminum oxide (Al.sub.2O.sub.3), thereby ensuring stability and reliability in the operation of the semiconductor device 100.

(38) In one embodiment, the gate terminal 109 is positioned over the passivation layer 108, advantageously encapsulating the fins.

(39) In one embodiment, the fins extend perpendicularly with respect to each other, forming a tri-gate architecture that enhances electrostatic control over the channels.

(40) In one embodiment, the semiconductor device 100 comprises a high aspect ratio for the fins, ensuring optimal gate coupling and improved subthreshold slope, thereby enhancing switching performance.

(41) Advantageously, the gate terminal 109 cab be configured to control the conduction of the underlying channels.

(42) In one embodiment, the gate terminal 109 comprises a conductive material such as tungsten (W), titanium nitride (TiN), or polysilicon, ensuring a low resistance gate path.

(43) Advantageously, the placement of the gate terminal 109 over the fins enables an effective electrostatic control of the carrier channels, thereby facilitating enhancement-mode operation of both the n-FET and the p-FET.

(44) In one embodiment, advantageously, the first drain terminal 110 and the first source terminal 111 are ohmic to electrons and serve as contacts for the semiconductor device 100, equivalent to an n-FET.

(45) For instance, in a non-limiting example, the drain terminals 110 and 112 comprise a metal stack including titanium (Ti), aluminum (Al), or nickel (Ni), ensuring low contact resistance and reliable electrical performance.

(46) In various embodiments, the semiconductor device 100 comprises adapted structural parameters for use as a GaN CMOS. The number of fins and the pitch of fins can be adapted accordingly, and subject to design specifications, which can be adjusted as required to meet performance criteria, as discussed hereafter.

(47) In one embodiment, advantageously, the second drain terminal 112 and the second source terminal 113 are ohmic to holes, functioning as contacts for the semiconductor device 100, equivalent to a p-FET.

(48) In one embodiment, the first source terminal 111 and the second source terminal 113 serve as respective contact points for the n-FET and p-FET. The first source terminal 111 is positioned in the same horizontal plane as the first drain terminal 110, ensuring a compact layout for the n-channel device. Similarly, the second source terminal 113 is positioned in a separate horizontal plane along with the second drain terminal 112, forming the conduction path for the p-channel device. In one embodiment, the terminals 111 and 113 are fabricated using a self-aligned process to minimize contact resistance and improve carrier injection efficiency.

(49) In various embodiments, as with the semiconductor device 100 equivalent to an n-FET, the number of fins, pitch of fins, and other structural parameters for the p-FET are adjustable based on design specifications to optimize performance, for instance for use as a GaN CMOS.

(50) FIG. 2 represents a cross-section view along an AA axis of FIG. 1 according to an embodiment of the present disclosure. In the illustrated embodiment, the element 200, 201, 202, 203, 204, 205, 206, 208, 209, and 211, respectively, correspond to the element 100, 101, 102, 103, 104, 105, 106, 108, 109, and 111, respectively. The elements 107, 112 and 113 are not presently visible.

(51) In particular, a cross-section view along an AA axis of a semiconductor device 200 is illustrated according to one possible embodiment.

(52) In this embodiment, the two-dimensional electron gas, 2DEG, is formed at the interface of the barrier layer 204 and of the GaN channel layer 203.

(53) Advantageously, the two-dimensional electron gas 2DEG is enabled thanks to the difference of spontaneous and polarization charge at the interface.

(54) In this embodiment, the UID-GaN layer 205, the p-GaN layer 206 and the p++GaN layer 207 are located above the barrier layer 204. Along with the difference of polarization charges at the interface, the two-dimensional hole gas, 2DHG, is enabled.

(55) In one embodiment, the first drain terminal 210 and the first source terminal 211, as illustrated in this cross-section, are ohmic to electrons.

(56) Advantageously, the conduction path from the first source terminal 211 to the first drain terminal 210 is completed by the two-dimensional electron gas, 2DEG.

(57) Advantageously, under a zero-gate bias, the two-dimensional electron gas, 2DEG, may be depleted due to the combined effect of the fin structure and of the p-GaN layer 206 on top of the barrier layer 204 and of the UID-GaN layer 205. In other words, this enables restoring electrostatically the two-dimensional electron gas, 2DEG, by applying a positive bias to the gate terminal, thereby completing the conduction path and turning on the semiconductor device 200.

(58) In the illustrated embodiment, the cross-section along the AA axis only shows the top portion of the gate 209. The passivation layer 208 under the gate layer is used to reduce the gate leakage current as well as to passivate the surface traps and traps induced due to etching of the p-GaN layer 206.

(59) FIG. 3 represents a cross-section view along a BB axis of FIG. 1 according to an embodiment of the present disclosure.

(60) In the illustrated embodiment, the element 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 312 and 313, respectively, is equivalent to the element 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 112 and 113, respectively.

(61) Specifically, this cross-section view along the BB axis depicts more clearly the fin structure of the n-channel and how to form the illustrated vertical stack of layers.

(62) In one embodiment, the formation of both the p-channel and n-channel fins occurs simultaneously. For instance, the top p++-GaN layer 307 and part of the p-GaN layer 306 region are etched using a self-aligned process, called self-aligned etching step, said step being carried out similarly for fabricating the p-FET. In a subsequent etching step, the p-GaN layer 306, the UID-GaN layer 305, the barrier layer 304, and one or more parts of the GaN channel layer 303 are etched to form the fin.

(63) Advantageously, a single mask can be used to carry out the aforementioned etching steps.

(64) In one embodiment, u and upon completion of the various etching steps, a covering step can be carried out so as to cover the etched, or exposed, regions with the passivation layer 308. Subsequently, a step of depositing the gate terminal 309 can be carried out.

(65) FIG. 4 represents a cross-section view along a CC axis of FIG. 1 according to an embodiment of the present disclosure.

(66) In the illustrated embodiment, the element 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 412 and 413, respectively, is equivalent to the element 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 112 and 113, respectively.

(67) Specifically, this cross-section view along the CC axis depicts more clearly the fin structure of the p-channel, i.e., a fin of the p-FET, shows the conduction path of the p-FET and how the conduction path of the p-FET is enabled through the various layers.

(68) In one embodiment, the epitaxial layers include the p-GaN layer 406 which is slightly etched, as well as the UID-GaN layer 405, in addition to the AlGaN barrier layer 404 and the GaN channel layer 403.

(69) In one embodiment, the second drain terminal 412 and the second source terminal 413 are configured to be ohmic to holes.

(70) As a result, the conduction path from the second source terminal 413 to the second drain terminal 412 is completed via the p++-GaN layer 407, the p-GaN layer 406, and the two-dimensional hole gas represented by 2DHG.

(71) Advantageously, at zero gate bias, the 2DHG channel is depleted due to the fin structure of the semiconductor device 400, considering that the gate terminal 409 is positioned over the passivation layer 408, enclosing the 2DHG channel from three different sides, thereby ensuring enhanced operation when using the semiconductor device.

(72) In this cross-section, only the upper portion of the gate terminal 409 is visible.

(73) Advantageously also, when a negative gate bias is applied, the two-dimensional hole gas represented by 2DHG is restored electrostatically, thereby completing the conduction path between the second source terminal 413 and the second drain terminal 412.

(74) FIG. 5 represents a cross-section view along a DD axis of FIG. 1 according to an embodiment of the present disclosure.

(75) In the illustrated embodiment, the element 500, 501, 502, 503, 504, 505, 506, 508 and 509, respectively, is equivalent to the element 100, 101, 102, 103, 104, 105, 106, 108 and 109, respectively. The p++-GaN layer is not visible, nor are the source and drain terminals.

(76) Specifically, this cross-section view along the DD axis depicts more clearly the fin of the p-FET channels.

(77) In one embodiment, advantageously, the channels may be depleted of holes due to the metal gate enclosing the fins. This further ensures the operation of the semiconductor device 500 in an enhancement mode.

(78) In one embodiment, the number of fins can be selected to further optimize the shape, the dimensions and the functionalities of the semiconductor device 500.

(79) FIG. 6 represents a view from atop of the device according to an embodiment of the present disclosure.

(80) In the illustrated embodiment, the element 600, 610, 611, 612 and 613, respectively, is equivalent to the element 100, 110, 111, 112 and 113, respectively.

(81) Specifically, this view from atop depicts more clearly the fins from the n-FET part and from the p-FET part of the semiconductor device 600.

(82) In one embodiment, the fins 625 of the n-FET part and the finds 615 of p-FET part of the semiconductor device 600 are arranged transversely to one another.

(83) Advantageously, this ensures sufficient space for the placement of contacts, such as the first drain terminal 610, the first source terminal 611, the second drain terminal 612 and/or the second source terminal 613 while also mitigating the effects of non-homogeneous potential distribution across the channels. Such effects can be due to the bias applied to a device opposed to the semiconductor device 600.

(84) In one embodiment, a single gate terminal 609 encapsulates the fins 615 and 625, i.e., the fins of both the n-FET and p-FET.

(85) Advantageously, this eliminates the need for additional interconnecting metal between the gate terminal(s) of the n-FET and p-FET when enabling CMOS operation.

(86) Surprisingly, this arrangement was also shown as significantly reducing the input capacitance and as strongly increasing the speed of operation of the semiconductor device 600.

(87) Advantageously, the n-channel and p-channel are vertically stacked, allowing for the vertical integration of the n-FET and p-FET without the requirement for regrowth or heterogeneous integration. This arrangement reduces area consumption and provides tighter integration, which is highly advantageous in semiconductor device fabrication.

(88) FIG. 7A represents a first side view of the device according to an embodiment of the present disclosure. FIG. 7B represents a second side view of the device according to the same embodiment of the present disclosure.

(89) Specifically, these views from the side of the semiconductor device depicts more clearly the position of the various terminals with respect to the various layers of the semiconductor device.

(90) In one embodiment, for instance, the first drain and source terminals, which are ohmic to electrons, are positioned in the plane(s) 701. The second drain and source terminals, which are ohmic to holes, are located in the plane(s) 702.

(91) FIG. 8 illustrates an equivalent circuit of the device according to an embodiment of the present disclosure.

(92) Specifically, the electronic schematic 801 represents the equivalent circuit representation of the semiconductor device 100 (and 200, 300, 400, 500, 600), which comprises both an n-FET 802 and a p-FET 803, the n-FET 802 and the p-FET 803 being vertically stacked and sharing a common gate terminal 804.

(93) Advantageously, mathematical equations can be established to describe the relations between the physical parameters of the semiconductor device 100 with respect to the equivalent circuit representation defined by the electronic schematic 801, and to control the device. In this equivalent circuit representation, S1 denotes the first source terminal, S2 denotes the second source terminal, D1 denotes the first drain terminal and D2 denotes the second drain terminal. The element 802 designates the n-FET part of the circuit, the element 803 designates the p-FET part of the circuit, while 804 defines its gate terminal, corresponding for instance to the previous element 109.

(94) In one embodiment, the physical parameters of the semiconductor device comprise, among others, the pitch of the fins of the element 802 and/or 803, i.e., W.sub.n and/or W.sub.p, as well as the number of fins of the element 802 and/or 803, i.e., n.sub.n-fin and/or n.sub.p-fin. These physical parameters can specifically be adjusted when designing or manufacturing the semiconductor device.

(95) In one embodiment, the magnitude of the electric drive currents which can be obtained at the level of the n-FET part of the circuit, i.e., I.sub.D,n for 802, and at the level of the p-FET part of the circuit, i.e., I.sub.D,p for 803, can be computed based on the two following mathematical equations eq1 and eq2:

(96) $\begin{array}{cc}{I}_{D,n}{}_n\frac{W_n}{L_n}{}_n\frac{n_{n-\mathrm{fin}}{w}_{n-\mathrm{fin}}}{n_{p-\mathrm{fin}}{w}_{p-\mathrm{fin}}}& \left(\mathrm{eq1}\right)\end{array}$$\begin{array}{cc}{I}_{D,p}{}_p\frac{W_p}{L_p}{}_p\frac{n_{p-\mathrm{fin}}{w}_{p-\mathrm{fin}}}{n_{n-\mathrm{fin}}{w}_{n-\mathrm{fin}}}& \left(\mathrm{eq2}\right)\end{array}$

(97) It is known that the ratio of transconductance parameters of given n-channel transistor and p-channel transistor parts of a GaN CMOS application is typically expressed by the following equation eq3:

(98) $\begin{array}{cc}\frac{{}_n}{{}_p}=\frac{{}_n{C}_{\mathrm{OX}}\left(\frac{W_n}{L_n}\right)}{{}_p{C}_{\mathrm{OX}}\left(\frac{W_p}{L_p}\right)}& \left(\mathrm{eq3}\right)\end{array}$

(99) In this expression, .sub.n and .sub.p correspond to the transconductance parameters of the n-channel and p-channel transistors, respectively, which define the current-driving capability of each device. The term .sub.n represents the electron mobility in the n-channel, while .sub.p represents the hole mobility in the p-channel. The factor C.sub.ox corresponds to the gate oxide capacitance per unit area, which is generally assumed to be similar for transistors obtained by a given fabrication process. The terms W.sub.n/L.sub.n and W.sub.p/L.sub.p denote the width-to-length ratios of the n-FET and p-FET, respectively, which define the geometrical scaling of the devices.

(100) Since the electron mobility .sub.n in GaN devices is significantly higher than the hole mobility .sub.p, the ratio of .sub.n and .sub.p is inherently large, which could lead to an imbalance in the current-driving capabilities of the n-FET and p-FET.

(101) However, the aforementioned embodiments advantageously enable compensating for imbalances and discrepancies in view of achieving matched drive currents, avoiding large device footprint and parasitic capacitances that can negatively impact circuit performance and switching speed. Specifically, when incorporating the semiconductor device of any of the aforementioned embodiments in a GaN CMOS application, it is advantageous to select and/or optimize the previously described physical parameters in view of mitigating imbalances in carrier mobility between electrons and holes.

(102) Advantageously, by appropriately adjusting the fin pitch, the number of fins, and the respective width-to-length ratios of the transistors, imbalances in carrier mobility can be mitigated directly by selecting and/or optimizing the physical parameters in the following mathematical expression:

(103) This, in turn, enables effectively controlling the ratio of .sub.n and .sub.p by adjusting the parameters in the following relationship eq4, providing a broader optimization scope and extending the design flexibility of semiconductor devices.

(104) $\begin{array}{cc}\frac{{}_n}{{}_p}\frac{{}_n}{{}_p}{\left(\frac{n_{n-\mathrm{fin}}}{n_{p-\mathrm{fin}}}\right)}^2{\left(\frac{w_{n-\mathrm{fin}}}{w_{p-\mathrm{fin}}}\right)}^2& \left(\mathrm{eq4}\right)\end{array}$

(105) As used in the specification and claims, the terms for example, for instance, and such as, and the verbs comprising, having, including, and their other verb forms, when used in conjunction with a listing of one or more components or other items, are each to be construed as open ended, meaning that the listing is not be considered as excluding others, additional components or items. The term based on means at least partially based on. Further, it is to be understood that the phraseology and terminology employed herein are for the purpose of any description and should not be regarded as limiting.

(106) Although the present disclosure and the embodiments described therein have been shown and described with reference to specific preferred embodiments, this is not to be construed as limiting the invention itself. Various changes may be made in form and details without departing from the scope of the invention as defined by the appended claims.

(107) Further aspects of the present invention are defined in the following numbered clauses:

(108) A. A semiconductor device (100; 200; 300; 400; 500; 600), comprising: a substrate layer (101; 201; 301; 401; 501), a buffer layer (102; 202; 302; 402; 502) arranged on the substrate layer (101; 201; 301; 401; 501), a channel layer (103; 203; 303; 403; 503) arranged on the buffer layer (102; 202; 302; 402; 502), a barrier layer (104; 204; 304; 404; 504) arranged on the channel layer (103; 203; 303; 403; 503; 603), the barrier layer (104; 204; 304; 404; 504; 604) forming a two-dimensional electron gas (2DEG), at an interface with the channel layer (103; 203; 303; 403; 503; 603), a plurality of epitaxial layers (105, 106, 107; 205, 206, 207; 305, 306, 307; 405, 406, 407; 505, 507) arranged on the barrier layer (104; 204; 304; 404; 504), forming a two-dimensional hole gas (2DHG), at an interface with the barrier layer (104; 204; 304; 404; 504; 604), at least two source terminals (111, 113; 211; 313; 413; 611, 613), a first of the at least two source terminal (111, 113; 211; 313; 407; 611, 613), called first source terminal (111; 211; 611), being electrically connected to the two-dimensional electron gas (2DEG), and a second of the at least two source terminal (111, 113; 211; 313; 407; 611, 613), called second source terminal (113; 313; 413; 613), being electrically connected to the two-dimensional hole gas (2DHG), at least two drain terminals (110, 112; 210; 312; 412; 610, 612), a first of the at least two drain terminals (110, 112; 210; 312; 412; 610, 612), called first drain terminal (110; 210; 610) being electrically connected to the two-dimensional electron gas (2DEG), and a second of the at least two drain terminals (110, 112; 210; 312; 412; 610, 612), called second drain terminal (112; 312; 412; 612) being electrically connected to the two-dimensional hole gas (2DHG), and a gate terminal (109; 209; 309; 409; 509; 609) arranged over a passivation layer (108; 208; 308; 408; 508; 608) of the semiconductor device (100; 200; 300; 400; 500; 600), the passivation layer (108; 208; 308; 408; 508; 608) being positioned over one of the epitaxial layers (105, 106, 107; 205, 206, 207; 305, 306, 307; 405, 406, 407; 505, 507), the gate terminal (109; 209; 309; 409; 509; 609) being configured to control electrical conduction in the two-dimensional electron gas (2DEG) and in the two-dimensional hole gas (2DHG).

(109) B. The semiconductor device (100; 200; 300; 400; 500; 600) according to clause A, wherein one of the epitaxial layers (105; 205; 305; 405; 505; 605) comprises unintentionally doped gallium nitride, UID-GaN.

(110) C. The semiconductor device (100; 200; 300; 400; 500; 600) according to clause A or B, wherein one of the epitaxial layers (106; 206; 306; 406; 506; 606) comprises p-type doped gallium nitride, p-GaN.

(111) D. The semiconductor device (100; 200; 300; 400; 500; 600) according to any of the preceding clauses, wherein one of the epitaxial layers (107; 207; 307; 407; 507; 607) comprises p++-doped gallium nitride, p++-GaN.

(112) E. The semiconductor device (100; 200; 300; 400; 500; 600) according to any of the preceding clauses, wherein the barrier layer (104; 204; 304; 404; 504; 604) is a III-N barrier layer.

(113) F. The semiconductor device (100; 200; 300; 400; 500; 600) according to any of the preceding clauses, wherein the barrier layer (104; 204; 304; 404; 504; 604) comprises aluminum gallium nitride, AlGaN,

(114) G. The semiconductor device (100; 200; 300; 400; 500; 600) according to any of the preceding clauses, wherein the first source terminal (111; 211; 311; 411; 611) and the first drain terminal (110; 210; 310; 410; 610) are arranged on a first plane extending substantially along the channel layer (103; 203; 303; 403; 503), and wherein the second source terminal (113; 213; 313; 413; 613) and the second drain terminal (112; 212; 312; 412; 612) are arranged on a second plane distinct from the first plane and extending substantially along one of the epitaxial layers (105, 106, 107; 205, 206, 207; 305, 306, 307; 405, 406, 407; 505, 507).

(115) H. The semiconductor device (100; 200; 300; 400; 500; 600) according to clause G, wherein the first drain and first source terminals are positioned on a common horizontal plane, whereas the second drain and second source terminals are situated on a separate horizontal plane, with the two planes distinctly separated.

(116) I. The semiconductor device (100; 200; 300; 400; 500; 600) according to clause G, wherein the first drain terminal (110; 210; 610) and the first source terminal (111; 211; 611) are arranged on a first plane, and wherein the second drain terminal (112; 312; 412; 612) and the second source terminal (113; 313; 413; 613) are arranged on a second plane distinct from the first plane.

(117) J. The semiconductor device (100; 200; 300; 400; 500; 600) according to any of the preceding clauses, wherein the gate terminal (109; 209; 309; 409; 509; 609) is arranged over the passivation layer (108; 208; 308; 408; 508; 608), the passivation layer (108; 208; 308; 408; 508; 608) being positioned between the gate terminal (109; 209; 309; 409; 509; 609) and one of the epitaxial layers (105, 106, 107; 205, 206, 207; 305, 306, 307; 405, 406, 407; 505, 507).

(118) K. The semiconductor device (100; 200; 300; 400; 500; 600) according to any of the preceding clauses, wherein the first source terminal (111; 211; 611) and the first drain terminal (110; 210; 610) are ohmic to electrons, and wherein the second source terminal (113; 313; 413; 613) and the second drain terminal (112; 312; 412; 612) are ohmic to holes.

(119) L. The semiconductor device (100; 200; 300; 400; 500; 600) according to any of the preceding clauses, wherein the gate terminal (109; 209; 309; 409; 509; 609) comprises a single gate terminal (109; 209; 309; 409; 509; 609), the single gate terminal (109; 209; 309; 409; 509; 609) encapsulating a plurality of fins of the semiconductor device (100; 200; 300; 400; 500; 600), each fin extending into the channel layer (103; 203; 303; 403; 503; 603), the plurality of fins including a first set of fins extending into a region of the formed two-dimensional electron gas (2DEG), the plurality of fins further including a second set of fins extending into a region of the formed two-dimensional hole gas (2DHG), the first set of fins and the second set of fins being arranged transversely to each other.

(120) M. The semiconductor device (100; 200; 300; 400; 500; 600) according to clause L, wherein the gate terminal (109; 209; 309; 409; 509; 609) extends over and along at least three sides of each fin of the plurality of fins, the plurality of fins including a first set of fins extending into a region of the formed two-dimensional electron gas (2DEG) and a second set of fins extending into a region of the formed two-dimensional hole gas (2DHG), the passivation layer (108; 208; 308; 408; 508; 608) being positioned between the gate terminal (109; 209; 309; 409; 509; 609) and the plurality of fins.

(121) N. The semiconductor device (100; 200; 300; 400; 500; 600) according to clause L, wherein the first set of fins defines a first Field Effect Transistor, called first FET, and the second set of fins defines a second Field Effect Transistor, called second FET, the number and the pitch of the fins of the first FET and the number and the pitch of the fins of the second FET being selected according to the proportionality equations

(122) $\frac{W_n}{L_n}\frac{n_{n-\mathrm{fin}}{W}_{n-\mathrm{fin}}}{n_{p-\mathrm{fin}}{W}_{p-\mathrm{fin}}},\mathrm{and}$$\frac{W_p}{L_p}\frac{n_{p-\mathrm{fin}}{W}_{p-\mathrm{fin}}}{n_{n-\mathrm{fin}}{W}_{n-\mathrm{fin}}},$

(123) W.sub.n and W.sub.p denoting the effective channel widths of the first FET and the second FET, respectively, L.sub.n and L.sub.p denoting the effective channel lengths of the first FET and the second FET, respectively, n.sub.n-fin and n.sub.p-fin denoting the respective numbers of fins of the first FET and the second FET, W.sub.n-fin and W.sub.p-fin denoting the respective fin widths of the first FET and the second FET.

(124) O. A method of manufacturing a semiconductor device (100; 200; 300; 400; 500; 600), comprising the steps of: forming a buffer layer (102; 202; 302; 402; 502) on a substrate (101; 201; 301; 401; 501), forming a channel layer (103; 203; 303; 403; 503) on the buffer layer (102; 202; 302; 402; 502), forming a barrier layer (104; 204; 304; 404; 504) on the channel layer (103; 203; 303; 403; 503), a two-dimensional electron gas (2DEG) being induced at an interface between the channel layer (103; 203; 303; 403; 503) and the barrier layer (104; 204; 304; 404; 504), forming a plurality of epitaxial layers (105, 106, 107; 205, 206, 207; 305, 306, 307; 405, 406, 407; 505, 507) on the barrier layer (104; 204; 304; 404; 504), a two-dimensional hole gas (2DHG) being induced at an interface between the barrier layer (104; 204; 304; 404; 504) and at least one of the epitaxial layers 105, 106, 107; 205, 206, 207; 305, 306, 307; 405, 406, 407; 505, 507), forming a passivation layer (108; 208; 308; 408; 508; 608) over one of the epitaxial layers (105, 106, 107; 205, 206, 207; 305, 306, 307; 405, 406, 407; 505, 507), forming a gate terminal (109; 209; 309; 409; 509; 609) over the passivation layer (108; 208; 308; 408; 508; 608), the gate terminal (109; 209; 309; 409; 509; 609) being configured to control electrical conduction in both the two-dimensional electron gas (2DEG) and the two-dimensional hole gas (2DHG), forming at least two source terminals (111, 113; 211; 313; 413; 611, 613), a first of the at least two source terminals (111, 113; 211; 313; 413; 611, 613), called first source terminal (111; 211; 611), being electrically connected to the two-dimensional electron gas (2DEG), and a second of the at least two source terminals (111, 113; 211; 313; 413; 611, 613), called second source terminal (113; 313; 413; 613), being electrically connected to the two-dimensional hole gas (2DHG), and forming at least two drain terminals (110, 112; 210; 312; 412; 610, 612), a first of the at least two drain terminals (110, 112; 210; 312; 412; 610, 612), called first drain terminal (110; 210; 610), being electrically connected to the two-dimensional electron gas (2DEG), and a second of the at least two drain terminals (110, 112; 210; 312; 412; 610, 612), called second drain terminal (112; 312; 412; 612), being electrically connected to the two-dimensional hole gas (2DHG).