POWER SEMICONDUCTOR DEVICE WITH AN AUXILIARY GATE STRUCTURE

Abstract

A heterojunction device having at least three terminals, the at least three terminals comprising a high voltage terminal, a low voltage terminal and a control terminal. The heterojunction device further comprises at least one main power heterojunction transistor, an auxiliary gate circuit comprising at least one first low-voltage heterojunction transistor, a pull-down circuit comprising a capacitor and a charging path for the capacitor. The heterojunction device further comprises at least one monolithically integrated component, wherein the capacitor is configured to provide an internal rail voltage for the at least one monolithically integrated component.

Claims

1. A heterojunction device comprising a high voltage terminal, a low voltage terminal, a control terminal, wherein the heterojunction device further comprises; at least one main power heterojunction transistor, wherein the at least one main power heterojunction transistor comprises a gate terminal, a source terminal and a drain terminal, an auxiliary gate circuit comprising at least one low-voltage heterojunction transistor; at least one Miller clamp transistor, wherein a drain terminal of the Miller clamp transistor is operatively connected to the gate terminal of the at least one main power heterojunction transistor, and wherein the at least one Miller clamp transistor is configured to pull-down the gate terminal at least one main power heterojunction transistor; and an internal rail voltage generation circuit operatively connected to the auxiliary gate circuit, the control terminal, and to the low voltage terminal; and wherein the internal rail voltage generation circuit comprises a capacitor with a charging path from the control terminal, wherein the capacitor is configured to generate an internal rail voltage from the control terminal to drive the at least one Miller clamp transistor.

2. The heterojunction device of claim 1, wherein: the source terminal of the at least one main power heterojunction transistor is operatively connected to the low voltage terminal, the drain terminal of the at least one main power heterojunction transistor is operatively connected to the high voltage terminal, and the gate terminal of the at least one main power heterojunction transistor is operatively connected to the auxiliary gate circuit.

3. The heterojunction device of claim 1, comprising one or more Miller clamp drivers configured to receive the internal rail voltage from the capacitor and drive the at least Miller clamp transistor based on the internal rail voltage.

4. The heterojunction device of claim 3, wherein the one or more Miller clamp drivers is an inverter.

5. The heterojunction device of claim 1, comprising a pull-down circuit, wherein the pull-down circuit comprises: at least one non-linear element, and at least one second enhancement mode heterojunction transistor, wherein the non-linear element comprises a potential divider for driving a gate terminal of the at least one second enhancement mode heterojunction transistor, wherein the potential divider is operatively connected to a gate terminal at least one low-voltage heterojunction transistor.

6. The heterojunction device according to claim 1, wherein a first side of the capacitor is operatively connected to the low voltage terminal, and wherein the internal rail voltage generation circuit comprises an enhancement mode transistor, wherein: a drain terminal of the enhancement mode transistor is operatively connected to the control terminal, a source terminal of the enhancement mode transistor is operatively connected to a second side of the capacitor, and a gate terminal of the enhancement mode transistor is operatively connected to a gate terminal of the at least one low-voltage heterojunction transistor.

7. The heterojunction device according to claim 6, wherein the drain terminal of the enhancement mode transistor is directly connected to the control terminal.

8. The heterojunction device of claim 6, wherein internal rail voltage generation circuit comprises a current source and a diode connected in series, wherein a midpoint between the current source and the diode is connected to the gate terminal of the enhancement mode transistor such that the diode is positioned between the gate terminal of the enhancement mode transistor and the gate terminal of the at least one low-voltage heterojunction transistor.

9. The heterojunction device of claim 8, wherein the current source comprises a depletion mode transistor and a resistor, wherein the resistor is operatively connected between a gate terminal of the depletion mode transistor and a first terminal of the depletion mode transistor.

10. The heterojunction device of claim 9, wherein the current source comprises a second depletion mode transistor connected to a second terminal of the depletion mode transistor, wherein a gate terminal of the second depletion mode transistor is operatively connected to a midpoint between the resistor and the first terminal of the depletion mode transistor.

11. The heterojunction device of claim 10, comprising a further current source operatively connected to the first current source and configured to provide temperature compensation for the at least one non-linear element, wherein the current source and the further current source each comprise a resistor with a different thermal coefficient.

12. The heterojunction device of claim 1, comprising a temperature compensation control circuit operatively connected between the control terminal and a gate terminal of the at least one low-voltage heterojunction transistor, wherein temperature compensation control circuit comprises a first current source and a second current source, each of the first and second current sources comprising a resistor with a different thermal coefficient.

13. The heterojunction device of claim 12, wherein the first and second current sources are connected in series.

14. The heterojunction device of claim 12, wherein the first and second current sources are connected in parallel.

15. The heterojunction device of claim 1, wherein the at least one main power heterojunction transistor, at least one low-voltage heterojunction transistor and at least one Miller clamp transistor each comprise a plurality of sub-transistors, wherein: the respective drain and source terminals of the sub-main power heterojunction transistors are respectively connected to form the drain terminal and source terminal of the at least one main power heterojunction transistor; and the gate terminal of each of the sub-main power heterojunction transistors is operatively connected to a sub-low-voltage heterojunction transistor of a respective sub-auxiliary gate circuit and to a drain terminal of a respective sub-Miller clamp transistor.

16. The heterojunction device of claim 15, comprising a single pull-down circuit common to all sub-main power heterojunction transistors, wherein the pull-down circuit comprises: at least one non-linear element, and at least one second enhancement mode heterojunction transistor, wherein the non-linear element comprises a potential divider for driving a gate terminal of the at least one second enhancement mode heterojunction transistor, and wherein the potential divider is operatively connected to a gate terminal each of the sub-low-voltage heterojunction transistors.

17. The heterojunction device of claim 15, comprising a plurality of pull-down circuits, each pull-down circuit operatively connected to one of the sub-main power heterojunction transistors, wherein each pull-down circuit comprises: at least one non-linear element, and at least one second enhancement mode heterojunction transistor, wherein the non-linear element comprises a potential divider for driving a gate terminal of the at least one second enhancement mode heterojunction transistor, and wherein the potential divider is operatively connected to a gate terminal a sub-low-voltage heterojunction transistor.

18. A heterojunction device comprising: a plurality of main power heterojunction transistors, wherein each main power heterojunction transistor comprises a gate terminal, a source terminal and a drain terminal; a plurality of auxiliary gate circuit comprising at least one low-voltage heterojunction transistor operatively connected to the gate terminal of a corresponding one the plurality of main power heterojunction transistors; and a plurality of Miller clamp transistors, wherein a drain terminal of each of the plurality of Miller clamp transistors is operatively connected to the gate terminal of a corresponding one the plurality of main power heterojunction transistors, and wherein each Miller clamp transistor is configured to pull-down the gate terminal the corresponding main power heterojunction transistors.

19. The heterojunction device according to claim 18, comprising at least one of: (i) a pull down-circuit, wherein the pull-down circuit comprises: at least one non-linear element, and at least one enhancement mode heterojunction transistor, wherein the non-linear element comprises a potential divider for driving a gate terminal of the at least one enhancement mode heterojunction transistor, and wherein the potential divider is operatively connected to the gate terminals of the plurality of main power heterojunction transistors; and (ii) a Miller clamp driver configured to receive an internal rail voltage and drive the plurality of Miller clamp transistors based on the internal rail voltage.

20. The heterojunction device according to claim 18, comprising at least one of: (i) a plurality of pull down-circuits, wherein each pull-down circuit comprises: at least one non-linear element, and at least one enhancement mode heterojunction transistor, wherein the non-linear element comprises a potential divider for driving a gate terminal of the at least one enhancement mode heterojunction transistor, and wherein the potential divider is operatively connected to the gate terminal of a corresponding one the plurality of main power heterojunction transistors; and (ii) a plurality of Miller clamp drivers, each Miller clamp driver configured to receive an internal rail voltage and drive a corresponding one of the plurality of Miller clamp transistors based on the internal rail voltage.

Description

BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0302] The present disclosure will be understood more fully from the detailed description that follows and from the accompanying drawings, which however, should not be taken to limit the disclosure to the specific embodiments shown, but are for explanation and understanding only.

[0303] FIG. 1 shows schematically the cross section in the active area of a prior art pGaN HEMT;

[0304] FIG. 2 illustrates a schematic representation of a cross section of the active area of the proposed disclosure according to one embodiment of the disclosure;

[0305] FIG. 3 shows a circuit schematic representation of one embodiment of the proposed disclosure as shown in the schematic cross section of FIG. 2;

[0306] FIG. 4A shows a circuit schematic representation of a further embodiment of the proposed disclosure in which a low on-state voltage diode is connected in parallel between the drain and the source of the auxiliary transistor;

[0307] FIG. 4B illustrates a 3D schematic representation of the embodiment of FIG. 4A;

[0308] FIG. 4C shows the cross section of the low voltage diode as used in embodiment of FIG. 4A;

[0309] FIG. 5 shows a circuit schematic representation of a further embodiment of the proposed disclosure in which the drain (gate) terminal and the source terminal of the auxiliary transistor are available as external gate terminals;

[0310] FIG. 6 shows a circuit schematic representation of a further embodiment of the proposed disclosure where a second auxiliary transistor is connected in parallel with a first auxiliary transistor where the drain (gate) terminal of the first low auxiliary transistor is connected to the source terminal of the second auxiliary transistor and the source terminal of the first auxiliary transistor is connected to the drain (gate) terminal of the second auxiliary transistor;

[0311] FIG. 7 shows a circuit schematic representation of a further embodiment of the proposed disclosure where a resistor is added between the drain terminal and gate terminal of the second auxiliary transistor;

[0312] FIG. 8 shows a circuit schematic representation of a further embodiment of the proposed disclosure where an additional resistor is added between the source terminal of the auxiliary transistor (drain terminal of the second auxiliary transistor) and source terminal of the active device;

[0313] FIG. 9 shows a circuit schematic representation of a further embodiment of the proposed disclosure where a third auxiliary transistor is added between the drain terminal and gate terminal of the second auxiliary transistor. The gate terminal of the third auxiliary transistor is connected to the source terminal of the third auxiliary transistor;

[0314] FIG. 10 shows a circuit schematic representation of a further embodiment of the proposed disclosure where a third auxiliary transistor is added between the drain terminal and gate terminal of the second auxiliary transistor. The gate terminal of the third auxiliary transistor is connected to the drain terminal of the third auxiliary transistor;

[0315] FIG. 11 shows a circuit schematic representation of a further embodiment of the proposed disclosure where a voltage limiting circuit is implemented composed of two resistors forming a potential divider and an actively switched low voltage enhancement mode transistor;

[0316] FIG. 12 shows a circuit schematic representation of a further embodiment of the proposed disclosure where a voltage limiting circuit is implemented composed of two resistors forming a potential divider and an actively switched low voltage depletion mode transistor;

[0317] FIG. 13 shows a circuit schematic representation of a further embodiment of the proposed disclosure where an over-current protection circuit is implemented composed of a resistor and an actively switched low voltage enhancement mode transistor;

[0318] FIG. 14 shows a circuit schematic representation of a further embodiment of the proposed disclosure where an over-current protection circuit is implemented composed of a resistor and an actively switched low voltage depletion mode transistor;

[0319] FIG. 15 shows a circuit schematic representation of a further embodiment of the proposed disclosure where an active Miller clamp circuit is implemented composed of a resistor, an actively switched low voltage enhancement mode transistor and an actively switched depletion mode transistor;

[0320] FIG. 16 shows a circuit schematic representation of a further embodiment of the proposed disclosure where an active Miller clamp circuit is implemented composed of a resistor, an actively switched low voltage enhancement mode transistor and an actively switched enhancement mode transistor;

[0321] FIG. 17 illustrates a schematic representation of a cross section of the active area of a proposed depletion mode device in prior art which can be used as an actively switched transistor;

[0322] FIG. 18 illustrates a three dimensional schematic representation of the active area of a proposed depletion mode device with pGaN islands (not found in prior art) which can be used as an actively switched transistor;

[0323] FIG. 19 illustrates a three dimensional schematic representation of the active area of the depletion mode device with pGaN islands shown in FIG. 18 operated in diode mode; and

[0324] FIG. 20 shows the transfer characteristic of the proposed depletion mode device shown in FIG. 18.

[0325] FIG. 21 illustrates a schematic representation of a cross-section of the active area of the proposed disclosure according to another embodiment of the disclosure. In this embodiment, the first additional terminal 16 and the auxiliary gate terminal 15 are not operatively connected.

[0326] FIG. 22 shows a circuit schematic representation of one embodiment of the proposed disclosure as shown in the schematic cross-section of FIG. 21.

[0327] FIG. 23 shows a schematic representation of the second aspect of the one embodiment of the proposed disclosure where the gate terminal of the auxiliary gate block is controlled by a current control block and a pull-down circuit block.

[0328] FIG. 24 shows the relationship between the external gate voltage bias and the active gate voltage.

[0329] FIG. 25 shows a circuit schematic representation of a further embodiment of the proposed disclosure where the current control block consists of a resistive element and the pull-down circuit comprises a HEMT in threshold multiplier configuration.

[0330] FIG. 26 shows a circuit schematic representation of a further embodiment of the proposed disclosure where the current control block comprises a resistive element with resistive and capacitive elements in parallel and where the pull-down circuit comprises a HEMT in threshold multiplier configuration, with additional capacitive elements.

[0331] FIG. 27 shows a circuit schematic representation of a further embodiment of the proposed disclosure where the current control block comprises a normally-on HEMT and a resistive element in series where the gate of the normally-on HEMT is connected to the second terminal of the resistive element; and where the pull-down circuit comprises a HEMT in threshold multiplier configuration. In this embodiment, the auxiliary gate block comprises an enhancement mode low voltage HEMT and a Schottky diode in parallel.

[0332] FIG. 28 shows a circuit schematic representation of a further embodiment of the proposed disclosure where the current control block comprises a normally-on HEMT and a resistive element in series where the gate of the normally-on HEMT is connected to the second terminal of the resistive element; and where the pull-down circuit comprises a HEMT in threshold multiplier configuration.

[0333] FIG. 29 shows a circuit schematic representation of a further embodiment of the proposed disclosure where the auxiliary gate block comprises a second auxiliary transistor connected in parallel with a first auxiliary transistor where the gate terminal of the second auxiliary transistor is connected to the source terminal of the first auxiliary transistor;

[0334] FIG. 30 shows a circuit schematic representation of a further embodiment of the proposed disclosure where the pull-down circuit comprises a HEMT in threshold multiplier configuration. In this embodiment, the voltage divider of the pull-down circuit comprises a temperature compensation circuit comprising a current source in parallel with a resistive element.

[0335] FIG. 31 shows a circuit schematic representation of a further embodiment of the proposed disclosure where the voltage divider of the pull-down circuit is connected to the source terminal of the HEMT of the current control block.

[0336] FIG. 32 shows a schematic representation of one embodiment of the proposed disclosure where the gate terminal of the auxiliary gate block is controlled by a current control block and a pull-down circuit block; and where the Miller clamp HEMT is controlled by a logic inverter. The logic inverter is supplied by the output voltage of an integrated DC/DC voltage regulator. Further, the input of the logic inverter is the output of a VG to Vlogic voltage regulator, limiting the voltage from the first additional terminal to a level that is optimised for the integrated GaN HEMT included in the inverter circuit.

[0337] FIG. 33 shows a circuit schematic representation of a further embodiment of the proposed disclosure where the auxiliary gate block comprises a normally-on HEMT.

[0338] FIG. 34 shows a circuit schematic representation of a further embodiment of the proposed disclosure where the auxiliary gate block comprises a normally-on HEMT and where the auxiliary gate block comprises a second auxiliary transistor connected in parallel with a first auxiliary transistor where the gate terminal of the second auxiliary transistor is connected to the source terminal of the first auxiliary transistor;

[0339] FIG. 35 shows a circuit schematic representation of a further embodiment of the proposed disclosure where the auxiliary gate block comprises a normally-on HEMT and where the auxiliary gate block comprises a second auxiliary normally-on HEMT connected in parallel with a first auxiliary transistor where the gate terminal of the second auxiliary transistor is connected to the first terminal;

[0340] FIG. 36 shows a circuit schematic representation of a further embodiment of the proposed disclosure where the voltage divider of the pull-down circuit is connected to the active gate terminal.

[0341] FIG. 37 shows a circuit schematic representation of a further embodiment of the proposed disclosure where the voltage divider of the pull-down circuit is connected to the active gate terminal and where the voltage divider comprises a series of source-gate connected E-HEMTs.

[0342] FIG. 38 shows a circuit schematic representation of a further embodiment of the proposed disclosure where the voltage divider of the pull-down circuit is connected to the active gate terminal and where the voltage divider comprises a HEMT in a threshold multiplier configuration.

[0343] FIG. 39 shows a circuit schematic representation of a further embodiment of the proposed disclosure where the voltage divider of the pull-down circuit is connected to the first additional terminal and where the voltage divider comprises a HEMT in a threshold multiplier configuration.

[0344] FIG. 40 shows a circuit schematic representation of a further embodiment of the proposed disclosure where the voltage divider of the pull-down circuit is connected to the first additional terminal and where the voltage divider comprises a current source, formed of a normally-on HEMT and a resistor, and a HEMT in a threshold multiplier configuration. In this embodiment, the output of the voltage divider is the gate terminal of the HEMT which is in threshold multiplier configuration.

[0345] FIG. 41 illustrates an interdigitated device layout of a further embodiment of the disclosure incorporating an auxiliary gate structure with the current control block and the pull-down circuit block.

[0346] FIG. 42 illustrates an interdigitated device layout of a further embodiment of the disclosure in which the auxiliary gate with the current control block and the pull-down circuit block and terminal regions are placed below the source pad metal.

[0347] FIG. 43 shows a block diagram of a further embodiment of the proposed disclosure where any of the embodiments of the GaN chip power device according to this disclosure are placed in a half-bridge configuration.

[0348] FIG. 44 shows a block diagram of a further embodiment of the proposed disclosure where any of the embodiments of the GaN chip power device according to this disclosure are placed in a three-phase half-bridge configuration.

[0349] FIG. 45 shows a schematic representation of one embodiment of a shielding and decoupling structure between two structures of the chip. In this embodiment, the decoupling structures consist of 2DEG structures ohmic contacts and connections to metal layers through vias. The metal layer may be shaped similar to the 2DEG.

[0350] FIG. 46 shows a schematic representation of one embodiment of the invention in which the pull-down circuit comprises an additional voltage input from an external terminal.

[0351] FIG. 47 shows a schematic representation of one embodiment of the invention in which the pull-down circuit comprises an additional voltage input stemming from a voltage source on the chip. This voltage source may be the output of a voltage regulator, voltage divider, charge pump or other switched voltage converter.

[0352] FIG. 48 shows a schematic representation of one embodiment of the pull-down circuit comprising a voltage source and capacitor in series with an enhancement HEMT with the gate terminal connected to the source terminal.

[0353] FIG. 49 shows a schematic representation of one embodiment of the pull-down circuit comprising a voltage source and capacitor in series with an enhancement HEMT in a threshold multiplier configuration.

[0354] FIG. 50 shows a block diagram of a voltage regulator connected to the input of the receiving circuit (for example logic inverter) through a decoupling circuit. The decoupling circuit reduces or eliminates the impact of voltage excursions or current spikes from the voltage source to the receiving circuit.

[0355] FIG. 51 shows a schematic circuit of a decoupling circuit comprising a resistive element and a capacitive element.

[0356] FIG. 52 shows a schematic circuit of a decoupling circuit comprising a current source and a capacitive element. The current source comprises a depletion HEMT and a resistive element.

[0357] FIG. 53 shows a schematic circuit of a decoupling circuit comprising a current source and a capacitive element. The current source comprises a depletion HEMT and a resistive element. In this embodiment, an additional HEMT in parallel to the current source allows the adjustment of the current limit.

[0358] FIG. 54 shows a schematic circuit of a decoupling circuit comprising a current source and a capacitive element. The current source comprises a depletion HEMT and a resistive element. In this embodiment, an additional HEMT in parallel to the resistive element allows the adjustment of the current limit.

[0359] FIG. 55 shows a schematic circuit of a decoupling circuit comprising a current source and a capacitive element. The current source comprises a depletion HEMT and a resistive element. In this embodiment, an additional HEMT in parallel to the capacitive element allows sinking the current in case of a current spike. The additional HEMT is turned on by a resistive and capacitive voltage divider on the input side of the decoupling circuit.

[0360] FIG. 56 shows an embodiment of FIG. 55 in which the additional HEMT in parallel with the current source is controlled by having its gate connected to the gate voltage of the active HEMT. In this embodiment, the coupling is strong when the active HEMT is in the on-state, weak when the active HEMT is off.

[0361] FIG. 57 shows a schematic of an embodiment of the current control block with an enhancement HEMT in parallel to the resistive element with the gate connected to a DC voltage level. As the voltage level of the source of the HEMT rises the resistance is increased and the current is reduced.

[0362] FIG. 58 shows a schematic of an embodiment of the current control block with a depletion HEMT in parallel to the resistive element with the gate connected to a DC voltage level. As the voltage level of the source of the HEMT rises the resistance is increased and the current is reduced.

[0363] FIG. 59 shows a schematic representation of one embodiment of a D-HEMT with p-GaN islands arranged in two rows operatively connected to the gate contact. The p-GaN islands form a meander shape between them.

[0364] FIG. 60 shows a schematic representation of one embodiment of a D-HEMT with p-GaN islands arranged in three rows operatively connected to the gate contact. The p-GaN islands form a labyrinth shape between them.

[0365] FIG. 61 shows a logic inverter circuit with an enhancement transistor on the low side and a resistive element as a pull-up circuit.

[0366] FIG. 62 shows a logic inverter circuit with an enhancement transistor on the low side and a current source as a pull-up circuit. The current source comprises a depletion transistor and a resistive element in series.

[0367] FIG. 63 shows a two-stage logic inverter circuit. Each stage has an enhancement transistor on the low side with the gate connected to the input signal. The pull up circuit of the first stage is a current source, as shown above. The pull-up circuit of the second stage comprises a depletion transistor and a resistive element in series, where the gate of the depletion transistor is connected to the output of the first stage.

[0368] FIG. 64 shows a two-stage logic inverter circuit. Compared to the circuit in FIG. 63, an additional enhancement transistor is added to the pull-up circuit of the second stage in parallel to the resistive element.

[0369] FIG. 65 shows a two-stage logic inverter circuit. Compared to the circuit in FIG. 63, an additional transistor is added to the pull-up circuit of the second stage in parallel to the series arrangement with the depletion transistor and resistive element.

[0370] FIG. 66 shows a schematic representation of an embodiment of the invention with the current control block connected to a separate control terminal. Further, an enable and disable function is connected across the pull-down circuit. The enable and disable function comprises a logic inverter and an enhancement HEMT connected between the source of the active HEMT and the gate of the auxiliary HEMT.

[0371] FIG. 67 shows a schematic representation of an embodiment of the invention with an actively controlled current control block. In this embodiment, the current control block comprises a resistive element that is connected to the output of a transistor switch controlled by a buffer from a control signal. Further, an enable and disable function is connected across the pull-down circuit. The enable and disable function comprises a logic inverter and an enhancement HEMT connected between the source of the active HEMT and the gate of the auxiliary HEMT.

[0372] FIG. 68 shows a schematic representation of an embodiment of the invention with an actively controlled current control block, a voltage regulator between the control terminal and the current control block. Further, it comprises an enable and disable function connected to the gate of the auxiliary HEMT.

[0373] FIG. 69 shows a schematic representation of several exemplary embodiments of disable or enable functions. The disable or enable function may be integrated with the gate of the active HEMT, with the Miller clamp transistor, with the inverter circuit or with the pull-down circuit.

[0374] FIG. 70 shows a schematic representation of an arrangement with more than one main power device sharing the source. One or several input signals or input DC voltages may be shared between several gate interfaces. One or several signals or DC voltages generated in one gate interface circuit may be used in other gate interface circuits.

[0375] FIG. 71 shows an example of a current-voltage characteristic of the D-HEMT transistor illustrated in FIGS. 59 and 60.

[0376] FIG. 72 shows a circuit schematic of an example GaN chip comprising a pull-down circuit with an integrated capacitor configured to provide an internal rail voltage.

[0377] FIG. 73 shows a circuit schematic of a further example GaN chip comprising a pull-down circuit with an integrated capacitor configured to provide an internal rail voltage, where the integrated capacitor may also be charged by an external rail voltage through a depletion mode transistor.

[0378] FIG. 74 shows a circuit schematic of an example multi-stage inverter.

[0379] FIG. 75 shows a circuit schematic of an example Vg to Vlogic circuit block.

[0380] FIG. 76 shows a circuit schematic of a second example Vg to Vlogic circuit block.

[0381] FIG. 77 shows a circuit schematic of a third example Vg to Vlogic circuit block.

[0382] FIG. 78 shows a circuit schematic of fourth example Vg to Vlogic circuit block.

[0383] FIG. 79 shows a circuit schematic of an example DC/DC circuit block forming a linear voltage regulator.

[0384] FIG. 80 shows a circuit schematic of a further example DC/DC circuit block forming a linear voltage regulator.

[0385] FIG. 81 shows a circuit block diagram of a power integrated circuit comprising an internal rail voltage generation circuit.

[0386] FIG. 82 shows a circuit schematic of an example internal rail voltage generation circuit.

[0387] FIG. 83 shows a circuit schematic of a further example GaN chip comprising the internal rail voltage generation circuit of FIG. 82.

[0388] FIG. 84 shows a circuit schematic of a further example internal rail voltage generation circuit.

[0389] FIG. 85 shows a circuit schematic of a further example GaN chip comprising the internal rail voltage generation circuit of FIG. 84.

[0390] FIG. 86 shows a circuit schematic of an example current source.

[0391] FIG. 87 shows a circuit schematic of a further example current source.

[0392] FIG. 88 shows a circuit schematic of an example temperature compensated current source.

[0393] FIG. 89 shows a circuit schematic of an example voltage regulator incorporating the temperature compensated current source of FIG. 88.

[0394] FIG. 90 shows a circuit schematic of an example circuit implementing a further example temperature compensated current source.

[0395] FIG. 91 shows a circuit schematic of an example distributed transistors in a GaN chip.

[0396] FIG. 92 shows a circuit schematic of a further example distributed transistors in a GaN chip.

[0397] FIG. 93 shows a circuit schematic of a further example distributed transistors in a GaN chip.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0398] FIG. 2 illustrates a schematic representation of a cross section of the active area of the proposed disclosure, according to one embodiment of the disclosure. In use the current flows in the active area of the semiconductor device. In this embodiment, the device comprises a semiconductor (e.g. silicon) substrate 4 defining a major (horizontal) surface at the bottom of the device. Below the substrate 4 there is a substrate terminal 5. The device includes a first region of a transition layer 3 on top of the semiconductor substrate 4. The transition layer 3 comprises a combination of III-V semiconductor materials acting as an intermediate step to allow the subsequent growth of regions of high quality III-V semiconductor materials.

[0399] On top of the transition layer 3 there exists a second region 2. This second region 2 is of high quality III-V semiconductor (for example GaN) and comprises several layers. A third region 1 of III-V semiconductor containing a mole fraction of Aluminium is formed on top of the second region 2. The third region 1 is formed such that a hetero-structure is formed at the interface between the second 2 and third region 1 resulting in the formation of a two dimensional electron gas (2DEG).

[0400] A fourth region of highly p-doped III-V semiconductor 11 is formed in contact with the third region 1. This has the function of reducing the 2DEG carrier concentration when the device is unbiased, and is pGaN material in this embodiment. A gate control terminal 10 is configured over the fourth region 11 in order to control the carrier density of the 2DEG at the interface of the second 2 and third region 1. A high voltage drain terminal 9 is arranged in physical contact with the third region 1. The high voltage drain terminal forms an ohmic contact to the 2DEG. A low voltage source terminal 8 is also arranged in physical contact with the third region 1 and also forms an ohmic contact to the 2DEG.

[0401] A portion of surface passivation dielectric 7 is formed on top of the fourth region 1 and between the drain terminal 9 and source terminal 8. A layer of SiO.sub.2 passivation 6 is formed above the surface passivation dielectric 7 and source and drain terminals 8, 9.

[0402] The device is separated into two cross sections by a vertical cutline. The two cross sections may not be necessarily placed in the same plane. The features described above are on one side (right hand side, for example) of the vertical cutline. This is termed as the active device 205. The other side of the vertical cutline (the left hand side, for example) is termed as the auxiliary device 210, which also comprises a semiconductor substrate 4, a transition layer 3, a second region 2 and a SiO.sub.2 passivation region 6.

[0403] A fifth region of III-V semiconductor 17 containing a mole fraction of Aluminium is positioned above the second region 2 in the auxiliary device such that a hetero-structure is formed at the interface between this fifth region 17 and the second region 2. This results in the formation of a second two dimensional electron gas (2DEG) in a region which will be referred to as the auxiliary gate. This AlGaN layer 17 of the auxiliary device 210 can be identical or different to the AlGaN layer 1 in the active device 205. The AlGaN layer thickness and AI mole fraction are critical parameters as they affect the carrier density of electrons in the 2DEG [15].

[0404] A sixth region of highly p-doped III-V semiconductor 14 is formed on top of and in contact with the fifth region 17. This has the function of reducing the 2DEG carrier concentration when the auxiliary gate is unbiased. An auxiliary gate control terminal 15 is configured over the sixth region 14 in order to control the carrier density of the 2DEG at the interface of the fifth 17 and second region 2. The auxiliary gate pGaN layer 14 may be identical or different to the active gate pGaN layer 11. Critical parameters which could differ include, but are not limited to, pGaN doping and width along the x-axis (shown in the figure).

[0405] An isolation region 13 is formed down the vertical cutline. This cuts the electrical connection between the 2DEG formed in the active device 205 and the 2DEG formed in the auxiliary device 210.

[0406] A first additional terminal 16 is arranged on top of and in physical contact with the fifth region 17 of the auxiliary device 210. This forms an ohmic contact to the 2DEG of the auxiliary device 210 and is also electrically connected (via interconnection metal) to the auxiliary gate control terminal 15 configured over the sixth region (pGaN) 14. The first additional terminal 16 is biased at the same potential as the auxiliary gate terminal 15 of the auxiliary device. A second additional terminal 12 is also arranged on top of and in physical contact with the fifth region 17 of the auxiliary device 210. This forms an ohmic contact to the 2DEG of the auxiliary device 210 and is electrically connected (via interconnection metal) to the active gate control terminal 10 configured over the fourth region 11 of the active device 205. The interconnection between the second additional terminal 12 of the auxiliary device 210 and the active gate terminal 10 of the active device 205 can be made in the third dimension and can use different metal layers in the process. Note that this interconnection is not shown in the schematic in FIG. 2. A similar but not necessarily identical AlGaN/GaN structure is used in the auxiliary gate.

[0407] When the device is in use the auxiliary gate 14, 15 drives the active gate 10, 11. The auxiliary 2DEG layer formed between the first and second additional terminals 12, 16 with the portion under the auxiliary p-GaN gate 14 is controlled by the potential applied to the auxiliary gate terminal 15.

[0408] The portion of the auxiliary 2DEG under the auxiliary pGaN gate 14 is depleted when the auxiliary gate terminal 15 and the short-circuited first additional terminal 16 are at 0V. As the auxiliary gate bias is increased (both terminals 15, 16) the 2DEG starts forming under the pGaN gate 14 connecting to the already formed 2DEG layer which connects to the first and second additional terminals 16, 12. A 2DEG connection is now in place between the first and second additional terminals 12, 16.

[0409] As the second additional terminal 12 is connected to the active gate 10 the device can now turn on. A positive (and desirable) shift in the device threshold voltage is observed using this structure as not all of the potential applied to the auxiliary gate 15 is transferred to the active gate 10. Part of this potential is used to form the auxiliary 2DEG under the auxiliary gate 15 and only part is transferred to the second additional terminal 12 which is connected to the active gate 10.

[0410] The auxiliary gate provides the additional advantage of being able to control the gate resistance of the device more easily. This can be achieved by varying the field plate design or distance between terminals 12 and 15 or 15 and 16. This can be useful in controlling the unwanted oscillations observed due to the fast switching of these devices.

[0411] Different embodiments of the device can include terminals 10, 15 being either Schottky or Ohmic contacts or any combination of those two.

[0412] FIG. 3 shows a circuit schematic representation of one embodiment of the proposed disclosure as shown in the schematic cross section of FIG. 2. The features shown in FIG. 3 carry the same reference numbers as the features in FIG. 2.

[0413] FIG. 4A shows a circuit schematic representation of a further embodiment of the proposed disclosure in which a low on-state voltage diode is connected in parallel between the drain and the source of the auxiliary transistor, as shown in the schematic 3D illustration in FIG. 4B. Many of the features of this embodiment are similar to those of FIG. 2 and therefore carry the same reference numerals, i.e., the semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO.sub.2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16 and second additional terminal 12. However, in this embodiment a low on-state voltage diode 31 is connected in parallel between the drain 16 and the source 12 of the auxiliary transistor. The parallel diode 31 acts as pull-down network during the turn-off of the overall configuration connecting to ground the gate terminal 10 of the active GaN transistor. When a positive bias (known as on-state) is applied to the auxiliary gate 15, the diode 31 will be reverse-biased and zero current will flow through it, leaving unaffected the electrical behaviour of the overall high-voltage configuration. When a zero bias (off-state) will be applied to the auxiliary gate 15 the diode 31 will be forward bias and the turn-off current flowing through it will discharge the gate capacitance of the active transistor, thus enabling the switching off of the overall configuration. In off-state, the gate of the active device 10 will remain biased to a minimum voltage equal to the turn-on voltage of the diode. The diode 31 will therefore be designed in such a way that its turn-on voltage will be as low as possible, ideally few mV. FIG. 4B illustrates how the diode 31 could be included monolithically. The diode could be a simple Schottky diode or could be a normal p-n diode. The diode 31 would pull down the active gate 10 during turn-off to the diode Vth, therefore the diode needs to be designed to have as low a threshold voltage as possible. A feature which can achieve this is the use of a recessed anode such that the contact is made directly to the 2DEG as seen in FIG. 4C.

[0414] FIG. 5 shows a circuit schematic representation of a further embodiment of the proposed disclosure in which the drain (gate) terminal 16 and the source terminal 12 of the auxiliary transistor are available as external gate terminals. Many of the features of this embodiment are similar to those of FIG. 2 and therefore carry the same reference numerals, i.e., the semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO.sub.2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16 and second additional terminal 12. However, in this case the external gate terminal is divided into two terminals. Since the gate driver sink output pin can now be connected to the source terminal of the auxiliary transistor directly offering a pull-down path, component 31 in FIG. 4 may (or may not) be omitted.

[0415] FIG. 6 shows a circuit schematic representation of a further embodiment of the proposed disclosure where a second auxiliary transistor 34 (could be advantageously low-voltage) is connected in parallel with the first auxiliary transistor where the drain (gate) terminal 16 of the first auxiliary transistor is connected to the source terminal of the second auxiliary transistor and the source terminal 12 of the first auxiliary transistor is connected to the drain (gate) terminal of the second auxiliary transistor. Many of the features of this embodiment are similar to those of FIG. 2 and therefore carry the same reference numerals, i.e., the semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO.sub.2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16 and second additional terminal 12. However, in this case the pull-down network during the turn-off of the overall configuration is a second auxiliary transistor 34.

[0416] FIG. 7 shows a circuit schematic representation of a further embodiment of the proposed disclosure where a resistor 41 is added between the drain terminal 12 and gate terminal 10 of the second auxiliary transistor 34. Many of the features of this embodiment are similar to those of FIG. 6 and therefore carry the same reference numerals, i.e., the semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO.sub.2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12 and second auxiliary transistor 34. In this embodiment, the resistor 41 acts to reduce the active gate capacitance discharge time through the pull-down network during the turn-off of the active device. The additional resistor performs this function by creating an increased potential, during turn-off, of the second auxiliary transistor gate terminal 10 compared to the second auxiliary transistor drain terminal 12.

[0417] FIG. 8 shows a circuit schematic representation of a further embodiment of the proposed disclosure where an additional resistor 42 is added between the source terminal of the auxiliary transistor (drain terminal 12 of the second auxiliary transistor) and source terminal 8 of the active device. Many of the features of this embodiment are similar to those of FIG. 7 and therefore carry the same reference numerals, i.e., the semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO.sub.2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, second auxiliary transistor 34 and resistive element 41. In this embodiment, the additional resistive element 42 acts as an additional pull-down network during the active device turn-off. During the active device turn-on and on-state the additional resistance 42 can act as a voltage limiting component to protect the gate terminal of the active device.

[0418] FIG. 9 shows a circuit schematic representation of a further embodiment of the proposed disclosure where a third auxiliary transistor 58 is added between the drain terminal 12 and gate terminal 10 of the second auxiliary transistor 34. Many of the features of this embodiment are similar to those of FIG. 8 and therefore carry the same reference numerals, i.e., the semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO.sub.2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, second auxiliary transistor 34 and additional resistive element 42. In this embodiment, the third auxiliary transistor acts to reduce the active gate capacitance discharge time through the pull-down network during the turn-off of the heterojunction power device. The third auxiliary transistor 58 performs this function by creating an increased potential, during turn-off, of the second auxiliary transistor gate terminal 10 compared to the second auxiliary transistor drain terminal 12. The third auxiliary transistor is a depletion mode device. The gate terminal of the third auxiliary transistor is connected to the source terminal of the third auxiliary transistor.

[0419] FIG. 10 shows a circuit schematic representation of a further embodiment of the proposed disclosure where a third auxiliary transistor 59 is added between the drain terminal 12 and gate terminal 10 of the second auxiliary transistor 34. Many of the features of this embodiment are similar to those of FIG. 8 and therefore carry the same reference numerals, i.e., the semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO.sub.2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, second auxiliary transistor 34 and additional resistive element 42. In this embodiment, the third auxiliary transistor acts to reduce the active gate capacitance discharge time through the pull-down network during the turn-off of the heterojunction power device. The third auxiliary transistor 59 performs this function by creating an increased potential, during turn-off, of the second auxiliary transistor gate terminal 10 compared to the second auxiliary transistor drain terminal 12. The third auxiliary transistor is a depletion mode device. The gate terminal of the third auxiliary transistor is connected to the drain terminal of the third auxiliary transistor.

[0420] FIG. 11 shows a circuit schematic representation of a further embodiment of the proposed disclosure where a voltage limiting circuit is implemented composed of a resistor 44, a resistor 45 (forming a potential divider) and an actively switched low voltage enhancement mode transistor 43. Many of the features of this embodiment are similar to those of FIG. 6 and therefore carry the same reference numerals, i.e., the semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO.sub.2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12 and second auxiliary transistor 34. In this embodiment, the enhancement mode transistor 43 can turn-on, and thus adjust the resistance between the active device gate terminal 10 and the active device source terminal 8, when the potential of the first additional terminal 16 (or the drain (gate) terminal 16) of the first auxiliary heterojunction transistor is raised above a certain value which can be controlled by the choice of resistors (44, 45) in the potential divider described. This function can protect the active gate terminal from over-voltage events.

[0421] FIG. 12 shows a circuit schematic representation of a further embodiment of the proposed disclosure where a voltage limiting circuit is implemented comprising a resistor 44, a resistor 45 (forming a potential divider) and an actively switched low voltage depletion mode transistor 46. Many of the features of this embodiment are similar to those of FIG. 6 and therefore carry the same reference numerals, i.e., the semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO.sub.2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12 and second auxiliary transistor 34. In this embodiment, the resistance of the depletion mode transistor 46 can be reduced, and thus adjust the resistance between the active device gate terminal 10 and the active device source terminal 8, when the potential of the first additional terminal 16 (or the drain (gate) terminal 16) of the first auxiliary heterojunction transistor is increased. The potential divider formed by the two resistors (44, 45) determines the potential on the gate terminal of the depletion mode transistor 46. The circuit described can protect the active gate terminal from over-voltage events.

[0422] FIG. 13 shows a circuit schematic representation of a further embodiment of the proposed disclosure where an over-current protection circuit is implemented composed of a current sensing resistor 48 and an actively switched low voltage enhancement mode transistor 49. Many of the features of this embodiment are similar to those of FIG. 6 and therefore carry the same reference numerals, i.e., the semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO.sub.2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12 and second auxiliary transistor 34. In this embodiment, the active area of the active (high voltage) transistor is divided into two regions forming two transistors in parallel. The drain and gate terminals of the two transistors are electrically connected. The two transistors in parallel are a low resistance (main power) transistor 55 and a high resistance (current sensing) transistor 54 comparatively. The first terminal of the current sensing resistor 48 is connected to the source terminal of the high resistance transistor 54. The potential at the gate terminal of the enhancement mode transistor 49 is increased as the current through the current sensing resistor 48 is increased. When the current through resistive element 48 reaches a critical value the enhancement mode transistor 49 turns on providing a reduction in the resistance of the path between the gate 10 and source 8 of the active (high voltage) device thus limiting the potential on the active gate terminal 10. The circuit described can protect the circuit from an over-current event.

[0423] FIG. 14 shows a circuit schematic representation of a further embodiment of the proposed disclosure where an over-current protection circuit is implemented composed of a current sensing resistor 48 and an actively switched low voltage depletion mode transistor 47. Many of the features of this embodiment are similar to those of FIG. 6 and therefore carry the same reference numerals, i.e., the semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO.sub.2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12 and second auxiliary transistor 34. In this embodiment, the active area of the active (high voltage) transistor is divided into two isolated regions forming two transistors in parallel. The drain and gate terminals of the two transistors are electrically connected. The two transistors in parallel are a low resistance (main power) transistor 55 and a high resistance (current sensing) transistor 54 comparatively. The first terminal of the current sensing resistor 48 is connected to the source terminal of the high resistance transistor 54. The potential at the gate terminal of the depletion mode transistor 47 is increased as the current through the resistive element 48 is increased. As the current through resistive element 48 increases the resistance of the depletion mode transistor 49 can decrease providing a reduction in the resistance of the path between the gate 10 and source 8 of the active (high voltage) device thus limiting the potential on the active gate terminal 10. The circuit described can protect the circuit from an over-current event.

[0424] FIG. 15 shows a circuit schematic representation of a further embodiment of the proposed disclosure where an active Miller clamp circuit is implemented composed of a resistor 52, an actively switched low voltage enhancement mode transistor 50 and an actively switched depletion mode transistor 51. Many of the features of this embodiment are similar to those of FIG. 6 and therefore carry the same reference numerals, i.e., the semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO.sub.2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12 and second auxiliary transistor 34. In this embodiment, the active Miller clamp circuit is implemented to offer an additional pull-down network for the active device gate terminal 10 during the device turn-off transient.

[0425] FIG. 16 shows a circuit schematic representation of a further embodiment of the proposed disclosure where an active Miller clamp circuit is implemented composed of a resistor 52, an actively switched low voltage enhancement mode transistor 50 and an actively switched enhancement mode transistor 53. Many of the features of this embodiment are similar to those of FIG. 6 and therefore carry the same reference numerals, i.e., the semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO.sub.2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12 and second auxiliary transistor 34. In this embodiment, the active Miller clamp circuit is implemented to offer an additional pull-down network for the active device gate terminal 10 during the device turn-off transient.

[0426] FIG. 17 illustrates a schematic representation of a cross section of the active area of a proposed depletion mode device in prior art which can be used as the actively switched transistor in locations 46, 47, 51, 58, 59, 60.

[0427] FIG. 18 illustrates a three dimensional schematic representation of the active area of a proposed depletion mode device with pGaN islands (not found in prior art) which can be used as the actively switched transistor in locations 46, 47, 51, 58, 59, 60.

[0428] FIG. 19 illustrates a three dimensional schematic representation of the active area of the depletion mode device with pGaN islands shown in FIG. 18 operated in diode mode and can be used in locations 34 58 59.

[0429] FIGS. 59 and 60 show schematic representations of two further embodiments of a transistor with p-GaN islands 11. In FIG. 59, they are arranged in such a way that an S-shaped meander is formed between the islands 11. The p-GaN islands are operatively connected through a contact layer 10 to the common gate terminal 59. FIG. 60 is a similar embodiment with three rows of p-GaN islands 11 arranged to form a labyrinth shaped 2DEG between the islands.

[0430] FIG. 71 shows an example of a current-voltage characteristic of the D-HEMT transistor illustrated in FIGS. 59 and 60.

[0431] The D-HEMT with p-GaN islands illustrated in FIGS. 59 and 60, when in the high resistance mode (gate bias with respect to source bias is between the first and second threshold voltage level), may feature a saturation current behaviour limiting the current at strong forward bias. The extent to which the current saturates may be affected by the distance between the pGaN islands where the smaller the distance between the pGaN islands, the stronger the current saturation observed. An example of this saturation is illustrated in FIG. 71.

[0432] FIG. 20 shows the transfer characteristic of the proposed depletion mode device shown in FIG. 18.

[0433] FIG. 21 illustrates the cross-section of an additional embodiment according to a second aspect of the proposed invention. The features shown in FIG. 21 carry the same reference numerals as those shown in FIG. 2. In this embodiment, the first additional terminal 16 and the auxiliary gate terminal 15 are not operatively connected.

[0434] FIG. 22 shows a schematic illustration of the structure of FIG. 21, and corresponding features of this figure use the same reference numerals. In this embodiment, a range of components may be added between the auxiliary gate terminal 15 and the first additional terminal 16. Merely for example, these components may include, but are not limited to, any one or more of resistive elements, passive elements and current sources. Further illustrative examples of such embodiments are presented herein.

[0435] In FIG. 23 a Gallium Nitride (GaN) chip 1000 (also referred to as a smart GaN power device or a GaN power or high voltage integrated circuit) is shown according to an embodiment of the second aspect of this invention. The GaN chip may comprise at least three terminals. These at least three terminals may include one or more of a high voltage terminal, a low voltage terminal and a control terminal. The chip 1000 may further comprise one or more main power heterojunction transistors 500 with an internal gate. The source and drain terminals of transistor 500 may be connected to the low voltage and high voltage terminals of the GaN chip respectively. Chip 1000 may further comprise a current control circuit 530, a pull-down circuit 520 and/or an auxiliary gate circuit 510. The auxiliary gate circuit 510 may contain at least one low-voltage heterojunction transistor (also referred to as an auxiliary transistor) with an internal gate.

[0436] The auxiliary gate circuit 510 may be operatively connected to at least the internal gate of the one main power heterojunction transistor 500 by a first connection, and may further comprise a second connection to operatively connect the auxiliary gate 510 to the control terminal. A third connection of the auxiliary gate circuit 510 may operatively connect the internal gate of the low-voltage heterojunction transistor of auxiliary gate circuit 510 to the pull down circuit 520.

[0437] In addition to the at least one connection to the auxiliary gate circuit, pull-down circuit 520 may comprise at least one connection to the current control circuit and at least one connection to the source terminal of the main power heterojunction transistor 500.

[0438] Current control circuit 530 may comprise at least one connection to each of the control terminal, auxiliary gate circuit 510 and pull down circuit 520.

[0439] The auxiliary gate 510 may partly control the voltage and the current levels into the internal gate of the main power heterojunction transistor 500. The current control circuit 530 may control the current level into pull down circuit 520 and in conjunction with the pull down circuit may further determine the voltage level applied to the internal gate of the low-voltage heterojunction transistor of auxiliary gate 510. The pull-down circuit in turn may actively pull down the gate voltage of the low-voltage heterojunction transistor in order to clamp the voltage of the internal gate of the main power heterojunction transistor.

[0440] With reference to FIGS. 22 and 23, in some embodiments the auxiliary gate terminal 15 of auxiliary gate block 510 may be connected through or via current control block 530 to the first additional terminal 16 of auxiliary gate block 510. Auxiliary gate terminal 15 may be further connected through or via the pull-down circuit block 520 to the source terminal 8 of active device block 500.

[0441] The portion of the auxiliary 2DEG under the auxiliary pGaN gate 14 may be depleted when the auxiliary gate terminal 15 is at or close to 0V. As the first additional terminal bias is increased, the potential on both terminals 15, 16 may increase and the 2DEG may begin forming under pGaN gate 14. The 2DEG formed under pGaN gate 14 may connect to the (already formed) 2DEG layers under the first and second additional terminals 16, 12. By connecting these 2DEG layers, a 2DEG connection may be formed between the first and second additional terminals 12, 16.

[0442] As the second additional terminal 12 is connected to the active gate 10 the device can now turn on. A positive shift in the device threshold voltage is observed using this structure as not all of the potential applied to the first additional terminal 16 is transferred to the active gate (internal gate) 10. Part of this potential is dropped across the auxiliary gate 510 and only part is transferred to the second additional terminal 12 which is connected to the active gate (internal gate) 10. Advantageously, this enables an increase in the threshold voltage without compromising the on-state resistance of the device, as discussed below.

[0443] FIG. 24 shows an example of the relationship between the external gate voltage bias (GaN chip control terminal bias) 2501 and the active gate voltage (internal gate voltage) 2502 according to one embodiment of the invention. When the external gate voltage signal rises initially (up to auxiliary gate transistor Vth) the auxiliary gate transistor has a high resistance. The majority of the potential applied is dropped across the auxiliary gate transistor and the potential of the active gate terminal remains close to 0V. When the external gate voltage signal reaches the auxiliary gate transistor Vth the auxiliary transistor becomes less resistive and the potential of the active gate terminal starts rising.

[0444] A threshold voltage increase is therefore achieved in the GaN chip multi-block HEMT without any compromise in the on-state resistance of the device. A positive shift (as shown in graph 2500) in the device threshold voltage is observed using this structure as not all of the potential applied to the external gate is transferred to the active gate (part of this potential is used to form the auxiliary 2DEG under the auxiliary gate) and only part is transferred to the terminal 12 which is connected to the active gate 10.

[0445] When the external gate 16 bias voltage reaches a pre-designed level, pull-down circuit block 520 becomes operational and pulls the gate 15 of the auxiliary transistor towards the active transistor source terminal 8 potential. The auxiliary transistor has a high resistance in this condition, therefore any additional external gate potential is dropped across the auxiliary transistor and the active gate terminal potential remains approximately constant with the external gate voltage signal rising, for example to at least approximately 20V.

[0446] The design of the current control block 530 and pull-down circuit block 520 determines the potential where the active gate terminal is clamped.

[0447] Several illustrative examples are included herein with different implementations of the functional blocks 510, 520, 530. Note that the list of examples presented is not exhaustive and any combination of the different implementations for each block can be considered under the scope of this invention. This includes the several examples of the auxiliary gate presented above. Furthermore, any or all of the protection and control circuits (over-voltage, overcurrent, miller clamp) presented above may also be combined with the functional blocks presented in FIG. 23.

[0448] FIG. 25 shows a schematic representation of one embodiment the GaN chip 1000a of the proposed invention. Auxiliary gate block 510a comprises an enhancement mode low voltage HEMT, current control block 530a comprises a resistor and the pull-down circuit 520a comprises a HEMT in threshold multiplier configuration. The threshold multiplier configuration in this embodiment comprises a potential divider and a pull-down enhancement mode HEMT where the midpoint of the potential divider is connected to the gate terminal of the pull-down HEMT. In this embodiment, the top of the potential divider is connected to the drain of the pull-down enhancement mode HEMT and the gate terminal of the auxiliary gate block HEMT.

[0449] FIG. 26 shows a schematic representation of a further embodiment of the GaN chip 1000b of the proposed invention where the auxiliary gate block 510b comprises an enhancement mode low voltage HEMT. The current control block 530b comprises a resistor in parallel with an RC circuit. The RC circuit in parallel can improve the device dynamic characteristic during turn-on and turn-off transients. The pull-down circuit 520b comprises a HEMT in threshold multiplier configuration with a passive element in parallel. The passive element can improve the device dynamic characteristic during turn-on and turn-off transients.

[0450] FIG. 27 shows a schematic representation of a further embodiment of the GaN chip 1000c of the proposed invention. The auxiliary gate block 510c comprises an enhancement mode low voltage HEMT and a Schottky or p-n diode in parallel. In this embodiment, a low on-state voltage diode is connected in parallel between the drain 16 and the source 12 of the auxiliary transistor. The parallel diode acts as pull-down network during the turn-off of the overall configuration connecting to ground the gate terminal 10 of the active GaN transistor. When a positive bias (known as on-state) is applied to the external gate terminal 16, the diode will be reverse-biased and zero current will flow through it, leaving unaffected the electrical behaviour of the overall high-voltage configuration. When a zero bias (off-state) is applied to the auxiliary gate 15 the diode is forward biased and the turn-off current flowing through it will discharge the gate capacitance of the active transistor, thus enabling the switching off of the overall configuration. In off-state, the gate of the active device 10 will remain biased to a minimum voltage equal to the turn-on voltage of the diode. The diode will therefore be designed in such a way that its turn-on voltage will be as low as possible, ideally few mV. The current control block 530c comprises a current source using a low voltage depletion mode HEMT and a resistor. The resistor value can be adjusted to set the maximum current level that can flow through the current source. The pull-down circuit 520c comprises a HEMT in threshold multiplier configuration.

[0451] FIG. 28 shows a schematic representation of a further embodiment of the GaN chip 1000d of the proposed invention where the auxiliary gate block 510d comprises an enhancement mode low voltage HEMT. The current control block 530d comprises a current source using a low voltage depletion mode HEMT and a resistor. The pull-down circuit 520d comprises a HEMT in threshold multiplier configuration.

[0452] FIG. 29 shows a schematic representation of a further embodiment the GaN chip 1000e of the proposed invention where the auxiliary gate block 510e comprises an enhancement mode low voltage HEMT. Furthermore, in this embodiment, a second auxiliary transistor (could be advantageously low-voltage) is connected in parallel with the first auxiliary transistor in the auxiliary gate block where the drain terminal 16 of the first auxiliary transistor is connected to the drain terminal of the second auxiliary transistor and the source terminal 12 of the first auxiliary transistor is connected to the source (gate) terminal of the second auxiliary transistor. In this embodiment, the pull-down network during the turn-off of the overall configuration is a second auxiliary transistor. This is similar to the embodiment shown in FIG. 27 but utilises a second auxiliary transistor rather than a diode. The current control block 530e comprises a current source using a low voltage depletion mode HEMT and resistor. The pull-down circuit 520e comprises a HEMT in threshold multiplier configuration.

[0453] FIG. 30 shows a schematic representation of a further embodiment the GaN chip 1000f of the proposed invention where the auxiliary gate block 510f comprises an enhancement mode low voltage HEMT. Furthermore, in this embodiment, a second auxiliary transistor is connected in parallel with the first auxiliary transistor as outlined in the embodiment in FIG. 29. The current control block 530f comprises a current source using a low voltage depletion mode HEMT and resistor. The pull-down circuit 520f comprises a HEMT in threshold multiplier configuration. In this embodiment, the threshold multiplier further comprises a current source in parallel with one of the resistors in the potential divider of the threshold multiplier circuit. The inclusion of the current source provides stability in temperature in the value of the clamped voltage achieved on the active gate of the high voltage transistor 500 when the voltage signal on the external gate terminal is high.

[0454] FIG. 31 shows a schematic representation of a further embodiment the GaN chip 1000j of the proposed invention where the auxiliary gate block 510j comprises an enhancement mode low voltage HEMT. The current control block 530j comprises a current source using a low voltage depletion mode HEMT and resistor. The pull-down circuit 520j comprises a HEMT in threshold multiplier configuration similar to previous embodiments which comprise a potential divider and an enhancement mode pull-down HEMT.

[0455] However, in this embodiment, the resistor at the top of the potential divider, which in previous embodiments was connected to the drain terminal of the enhancement mode pull-down HEMT, is alternatively connected to the source terminal of the depletion mode HEMT used in the current source of the control block.

[0456] FIGS. 46 and 47 show further embodiments of the invention with the pull-down circuit comprising a second input. This second input may be a supply or regulated voltage stemming from an external terminal or generated on the chip. The second input may be used as a reference voltage.

[0457] FIG. 48 shows a schematic representation of a further embodiment of the pull-down circuit 520k. The pull-down circuit block comprises a voltage source and a capacitor in series with a HEMT in a diode configuration. In this embodiment, the resulting voltage drop across the pull-down circuit is the sum of the voltage level of the voltage source and the voltage drop across the HEMT at the current level defined by the current control block. When zero volts, or a small voltage (for example below 1V) or a negative voltage is applied to the external gate terminal 16 (off-state), the HEMT in diode configuration will be reversed biased. FIG. 49 shows a similar embodiment of the pull-down circuit where the HEMT is not in diode configuration but rather in a threshold multiplier configuration using two resistive elements. Other examples include the use of non-linear elements in the threshold multiplier configuration.

[0458] FIG. 32 shows a block diagram schematic representation of a further embodiment of the proposed invention. In this embodiment, some additional functional blocks are included compared to the embodiment shown in FIG. 23. In this embodiment, the auxiliary gate block, current control block and pull-down circuit block are included as in previous embodiments. An integrated active Miller clamp is also included.

[0459] FIG. 61 shows the schematics of an embodiment of a logic inverter 560a comprising a resistive element as a pull-up circuit and an enhancement mode transistor on the low side, similar to those shown in FIGS. 15 and 16 driving the Miller clamp transistor.

[0460] FIG. 62 shows a further embodiment of the logic inverter 560b comprising a current source circuit rather than a resistive element in series with an enhancement mode transistor in which the current source consists of a depletion mode transistor and a resistive element.

[0461] In FIG. 63, an embodiment of the logic inverter 560c is shown that consists of two stages. In a multi-stage inverter, all stages comprise an enhancement transistor on the low side with the gate connected to the input signal. Both stages comprise a pull-up circuit, the one of the second stage is controlled by the output of the first stage. In this embodiment of a two-stage inverter, the pull-up circuit of the first stage comprises a current source as described above. The pull-up circuit of the second stage comprises a resistive element and a depletion-mode transistor in series where the gate of the depletion-mode transistor is connected to the output of the first stage. In this embodiment the capacitance of the output of the first stage may be very small, leading to a fast switching time even at a small current consumption. Therefore, the gate of the depletion-mode transistor of the second stage will rise faster than in a current source arrangement. Therefore, this arrangement may lead to a faster switching time at a given load and a given current consumption.

[0462] A further embodiment of a two-stage inverter 560d is shown in FIG. 64. An additional enhancement transistor is connected to the pull-up circuit of the second stage. This transistor has the gate connected to the output of a previous stage and is connected in parallel to the resistive element of the pull-up circuit. During switching to high, the output of the first stage is at a higher voltage compared to the output of the second stage. Therefore, the gate of the additional pull-up circuit transistor being positively biased compared to its source terminal reduces its resistance and increases the current into the output signal. Before and after switching, the output of the first stage and second stage are the same, and the gate of the additional pull-up circuit transistor has zero bias compared to its source bias. The increased current during switching leads to a faster switching time for a given load, such as the actively switched transistor of a Miller clamp, without compromising current consumption in the high or low state.

[0463] In FIG. 65, a further embodiment of a two-stage inverter 560e is shown. Compared to FIG. 63, the additional pull-up circuit enhancement transistor is connected between the dc voltage rail and the output and works similarly as described in FIG. 64.

[0464] The active Miller clamp circuit (for example in FIG. 32) is implemented to offer an additional pull-down network for the active device gate terminal 10 during the device turn-off transient. The active Miller clamp circuit may comprise a monolithically integrated Miller clamp transistor 570, a logic inverter 560, an external gate signal to logic signal conversion 540 and/or a DC to DC block 550 to produce an appropriate inverter VDD rail.

[0465] The transistor 570 may include a low voltage enhancement mode HEMT as illustrated in this embodiment. The logic inverter 560 may include a low voltage enhancement mode HEMT and a resistor (similar to the inverter circuit illustrated in FIG. 16). However, this is merely provided as an example configuration, and other logic inverter designs (as illustrated in FIGS. 61, 62, 63, 64 and 65) could be utilised in place of or in addition to this. The enhancement mode device used in the inverter may be formed in the same process step as the active high voltage transistor. Therefore, the upper limit of the voltage signal that can be applied to the gate of the inverter transistor might be lower than the external gate signal. The Vg to logic block 540 may be used to reduce the external gate voltage signal to a voltage signal appropriate for use with a p-GaN technology enhancement mode HEMT.

[0466] The integrated Miller clamp transistor may receive a signal close to VDD to its gate terminal when the output of the inverter is high. Therefore, if the VDD rail available is higher than the peak gate voltage that the integrated clamp resistor can tolerate then a DC/DC step 550 may be integrated into the GaN chip multi-block power device to reduce the VDD rail to a desirable level.

[0467] FIG. 50 shows the block diagram of a voltage regulator (or DC/DC block) 550 connected to the input of the receiving circuit (for example the logic inverter) through a decoupling circuit 580. An embodiment with a decoupling circuit may protect the inverter from current spikes or voltage excursions induced from the voltage source. These current spikes or voltage excursions may be a result of electromagnetic coupling of the circuit to other elements of the chip or the system, in particular, fast voltage and current slopes and may originate from the input to the DC/DC block, or within the DC/DC block. Overvoltage of the DC voltage may destroy the inverter, under voltage may lead to malfunction.

[0468] In FIG. 51, an exemplary embodiment of the decoupling circuit is shown where the decoupling circuit 580a consists of a series resistive element and a capacitor across the input voltage of the inverter. In another embodiment, shown in FIG. 52, the resistive element may be replaced with a current source formed of a depletion HEMT and a resistive element. FIGS. 53 and 54 show exemplary embodiments, where a transistor is added to the current source in parallel to the current source or in parallel to the resistive element to adjust the current limit through the current source. When the additional transistor is in a low resistive state the coupling is strong for high current supply. When the additional transistor is in a high resistive state, the coupling is weak (good decoupling) but only a low current can be supplied through the decoupling circuit. The additional HEMT allows adjusting coupling and current limit to varying operating status.

[0469] FIG. 55 shows the decoupling circuit 580e comprising a current source as in FIG. 52 and an additional HEMT in parallel to the capacitive element. This additional HEMT allows sinking the current in case of a current spike and may be effective against overvoltage. In this exemplary embodiment, the additional HEMT is turned on by a resistive and capacitive voltage divider on the input side of the decoupling circuit. When the input voltage rises to a certain level or exceeds a certain rate the gate of the additional HEMT is increased to turn the HEMT on and to sink excess current.

[0470] FIG. 56 shows an additional embodiment of a decoupling circuit 580c (similar to the decoupling circuit 580e shown in FIG. 55) in which the additional HEMT in parallel with the current source is controlled by having its gate connected to the gate voltage of the active HEMT 500. In this embodiment, the coupling is strong when the active HEMT is in the on-state, weak when the active HEMT is off.

[0471] The described decoupling circuits may be applied not just for the input of the inverter but for any dc signal or dc supply voltage on the chip.

[0472] FIG. 33 shows a schematic representation of a further embodiment the GaN chip 3000a of the proposed invention where the auxiliary gate block 610a comprises a depletion mode low voltage HEMT. The current control block 630a comprises a resistive element. The pull-down circuit 620a comprises a HEMT in threshold multiplier configuration. The operation of the GaN chip multi-block power device illustrated in this embodiment is similar to the operation of the device illustrated in FIG. 25 in achieving a clamped voltage signal on the active gate terminal (internal gate terminal) of the high voltage HEMT (the main power heterojunction transistor) 500 when the external voltage signal exceeds a pre-determined (by design) level. The use of a depletion mode transistor in the auxiliary gate block in this embodiment might not be as effective in providing an increased threshold voltage for the GaN chip power device 3000a, compared to the GaN chip power device 1000a. The low voltage depletion mode HEMT may be more effective in providing a turn-off path as part of the turn-off network of the device as the channel in the depletion-mode transistor is present when the potential on the active gate is high and the potential at the external gate terminal is low.

[0473] FIG. 34 shows a schematic representation of a further embodiment of the GaN chip 3000b of the proposed invention where the auxiliary gate block 610b comprises a depletion mode low voltage HEMT. In this embodiment, a second auxiliary transistor (which may advantageously be a low-voltage transistor) is connected in parallel with the first auxiliary transistor in the auxiliary gate block where the drain terminal 16 of the first auxiliary transistor is connected to the drain terminal of the second auxiliary transistor and the source terminal 12 of the first auxiliary transistor is connected to the source (gate) terminal of the second auxiliary transistor. In this embodiment, the second auxiliary transistor is included as an additional pull-down network during the turn-off of the high voltage transistor 500. The current control block 630e comprises a current source using a low voltage depletion mode HEMT and resistor. The pull-down circuit 620e comprises a HEMT in threshold multiplier configuration.

[0474] FIG. 35 shows a schematic representation of a further embodiment the GaN chip 3000d of the proposed invention where the auxiliary gate block 610d comprises a depletion mode low voltage HEMT. Furthermore, in this embodiment, a second depletion mode auxiliary transistor (could be advantageously low-voltage) is connected in parallel with the first auxiliary transistor in the auxiliary gate block where the drain terminal 16 of the first auxiliary transistor is connected to the drain terminal of the second auxiliary transistor and the source terminal 12 of the first auxiliary transistor is connected to the source terminal of the second auxiliary transistor. The gate terminal of the second auxiliary transistor is connected to the source terminal of the high voltage transistor 500. In this embodiment, the second depletion mode auxiliary transistor is included as an additional current path during the turn-on of the high voltage transistor 500. When the external gate signal goes high the second depletion-mode transistor is in saturation mode and provides an additional conduction path for charging the gate-source capacitance of the high voltage transistor 500. As the voltage of the active gate terminal rises above the threshold voltage of the second depletion mode transistor that conduction path becomes very resistive. The current control block 630e comprises a current source using a low voltage depletion mode HEMT and resistor. The pull-down circuit 620e comprises a HEMT in threshold multiplier configuration.

[0475] FIG. 36 shows a schematic representation of a further embodiment the GaN chip 5000b of the proposed invention where the auxiliary gate block 810b comprises an enhancement mode low voltage HEMT. The current control block 830b comprises a current source using a low voltage depletion mode HEMT and resistor. The pull-down circuit 820b comprises a HEMT in threshold multiplier configuration which comprises a potential divider and a pull-down enhancement mode HEMT where the midpoint of the potential divider is connected to the gate terminal of the pull-down HEMT. In this embodiment, the top of the potential divider is connected to the active gate terminal rather than the drain of the pull-down enhancement mode HEMT as in previous embodiments.

[0476] In FIG. 37 the top of the potential divider is connected to the active gate terminal, the potential divider comprises a number of source-gate connected E-HEMTs in series 821c with the resistors shown in previous embodiments. While FIG. 37 shows two HEMT in series, a different number may be used. These HEMTs are one possible method to adjust the voltage level that is required to be reached on the active gate terminal before the pull-down enhancement mode HEMT becomes operational.

[0477] FIG. 38 shows another method for adjusting the voltage level required to be reached on the active gate terminal before the pull-down enhancement mode HEMT becomes operational. FIG. 38 utilises an additional HEMT in threshold multiplier configuration 821d.

[0478] FIG. 39 shows a schematic representation of a further embodiment the GaN chip 6000a of the proposed invention where the auxiliary gate block 910a comprises an enhancement mode low voltage HEMT. The current control block 930a comprises a current source using a low voltage depletion mode HEMT and resistor. The pull-down circuit 920a comprises a HEMT in threshold multiplier configuration which comprises a potential divider where the midpoint of the potential divider is connected to the gate terminal of the pull-down HEMT similar to previous embodiments. However, in this embodiment, the potential divider is connected to the external gate terminal rather than the gate terminal of the auxiliary transistor. In addition, a further HEMT in threshold multiplier configuration may be included between the gate and source terminal of the enhancement mode pull-down HEMT. This additional threshold multiplier acts to limit voltage on the gate terminal of the pull-down transistor. This additional threshold multiplier may alternatively be implemented using one or more diodes in series.

[0479] FIG. 40 shows a schematic representation of a further embodiment the GaN chip 6000b of the proposed invention where the auxiliary gate block 910b comprises an enhancement mode low voltage HEMT. The current control block 930b comprises a current source using a low voltage depletion mode HEMT and resistor. The pull-down circuit 920b comprises a pull-down enhancement mode HEMT with the gate connected to the output of a voltage divider similar to other embodiments. In this embodiment, the voltage divider is connected to the external gate terminal and consists of a current source and a HEMT in threshold multiplier configuration. The current source is implemented using a low voltage depletion mode HEMT and a resistor. The output of the voltage (potential) divider is the gate of the additional low-voltage HEMT.

[0480] In further embodiments, the gate of the pull-down HEMT may be controlled by an additional external signal, preferably through a VG to Vlogic regulator as described above, or by the output of an additional circuit integrated on the GaN device providing functions such as over-current protection, under-voltage lock-out, supply-voltage over-voltage protection, logic inverter or others.

[0481] In further embodiments, the exemplary GaN chip circuit 7000 illustrated in FIG. 69 may comprise one or several enable or disable functions to permanently or temporarily enable or disable the active HEMT, independent of the control signal applied. In FIG. 69, several exemplary embodiments are shown of enable or disable functions. With HEMT 595a, the disable function is realised as a HEMT across the pull-down circuit 520 limiting the voltage of the gate of the auxiliary gate.

[0482] HEMT 595b is integrated with the inverter driving the Miller clamp transistor 570. The inverter and HEMT 595b are forming a logic NAND function.

[0483] A third exemplary embodiment is shown in FIG. 69 where HEMT 595c is in series with the Miller clamp in a logic NAND connection, meaning that both the Miller clamp transistor and the disable transistor must be off to enable the gate voltage of the active GaN HEMT 500 to rise.

[0484] In a fourth exemplary embodiment, HEMT 595d is connected in parallel to the Miller clamp in a logic NOR connection, meaning that either the Miller clamp or the disable HEMT 595d may reduce the gate voltage of the active GaN HEMT 500.

[0485] A further embodiment of the invention is shown in FIG. 66 comprising a current control circuit 530 that is connected to a separate input (VINPUT2) than the auxiliary gate transistor. Further, in the same figure, the integration of a disable function 595e is shown in parallel to the pull-down circuit 520. While the disable function is active, the gate of the active GaN HEMT 500 is not affected by the input signal on the first additional terminal (VINPUT1). In this exemplary embodiment, the disable block 595e consists of an enhancement HEMT and a logic inverter allowing the application of a high signal to enable the turn-on of the device. The disable function 595e does not actively reduce (turn off) the gate of the active GaN HEMT 500. To do this, a Miller clamp transistor 570 as shown in FIG. 32 may be integrated. With the Miller clamp arrangement and disable function shown here, a gate driver functionality is realised in which the voltage on the first additional terminal (VINPUT1) may be kept constant and the disable and Miller clamp may control the gate of the active GaN HEMT 500.

[0486] A further embodiment of the invention is shown in FIG. 67 in which the current control block 530m is actively switched. In this embodiment, the control signal to the current control block stems from the enable and disable input. Compared to the arrangement in FIG. 66, the current is reduced when the disable function is active, reducing the current consumption when the device is disabled.

[0487] Another exemplary embodiment is presented in FIG. 68. The pull-down circuit 520k consists of a voltage source VDD3 and an enhancement HEMT with drain connected to the gate, as described earlier in this invention. An enable/disable circuit 595f is in parallel to the pull-down circuit as in FIG. 67. The current control block 530n in this embodiment contains an additional voltage drop where a voltage VDD2 is generated from the voltage at the first additional terminal (VINPUT1). The voltage drop between VINPUT1 and VDD2 is achieved through a voltage regulator 530na based on an embodiment of the gate interface circuit described in this invention. The current control block is actively controlled with a signal from the enable or disable terminal. The active control may be realised using a logic inverter driving the gate of a depletion HEMT 531 forming the current source. A logic inverter with more than one stage, as described earlier in this invention, may be used to drive the depletion HEMT 531. Additionally, an enhancement HEMT 532 is connected in parallel to the current source with the gate of the enhancement HEMT connected to an internal node of the current control block. This additional enhancement HEMT may provide an additional current path during the switching event when the disable function is released.

[0488] FIG. 41 illustrates an interdigitated device layout of a further embodiment of the disclosure incorporating an auxiliary gate structure. Many features of this embodiment are similar to those shown in FIG. 21 and therefore carry the same reference numerals, i.e., active gate terminal 10, low voltage source terminal 8, high voltage drain terminal 9, first additional terminal 16 and second additional terminal 12. Also shown in this illustration are the source pad metal 18, drain pad metal 19, and gate pad metal 20. However, in this embodiment, rather than the gate pad metal 20 being contacted to the gate fingers 10 directly as in a prior art device, it is connected to the auxiliary gate terminal 16. The gate fingers in the interdigitated structure are directly connected to the second additional terminal 12. Note that in this layout, as in the cross-sections in previous embodiments, an isolation layer exists between the 2DEG in the auxiliary gate and the active device. The additional operational blocks in this device are also illustrated: auxiliary gate block 510, pull-down circuit block 520, current control block 530. The connections of the different blocks can be made using interconnection metal layers 210.

[0489] FIG. 42 illustrates an interdigitated device layout of a further embodiment of the disclosure in which the auxiliary gate and terminal regions are placed below the source pad metal. Similarly, these circuits could be placed under the gate pad or the drain pad (not shown).

[0490] Many features of this embodiment are similar to those shown in FIG. 41 and therefore carry the same reference numerals, i.e., active gate terminal 10, low voltage source terminal 8, high voltage drain terminal 9, first additional terminal 16, second additional terminal 12, source pad metal 18, drain pad metal 19, gate pad metal 20, auxiliary gate block 510, pull-down circuit block 520, current control block 530, interconnection metal 210. However, in this embodiment, the auxiliary gate block, current control block and pull-down circuit block are placed below the source pad metal 18. Intermetal vias 220 can connect blocks at different metal layers in the process. Less additional wafer area would be needed to include the additional blocks compared to a prior art design. Note that in this illustration the additional blocks are placed under the source pad metal however this disclosure is intended to include designs where the additional blocks may be placed under other pads present in the integrated circuit layout.

[0491] FIG. 43 shows a block diagram of a further embodiment of the proposed disclosure where any of the embodiments of the GaN chip power device 35 are placed in a half-bridge configuration, where the external gates of the two power devices (both high and low side) are connected to gate driving blocks which are in turn connected to logic blocks. The different components and blocks included in the figure can be discrete components or connected monolithically. This demonstrates different examples of possible monolithic integration 36, 37, 38 while utilising the concept of the auxiliary gate.

[0492] FIG. 44 shows a circuit schematic representation of a further embodiment of the proposed disclosure where the GaN chip power device 35 according to this disclosure is connected in a standard three-phase half-bridge configuration.

[0493] FIG. 57 shows a schematic representation of an embodiment of the current control block 530k with a current reduction feature. To a conventional current source consisting of a depletion HEMT and resistive element, an additional enhancement mode HEMT is added, in parallel to the resistive element. Note that during off-state of the active GaN HEMT 500, the output of the current control block is at a low voltage, and in the on-state it is at a higher voltage. The gate of the additional enhancement mode HEMT is at a fixed voltage. Therefore, the resistance of the additional enhancement mode HEMT is higher in on-state than in off-state. This leads to the desired reduction of the current in the current control block during on-state of the active GaN HEMT 500. In addition, the gate of the additional HEMT can be actively controlled to further modulate the current level through the current control block. Further, the additional enhancement HEMT may be connected in parallel to the entire current source rather than only the resistive element.

[0494] FIG. 58 shows a similar embodiment of a current control block with a current reduction feature but using an additional depletion HEMT instead of an additional enhancement HEMT.

[0495] FIG. 45 shows a schematic representation of an embodiment of a shielding and/or decoupling structure. The purpose of shielding and/or decoupling structure is to reduce or eliminate the influence of one part of the chip, e.g. the active GaN device (main power HEMT), on a different part of the chip, e.g. the pull-down circuit, via electro-magnetic coupling. The shielding and/or decoupling structures can be below, above, on the sides or in the vicinity of either or both of the two parts of the chip. FIG. 45 shows an example shielding and/or decoupling structure 61, 62 situated laterally between two parts, or structures, 60, 66 of the chip. In this example, the decoupling structure comprises a plurality of 2DEG structures 61, 62. These 2DEG structures 61, 62 are connected to a controlled potential, e.g. to the first terminal of the active GaN device, through an ohmic contact layer 64 and operatively connected through vias 65 to other metal layers. Areas 60 and 66 may comprise arrangements of HEMTs, capacitive and resistive elements and electrical connections. Areas 60 and 66 may further be fully or partially shielded by layers above or below.

[0496] FIG. 70 shows a block diagram of a further embodiment of the disclosure with several GaN chip power devices. In this embodiment, the power devices 500a, 500b and the gate interfaces 8000a, 8000b share the low-voltage terminal (source). FIG. 70 shows how some of the external control or supply signals are connected to only one gate interface. Other control or supply signals are connected between several gate interfaces. This is the result of the blocks auxiliary gate circuit, pull-down circuit and current control-circuit or parts thereof being shared among the several main power devices for more compact solutions. For example, a voltage regulated on one gate interface block may be used directly in another gate interface block. This avoids duplication of sub-circuits and saves chip area.

[0497] FIG. 72 shows an example GaN chip 2500. In implementations of the pull-down circuits 520k and 5201 as shown in FIG. 48 and FIG. 49, the voltage VDD may not be a regulated voltage which is generated internally on the chip or applied externally. In some cases, the voltage VDD may be provided by the pull-down circuit itself.

[0498] When the gate terminal is high, a capacitor in the pull-down circuit may be charged from the gate terminal via a charging path (e.g. through the current control circuit 530). The magnitude of VDD may be set through the design of a threshold multiplier (e.g. as in pull-down circuit 520a) included in parallel to the pull-down circuit 520k illustrated in FIG. 48. As the gate terminal is not kept constantly high, but rather switches from high to low according to the required operation of the power HEMT 500, it may take a number of switching cycles to fully charge the capacitor in the pull-down circuit.

[0499] The VDD circuit generated may be used to power other blocks of the integrated circuit, for example inverter 560. This may remove the need for the VDD supply provided to the power integrated circuit (which in previous implementations has generally been provided externally or generated in other parts of the power integrated circuit). Alternatively, this internally generated VDD circuit may complement (in terms of the current) or replace an external VDD supply, and/or provide an alternative internal VDD rail for use if, for example, the external VDD rail is under a certain voltage value, which could cause the malfunction of the GaN chip 2500, and/or if the external VDD pin is not connected (i.e. it is floating).

[0500] The maximum voltage across the capacitor may be limited by the maximum voltage across the pull-down circuit.

[0501] In further implementation shown by GaN chip 2600 of FIG. 73, the internal voltage VDD may be additionally charged from an external high voltage node Vrail. The circuit 505 forms a second charging path for charging the capacitor of the pull down circuit 520, and comprises a high voltage depletion mode HEMT which can draw current from the high voltage node Vrail. The source of the depletion mode HEMT in circuit 505 is connected to VDD voltage node and the gate of the depletion mode HEMT is connected to the source of the power HEMT. When the capacitor of the pull down circuit 520 is charged via only the second charging path, the voltage across the capacitor is limited by an absolute value of a threshold voltage of the depletion mode HEMT.

[0502] An integrated resistor may be connected in series with the source as shown to control the maximum allowable current. This resistor may be e.g. a 2DEG resistor, and/or part of the depletion mode HEMT transistor itself.

[0503] When the gate is switching during normal operations, (in which the capacitor in the pull-down circuit is charged through the gate via the charging path) the voltage VDD may be designed to be at a value which is greater than the threshold voltage of the depletion mode HEMT. Under this condition, the Vgs for the depletion mode HEMT is more negative than its threshold voltage, and therefore the depletion mode HEMT is in the off-state and draws a negligible current.

[0504] When the gate is not switching or otherwise operating under normal conditions (e.g. during start-up, operating under no-load conditions, or in a standby mode), the voltage VDD that the capacitor is charged at, will drop until it reaches a value which is approximately equal to the threshold value of the depletion mode HEMT. Under this condition, the depletion mode HEMT will be in saturation and current can be drawn from the high voltage supply to power the circuit blocks which are connected to VDD (in this example the Miller clamp).

[0505] As the current is drawn from the high voltage supply, the load connected during this condition draws very little current, such that the power dissipation while these conditions are in place remain within any limits required by the intended use or design requirements.

[0506] The Vrail can be connected to a high voltage rail in the system (not shown) or alternatively could be connected to the drain terminal (Drain) of the power HEMT. In the latter case, there is no need for an additional pin or terminal connection for the Vrail.

[0507] The depletion mode HEMT may have a Schottky gate, or may have a p-GaN island gate as described in this application.

[0508] It may be desirable to maintain the operation of the Miller clamp during all conditions of the power integrated circuit so as to protect power HEMT 500 and the overall system, where the power integrated circuit is used from fast dV/dt transients.

[0509] FIG. 74 shows an example multi-stage inverter 560f. The first stage of the inverter comprises a current source 5603 and an enhancement mode HEMT 5604 similar to those implementations described above. The current source 5603 is not connected to voltage VCC but rather is connected to a level shifted version of VCC, as shown. The level shift may be achieved using source-gate connected HEMTs 5601, 5602.

[0510] The output of the first inverter stage is connected to the gate terminal of enhancement mode transistor 5607. The second stage of the inverter comprises an enhancement mode HEMT 5606, a capacitor 5605 and the enhancement mode HEMT 5607.

[0511] When the input to the multi-stage inverter is high the output of the first stage is low. HEMT 5606 is conductive under this condition, and so the output node of the inverter is low. HEMT 5607 is not conductive under this condition as Vgs=0V for this device. Capacitor 5605 is therefore charged through the source-gate connected HEMTs 5601 5602 to approximately VCC2*Vth.

[0512] With the absence of p-channel devices, it is challenging to achieve a fast transition of the output from low to high (i.e. pull-up) while minimising the power dissipation of the inverter in all conditions. Thus, in this implementation, a fast pull-up is achieved through capacitor 5605.

[0513] When the input to the multi-stage inverter 560f is low the output of the first stage is high. As the first stage output is connected to the gate of enhancement mode HEMT 5607 making it conductive, the output node of the inverter is held up through HEMT 5607.

[0514] FIG. 75 shows a circuit schematic of an implementation of a Vg to Vlogic circuit block 540a. Circuit block 540a comprises a current source and a group of enhancement mode transistors connected in series. The block 540a can receive a switching signal as an input (e.g. 12V, 0V) and output a switching signal which is limited in magnitude (e.g. 6V, 0V). The limit in the output magnitude of this circuit block may be designed or controlled by selecting the appropriate number of source-gate connected transistors (or drain-gate connected transistors).

[0515] FIG. 76 shows a circuit schematic of a further implementation of a Vg to Vlogic circuit block 540b. Circuit block 540b comprises a current source and a threshold multiplier. The block 540b can receive a switching signal as an input (e.g. 12V, 0V) and output a switching signal which is limited in magnitude (e.g. 6V, 0V). The limit in the output magnitude of this circuit block may be designed or controlled by selecting the appropriate ratio of the resistors in the potential divider of the threshold multiplier.

[0516] FIG. 77 shows a Vg to Vlogic circuit block 540c. This implementation is similar to circuit block 540b, but comprises an additional capacitor to enhance the speed of the circuit.

[0517] FIG. 78 shows a circuit schematic of another example Vg to Vlogic circuit block 540d. Circuit block 540d comprises a current source, an enhancement mode HEMT and a resistor. The gate of the enhancement mode HEMT is connected to fixed voltage VCC. The fixed voltage may be provided externally or be generated internally on the chip (e.g. as a VDD described above). The voltage output of block 540d is limited to a value of approximately VCC-Vth, the threshold voltage being the threshold voltage of the enhancement voltage HEMT. If the voltage on the output of the Vg to Vlogic circuit 540d exceeds this limit (i.e. is greater than VCC-Vth), then the enhancement mode HEMT will be in the off-state and the majority of the additional voltage applied across the input of the Vg to Vlogic circuit 540d will be dropped across the enhancement mode HEMT.

[0518] FIG. 79 shows a circuit schematic of an example DC/DC circuit block 550a. The DC/DC block 550a is formed of a linear voltage regulator which comprises a depletion mode HEMT connected in series between the input and the output of the linear voltage regulator. The circuit further comprises a current source and threshold multiplier. The threshold multiplier comprises an enhancement mode HEMT and a potential divider, where the midpoint of the potential divider is connected to the gate terminal of the enhancement mode HEMT. The top of the potential divider is connected to the output of the linear voltage regulator. Alternatively, the top of the potential divider could be connected to the gate of the depletion mode HEMT.

[0519] In another example (not shown) the depletion mode HEMT connected between the input and output of the linear voltage regulator may be replaced by an enhancement mode HEMT.

[0520] FIG. 80 shows a circuit schematic of a further example DC/DC circuit block 550b. The threshold multiplier in block 550a is replaced by a number of source-gate connected (or drain-gate connected) enhancement mode HEMTs connected in series.

[0521] In some of the implementations described above, the maximum internal rail voltage generated (VDD) may be limited by the maximum voltage across the pull-down circuit. The pull-down circuit is connected to the control terminal (i.e. external gate) through the auxiliary interface and the current control circuit, therefore the maximum voltage generated is limited by the regulated voltage generated by the auxiliary transistor, as well as being defined by the design of the current control block 530 and pull-down circuit block 520.

[0522] The pull down circuit may incorporate a HEMT in diode configuration connected to the capacitor (e.g. as shown in pull-down circuit 520k of FIG. 48) so that when zero volts, or a small voltage (for example below 1V), or a negative voltage is applied to the external gate terminal (i.e. in an off-state), the HEMT in diode configuration will be reversed biased and it will avoid the discharge of the capacitor. The resulting voltage drop across the pull-down circuit is the sum of the voltage level at the gate of auxiliary transistor and the voltage drop across the HEMT at the current level defined by the current control block. Pull-down circuit 520l (as illustrated in FIG. 49) similarly comprises a HEMT that is not in diode configuration, but rather in a threshold multiplier configuration using two resistive elements. Other examples include the use of non-linear elements in the threshold multiplier configuration. In all these embodiments, the VDD generated will be equal to or less than the regulated voltage level generated by the auxiliary transistor. When this VDD is applied to the inverter to operate the Miller clamp, the charge is shared with the capacitance Cgs of the Miller Clamp. This reduces the voltage applied to the gate of the Miller clamp to be lower than the VDD, which is limited to pull-down the inner gate (i.e. the gate of the main power HEMT 500) strongly.

[0523] In some implementations, an internal rail voltage generation circuit may be incorporated in the power integrated circuit. The internal rail voltage generation circuit may be provided independently, or may be a part of the pull-down circuit. The internal rail voltage generation circuit is provided with an additional input directly connected to the control terminal (i.e. an external gate terminal), that results in a higher VDD generation which can assist or facilitate the Miller clamp driver to turn-on the Miller Clamp strongly or more effectively in the linear region. This can lead to a faster pull-down of the inner gate, and/or reduce the resistance of the Miller Clamp. As used herein, two components and/or circuits being directly connected may mean that an electrically conductive path is provided between the two circuits or components, with no electrical circuits or components present on the conductive path between the two circuits or components other than the conductive path itself.

[0524] FIG. 81 depicts a block diagram of an example power integrated circuit comprising an internal rail voltage generation circuit 590. The internal rail voltage generation circuit 590 is connected between the control terminal and auxiliary gate circuit 510. The output of the internal rail voltage generation circuit 590 (VDD) is connected to a Miller clamp driver 560 that drives the Miller clamp transistor 570. The generated rail voltage VDD may also be used to power other circuits on or in the power integrated circuit, such as analog circuits.

[0525] FIG. 82 depicts a circuit schematic of an example internal rail voltage generation circuit 590a. The internal rail voltage generation circuit 590a comprises an enhancement mode HEMT 5202 and a capacitor 5203. The gate of the HEMT 5202 is connected to the gate of the auxiliary transistor, the drain of the HEMT 5202 is connected to the external gate (control terminal), and the source of the HEMT 5202 is connected to the capacitor. This configuration does not require any additional diode (or additional HEMT configured as a diode) to avoid the discharge of the capacitor when the external gate is low. Instead, in this example, if the regulated voltage generated at the internal gate is 6V then the voltage at the gate of the HEMT is 6V+Vth of the auxiliary HEMT. The voltage VDD generated at the capacitor will be 6V. Although this may be similar to the VDD generated in pull-down circuit 520k, the internal rail voltage generation circuit 590a will not affect the speed of charging the auxiliary gate while the example pull-down circuit 520k will. Here, it is assumed that the capacitance of capacitor 5203 is much smaller than the gate capacitance of main power HEMT (e.g. transistor 500 of FIG. 81), for example at least 50 times smaller. In an example, the capacitance of capacitor 5203 may be 50 to 100 times smaller than the capacitance of the main HEMT. Therefore, adding this capacitor will not affect the speed of charging the gate capacitance of the main HEMT which in effect will not affect the turn on of the main HEMT.

[0526] FIG. 83 shows an example Gallium Nitride (GaN) chip comprising an internal VDD generation block (e.g. internal rail voltage generation circuit 590a) connected to other circuit blocks. Such a GaN chip may also be referred to as a smart GaN power device or a GaN power or high voltage integrated circuit. While the Miller clamp driver 560 is depicted as an inverter in this example, it will be understood that any suitable Miller clamp driver may be used according to the needs and design requirements of the chip.

[0527] The GaN chip of FIG. 83 also comprises a pull-down circuit 520m. Pull-down circuit 520m comprises a HEMT 5204 in threshold multiplier configuration. The threshold multiplier configuration comprises a potential divider and a pull-down enhancement mode HEMT 5204, where the midpoint of the potential divider is connected to the gate terminal of the pull-down HEMT 5204. The top of the potential divider is connected to the drain of the pull-down enhancement mode HEMT 5202 and the gate terminal of the HEMT of the auxiliary gate block 510m. The pull-down circuit 520m may function as a voltage limiter, e.g. to limit the potential of the active gate terminal by pulling down the gate of the auxiliary gate transistor when the gate signal on the external gate terminal (i.e. the control terminal of the GaN chip) increases beyond a certain or threshold level.

[0528] Auxiliary gate block 510m comprises an enhancement mode low voltage HEMT as a first auxiliary transistor. Optionally, the auxiliary gate block may also incorporate a second auxiliary transistor (which may, for example, be a low-voltage transistor) connected in parallel with the first auxiliary transistor. The drain terminal of the first auxiliary transistor may be connected to the drain terminal of the second auxiliary transistor, and the source terminal of the first auxiliary transistor may be connected to the source (gate) terminal of the second auxiliary transistor, in a similar or same design as shown in auxiliary block 510e of FIG. 29.

[0529] FIG. 84 shows a further example internal rail voltage generation circuit 590b. In this implementation, a constant current source 5205 and a diode 5206 are connected in series to the external gate. The mid-point of the current source and the anode of the diode are connected to the gate of a transistor 5202, while the cathode of the diode is connected to the gate of the auxiliary transistor. The drain of the HEMT 5202 is connected to the external gate, and source of the HEMT 5202 is connected to the capacitor 5203. Other circuits such as pull-down circuit, current control, Miller clamp, inverter (Miller clamp driver) etc. may also be provided, but are not shown here for simplicity and clarity.

[0530] In the internal rail voltage generation circuit 590b, if the regulated voltage generated at the internal gate is 6V then the voltage at the gate of the auxiliary HEMT is 6V+Vth of the auxiliary HEMT and the voltage at the mid-point of the current source and the diode is 6V+2Vth (assuming Vth of the diode is equal to the Vth of the auxiliary HEMT). Eventually, VDD generated at the capacitor will be 6V+Vth. This is higher than in the internal rail voltage generation circuit 590a, and when this is applied to the Miller clamp driver (e.g. inverter 560), the gate of the Miller Clamp will see at least 6V or more in this example. This will result in an effective turn-on of the Miller clamp and in a stronger pull down of the inner gate. This design may therefore enhance the efficiency of operation of the Miller Clamp and remove the requirement for higher VDD supply from external sources.

[0531] FIG. 85 illustrates another example GaN chip comprising the further example internal rail voltage generation circuit 590b, pull-down circuit 520n and auxiliary gate block 510n. It will be understood that discussions above relating to pull-down circuit 520m and auxiliary gate block 510m apply equally to pull-down circuit 520n and auxiliary gate block 510n, respectively.

[0532] FIGS. 27-30 illustrate the implementation of current control block comprising a current source using a low voltage depletion mode HEMT and a resistor. FIG. 86 shows a similar example voltage independent current source 5301, corresponding to the current source incorporated in the current control block 530d in FIG. 28. In this design, a depletion mode HEMT D1 and a resistor R are employed to generate a voltage independent current source from the VDD. This current depends on the Vgs of the D-HEMT D1, and the resistor R. The current through this current source (I_D1) is varied by the channel modulation of the depletion mode HEMT (D1), and the Vds of D1 is varied by VDD. The use of channel modulation means the drain current may be increased by a drain voltage increment across D1. When VDD increases, the Vds of D1 increases resulting in the Vgs of D1 becoming more negative to maintain the same current. This increases the voltage across the resistor and increases the current, and is the cause of channel modulation in the current source incorporated in the current control block 530d.

[0533] FIG. 87 shows an example of a supply independent current source 5302 that can be implemented with current control blocks or any other circuit blocks where a current source is required such as logic signal clamping circuit, DC to DC converter block, logic inverter, multi-stage inverter circuit, pull-down circuit, decoupling circuit etc. For example, the current source 5302 may be used as the current source 5205 and/or as a current source for or in current control block 530. In this implementation, and relative to current source 5301 shown in FIG. 86, another D-HEMT D2 (12V) is placed at the top of the first D-HEMT D1 in a cascode configuration. In the cascode D-HEMT current source 5302, the current is still defined by I_D1, but the Vds of D1 is determined by the Vgs of D2 instead of VDD. This current source 5302 can therefore reduce the channel modulation effect by up to five times compared to current source 5301. As such, the application of current source 5302 in a voltage regulator can help to reduce or minimize the dependence of the regulator's output voltage on VDD. For example, in a voltage regulator, the voltage across a current source is generally from 1V to 12V. If the current source has high channel modulation effect, this increment in current will increase the internal gate voltage (also called VGI or the gate voltage of the main power transistor). This means that the overall VGI variation becomes bigger, and causes the yield loss. Thus, by reducing the channel modulation effect, the yield loss may be reduced.

[0534] Additionally, where two current sources are provided, the use of two current sources designed according to the principles of current source 5302 can help to reduce or minimize their mismatch due to differences in their Vds.

[0535] In some cases, it may be desirable or advantageous to provide a current source with temperature compensation. The addition of a temperature compensation current source to a voltage regulator circuit can help to reduce the temperature induced variation of the gate voltage of the main power transistor. Traditional methods of temperature compensation use a combination of SiCr and 2DEG resistors. In these methods, the ratio of the SiCr and 2DEG resistors in a potential divider is tuned to tune the temperature coefficient of internal gate voltage. However, a skew between the 2DEG and SiCr resistor can lead to possible yield loss.

[0536] FIG. 88 illustrates a further current source circuit 5303. Relative to current source 5301, current source circuit 5303 comprises an additional current source connected in series with the first current source (i.e. current source 5301). This additional current source incorporates depletion mode transistor D3 with an SiCr resistor R_SiCr connected to its source. The resistor R_SiCr makes this current source function as a temperature compensated current source. It will be understood that the resistor materials described above are merely provided as examples, and in general the resistor R_SiCr and the first resistor R may be any two resistors with different thermal coefficients. While the two current sources of the current source circuit 5303 are shown connected in series, in implementations they may instead be connected in parallel.

[0537] FIG. 89 illustrates an example voltage regulator circuit comprising the temperature compensated current source 5303 in the current control block 530p. The temperature compensation current source 5303 sinks a higher percentage of the biasing current to the pull-down transistor in the pull-down circuit 520p at higher temperatures. Thus, the VGI will be lower at a high temperature, such that the temperature coefficient of VGI can be tuned based on the requirements and needs of a particular chip design or intended use.

[0538] FIG. 90 illustrates another example a voltage regulator circuit comprising an alternative temperature compensated current source circuit as part of the current control block 530q. In contrast to the series connected temperature compensated current sources provided in current control circuit 530p, the current sources in current control circuit 530q are connected in parallel.

[0539] High power applications such as industrial motor drives, data center power, electric vehicle powertrains, renewable energy, avionics, factory automation, lighting, and medical devices etc. may require switches with high power density and efficiency. This increases a need of GaN power devices with reduced Ron (on-state resistance). However, lower Ron devices may come at the cost of larger die sizes and higher parasitics. Larger die designs can face multiple challenges such as the need for more complex interconnects and wire bonds in packaging, higher capacitances and inductances, and slower switching speeds. If the active device is broken into multiple smaller cells or sub-transistors that are laid out across the die and connected in parallel, then each unit cell may be configured to handle a fraction of the total current. Thus, it will be understood that the power transistors described herein may be distributed into a plurality of main sub-transistors. In such an implementation, the auxiliary HEMT and Miller clamp transistor may also be distributed into a plurality of auxiliary sub-transistors and a plurality of Miller clamp sub-transistors. FIGS. 91, 92 and 93 show various example distributed transistors.

[0540] The distribution of the Miller Clamp and auxiliary HEMTs may facilitate the provision of auxiliary sub-transistors and Miller clamp sub-transistors in close proximity to their respective main sub-transistor. This can provide for a more optimized layout and metal routing, with reduced or minimized loop inductance and parasitic hotspots. Each small cell comprises a main sub-transistor along with its auxiliary sub-transistor and Miller clamp sub-transistor, and can individually operate with lower gate and output capacitances. Further, this approach can make the overall device completely modular and scalable. Therefore, instead of resizing auxiliary HEMTs and Miller clamp transistors for different die sizes, some implementations may comprise multiple distributed cells that can be added/removed to scale with the die size and number of fingers tailoring performance to specific applications (e.g., high-efficiency vs high-power). In some examples, the device may comprise one or more central cells to which the distributed cells are added/removed.

[0541] In FIG. 91, the respective drain terminals and the source terminals of the plurality of main sub-transistors (500_1, 500_2, etc.) are connected to each other to form the drain and source terminal of the power HEMT, respectively. However, the gate terminal of each main sub-transistor (500_1, 500_2, etc.) is connected to the second terminal of respective auxiliary sub-transistor (510_1, 510_2, etc.) while the first terminal of the auxiliary sub-transistors (510_1, 510_2, etc.) are connected together to the control terminal. Similarly, the gate terminal of each main sub-transistor is connected to the drain terminal of the respective Miller clamp sub-transistor (570_1, 570_2, etc.).

[0542] The gates of the auxiliary sub-transistors (510_1, 510_2, etc.) may be connected together to a common pull-down circuit or individually to a distributed pull-down circuit with one sub-block for each auxiliary sub-transistor. Similarly, the Miller clamp sub-transistors may be driven by a single Miller clamp driver or alternatively the Miller clamp driver may also be distributed. FIG. 92 depicts an example circuit schematic with a common pull-down circuit and a common Miller clamp driver, while FIG. 93 depicts an implementation with distributed pull-down circuits and Miller clamp drivers. However, it will understood that the distributed transistors may be provided with e.g. a common pull-down circuit and distributed Miller clamp drivers, or vice versa. The Miller Clamp drivers may be connected to the control terminal through logic signal clamping circuits as illustrated in previous embodiments. Other circuit blocks may optionally be provided but are not shown for simplicity and clarity. Any other circuit blocks may also be distributed or common. Optionally, the Miller clamp driver (or drivers when distributed) may be provided with an external or internal VDD. Where the Miller clamp drivers are distributed, each driver may be provided with an individual VDD, or all Miller clamp drivers may share a single VDD.

[0543] It will be appreciated that the auxiliary transistor described above in relation to all the embodiments can be a low voltage transistor or a high voltage transistor.

[0544] It will also be appreciated that terms such as top and bottom, above and below, lateral and vertical, and under and over, front and behind, underlying, etc. may be used in this specification by convention and that no particular physical orientation of the device as a whole is implied.

[0545] Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure, which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

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