Semiconductor device with self-aligned channel and self-aligned contact region, and method of preparing the same

Abstract

A semiconductor device and method of making is described. A substrate (1) topped by a buffer layer (2) of a first conductivity type and one or more epitaxial layers (3) of the same type. In the topmost epitaxial layer, a body region (4) of a second conductivity type is formed, along with a source region (5) of the first conductivity type. Beneath the source region lies a buried body contact region (6) of the second conductivity type. A trench (16) in the source region provides access to the body contact region and is narrower than it. Ohmic contacts include a source contact (9) overlapping the source region on trench sidewalls and a body contact (10) overlapping the body contact region at the trench bottom. Between body regions of neighboring cells, a JFET region (13) is formed.

Claims

1. A method to make a semiconductor device having a source region self-aligned with a body region and a body contact region self-aligned with the body region, comprising 1) providing a semiconductor substrate; 2) depositing a semiconductor buffer layer of a first conductivity doping type on the semiconductor substrate; 3) depositing one or more semiconductor epitaxial layers of the first conductivity doping type on the buffer layer and forming a drift layer; 4) forming through depositing or growing a thin layer (M0) on a topmost epitaxial layer, wherein the said thin layer (M0) is configured to adjust profiles of implanted ions and to protect the topmost epitaxial layer; 5) depositing and patterning a first hard mask material to produce a first hard mask (M1), wherein the first hard mask has a thickness to block the implanted ions; 6) forming a body region of a second conductivity doping type by ion implantation, using the first hard mask (M1) as a mask; and forming Junction Field-Effect Transistor (JFET) regions between the body regions of neighboring cells; 7) depositing a second hard mask material on top of the first hard mask (M1) and the thin layer (M0); 8) etching the second hard mask material to create a second hard mask (M2) as a spacer mask on sidewalls of the first hard mask (M1), a width of the spacer mask equals a thickness of the deposited second hard mask material; 9) forming a source region of the first conductivity doping type by ion implantation, using the first hard mask (M1) and the second hard mask (M2), making the source region self-aligned with the body region, creating a channel between the JFET region and the source region at a shallow depth in the body region; 10) forming a body contact region of the second conductivity doping type by ion implantation, wherein the body contact region and the source region are vertically aligned, each being laterally positioned in accordance with inner edges of the second hard mask (M2); wherein the channel between the JFET region and the source region in the body region is vertically aligned with second hard mask (M2), said vertical alignments are achieved essentially through the use of the first hard mask (M1) and the second hard mask (M2); 11) removing the thin layer (M0), the first hard mask (M1) and the second hard mask (M2) by wet etching or dry etching with high selectivity to the semiconductor material; 12) activating the implanted ions, forming a gate insulator, forming a gate and forming an interlayer dielectric enclosing the gate; 13) etching an ohmic contact via in the interlayer dielectric using a contact mask and using the same contact mask to etch a trench in the source region to access the body contact region; 14) removing the contact mask and depositing an ohmic metal layer on top and sidewalls of the interlayer dielectric and on bottom and sidewalls of the semiconductor trenches; 15) annealing the ohmic metal using a first contact annealing process to form a self-aligned metal and semiconductor alloy on the trench bottom and sidewalls; 16) removing the unalloyed ohmic metal from the interlayer dielectric and semiconductor, leaving the metal and semiconductor alloy intact, and annealing the metal and semiconductor alloy using a second contact annealing process to achieve final properties of ohmic contacts; source contact defined by an overlap of the alloy with the source region on the sidewalls of the semiconductor trenches, body contact defined by an overlap of the alloy with the body contact region on the bottom of the semiconductor trenches; 17) processing the semiconductor device, including etching a gate contact via, depositing and patterning front side metallization, depositing and patterning passivation, and forming backside metallization.

2. The method of claim 1, wherein the substrate is selected from silicon carbide, silicon, gallium nitride, gallium oxide, diamond or aluminum nitride.

3. The method of claim 2, wherein the substrate has a first conductivity doping type, which is the same as the doping type of the buffer layer and the one or more semiconductor epitaxial layers.

4. The method of claim 2, wherein the substrate has a second conductivity doping type, which is opposite to the doping type of the buffer layer and the one or more semiconductor epitaxial layers.

5. The method of claim 1, wherein the first hard mask material and the second hard mask material are selected from a group consisting of silicon dioxide, silicon nitride and polysilicon, or any combination of them.

6. The method of claim 1, further comprising controlling a width of the spacer by controlling a thickness of the deposited second hard mask material, controlling the channel length by the spacer width.

7. The method of claim 1, wherein the body contact region is buried below the source region, wherein the implantation of the body contact region does not affect the electrical properties of the source contact on the source region.

8. The method of claim 1, further comprising forming the trench narrower than the body contact region.

9. The method of claim 1, wherein the substrate, buffer layer and epitaxial layers are silicon carbide, the first conductivity doping type ions are nitrogen or phosphorous, the second conductivity doping type ion is aluminum and the ohmic metal is nickel, aluminum, titanium or their compounds.

10. The method of claim 1, wherein the substrate, buffer layer and epitaxial layers are silicon carbide, the first conductivity doping type ion is aluminum, the second conductivity doping type ions are nitrogen or phosphorous and the ohmic metal is nickel, aluminum, titanium or their compounds.

Description

DESCRIPTION OF DRAWINGS

(1) In order to further illustrate the technical solutions of embodiments of the present disclosure, various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In the illustrated drawings, the elements are a substrate (1); a buffer layer (2); one or more more epitaxial layers (3); a body region (4); a source region (5); a body contact region (6); a gate insulator (7); a gate (8); a source contact (9); a body contact (10); an interlayer dielectric (11); top metallization (12); a JFET region between the body regions of neighboring cells (13); a self-aligned channel (14) between the source region (5) and the JFET region (13) at a shallow depth in the body region (4) bottom metallization (15); a thin layer (M0); a first hard mask (M1); a second hard mask (M2); a source electrode (S); a drain electrode (D); and a gate electrode (G).

(2) FIG. 1 is a schematic diagram depicting a cross-sectional view of a device structure of the present invention.

(3) FIG. 2 is a schematic illustration of a structure formed out of an initial substrate for the semiconductor device manufacturing process, beginning with the preparation of a substrate layer (1), followed by the deposition of a buffer layer (2) of the first conductivity doping type, and then the deposition of one or more epitaxial layers (3) of the first conductivity doping type.

(4) FIG. 3 is a schematic illustration of forming a thin layer (M0) for the adjustment of ion implantation profiles and protection of the topmost epitaxial layer, and of forming a first hard mask (M1) for the selective implantation of a body region with ions of the second conductivity doping type.

(5) FIG. 4 is a schematic illustration of depositing the second hard mask material on top of the first hard mask (M1) and thin layer (M0).

(6) FIG. 5 is a schematic illustration of etching the second hard mask material to form a second hard mask (M2) on sidewalls of the first hard mask, along with the implantation of a source region (5) of the first conductivity doping type self-aligned with the body region (4).

(7) FIG. 6 is a schematic illustration of using the first and second hard masks (M1 and M2) as masks for the implantation of a body contact region (6) of the second conductivity doping type self-aligned with the body region (4) and the source region (5).

(8) FIG. 7 is a schematic illustration of a structure formed after the removal of all masks, M0, M1 and M2.

(9) FIG. 8 is a schematic diagram depicting a cross-sectional view of a device after the formation of a gate insulator (7), a gate (8), and an interlayer dielectric (11) enclosing the gate.

(10) FIG. 9 is a schematic illustration of etching an ohmic contact via in the interlayer dielectric (11) and further etching a trench (16) in the source region (5) to access the body contact region (6).

(11) FIG. 10 is a schematic diagram depicting a cross-sectional view of a device structure with a deposited ohmic metal layer on top and sidewalls of the interlayer dielectric (11) and on bottom and sidewalls of the semiconductor trench (16).

(12) FIG. 11 is a schematic illustration of forming a source contact (9) on the source region (5) on the sidewalls of the semiconductor trench (16) and forming a body contact (10) on the body contact region (6) on the bottom of the semiconductor trench (16).

(13) FIG. 12 is a schematic diagram depicting a cross-sectional view of the device after frontside metallization (12) and backside metallization (15).

(14) FIG. 13 is an illustration of exemplary doping profiles.

(15) FIG. 14 is an illustration showing that the body contact region (6) can be deeper than the body region (4).

(16) FIG. 15 is a schematic illustration of a trench (16) indenting into the body contact region (6), dividing the source region (6) into two parts, where the body contact (10) is located on the bottom and sidewalls of the semiconductor trench (16).

(17) FIG. 16 is a schematic illustration showing that the trench (16) can indent into the body contact region (6), whose depth is bigger than the depth of the body region (4).

(18) FIG. 17 is a schematic illustration of the basic elementary cell structure of a comparative semiconductor device.

(19) FIGS. 18-22 are schematic diagrams depicting a cross-sectional view showing the formation of the comparative semiconductor device of FIG. 17.

(20) FIG. 18 is a schematic illustration of forming a first hard mask (M1) on top of a thin layer (M0), along with a selective implantation of a body region (4), to produce the comparative semiconductor device.

(21) FIG. 19 is a schematic illustration of depositing the second hard mask material on top of the first hard mask (M1) and thin layer (M0), to produce the comparative semiconductor device.

(22) FIG. 20 is a schematic illustration of etching the second mask material to form a second hard mask (M2) on the sidewalls of the first hard mask, along with the ion implantation of the source region (5) self-aligned with the body region (4), to produce the comparative semiconductor device.

(23) FIG. 21 is a schematic diagram illustrating the implantation of the body contact region (6), to produce the comparative semiconductor device.

(24) FIG. 22 is a schematic illustration showing the presence of a parasitic body diode in a device structure and polarization of the electrical voltage over the diode in forward and blocking states for an n-type device.

(25) FIG. 23 is a schematic illustration of a minimum spacing between the source regions (5) of the comparative semiconductor device, where the spacing equals a sum of a minimum feature size for the first hard mask M1 (L1) and a double channel length (spacer width, C), spacing=L1+2C.

(26) FIG. 24 is a schematic illustration of a minimum spacing between the source regions (5) of the invented semiconductor device, where the spacing equals the minimum feature size L2 for the trench and ohmic metal processes, L2 being significantly smaller than L1+2C.

DESCRIPTION OF EMBODIMENTS

(27) One object of the invention is to present a device elementary cell with a reduced pitch, enabling a higher density of cells within an integrated device. This increased cell integration results in reduced device resistance and power losses. Alternatively, it allows for the usage of a smaller semiconductor area in device fabrication, reducing the overall device cost, which is particularly beneficial for expensive silicon carbide technology.

(28) The invention incorporates three self-aligned processes for the formation of a channel, a body contact region and an ohmic contact, which reduces the number of fabrication steps and lowers the device manufacturing cost.

(29) The term self-aligned channel process refers to a technique where the source and body regions of a transistor are aligned with each other utilizing just one and the same photolithography mask.

(30) The term hard mask refers to a mask produced from a material which can withstand processing at elevated temperatures, typically the temperatures above the graphitization point of organic layers, e.g. a photoresist. The common materials are silicon nitride, silicon dioxide and polysilicon.

(31) The terms M1 and M2 refer to specific masks used in the process.

(32) The term contact mask indicates a mask used specifically for creating the contacts, which are the regions touching the semiconductor and having the electrical connection with a source electrode.

(33) Further the semiconductor device structure made using the process disclosed in the present invention is characterized by the body contact region buried below the source region; the source region i-split in two parts by a trench in order to access the buried body contact region; the source contact overlapping the source region on trench sidewalls and the body contact overlapping the body contact region on trench bottom or on trench bottom and sidewalls and no source and body contacts on top semiconductor surface.

(34) The invention can be applied to fabrication of semiconductor devices, e.g. MOSFET, IGBT, Superjunction MOSFET. The invention can be applied to different semiconductor materials, e.g. silicon carbide, silicon, gallium nitride, gallium oxide and aluminum nitride. The invention can be applied to semiconductor devices using a different shape of elementary cell, e.g. stripes, squares and hexagons. Power devices using the invention find an application in energy conversion. Typical power electronics applications, which may benefit from the invention, are electric vehicle (EV) traction inverter, EV charger and EV on-board charger, data center, motor drives, rolling stock inverters, solar inverters, consumer power electronics.

(35) In accordance with the first aspect of the invention, a method to make a semiconductor device is disclosed.

(36) The method disclosed herein is a multistep process. The description provided is intended to thoroughly explain the invention, but it does not imply that the invention must include all the steps described. Individual steps or groups of steps can be used independently or in combination with other steps to achieve the desired outcome, depending on the specific application or embodiment of the invention. This flexibility allows the invention to be adapted to various contexts while maintaining its core functionality and benefits.

(37) 1. Providing a Substrate

(38) Referring to FIGS. 1-7, the method comprises a step, or step 1, of providing a semiconductor substrate; the substrate is selected from silicon carbide, silicon, gallium nitride, gallium oxide, aluminum nitride or another semiconductor material. The conductivity doping type for the substrate can be either an n-type doping or a p-type doping.

(39) In one embodiment, wherein the semiconductor substrate has a first conductivity doping type; the substrate is selected from silicon carbide, silicon, gallium nitride, gallium oxide, aluminum nitride or another semiconductor material. The first conductivity doping type for the substrate can be either an n-type doping or a p-type doping. In one instance, the first conductivity doping type is n-type doping. In another instance, the first conductivity doping type is p-type doping.

(40) In the scope of the present invention, n-type doping involves adding elements that have more valence electrons than the semiconductor material (e.g., phosphorus, arsenic in silicon), resulting in an excess of free electrons, which are the majority charge carriers. This makes the semiconductor conductive by electrons.

(41) In the scope of the present invention, p-type doping involves adding elements that have fewer valence electrons than the semiconductor material (e.g., boron, aluminum in silicon), creating holes (absence of electrons) which act as positive charge carriers. This makes the semiconductor conductive by holes.

(42) 2. Forming a Buffer Layer

(43) The next step, step 2 of the method, comprises depositing a semiconductor buffer layer of the first conductivity doping type onto the substrate. This deposition is carried out using homoepitaxy, meaning that the substrate and the buffer layer are composed of the same material.

(44) 3. Depositing One or More Semiconductor Epitaxial Layers

(45) Following that, step 3 of the method comprises depositing one or more semiconductor epitaxial layers of the first conductivity doping type onto the buffer layer. This deposition is also performed using homoepitaxy, ensuring that the buffer layer and the epitaxial layers are made of the same material. The layer that bears the majority of the blocked voltage is referred to as the drift layer. In the scope of the present invention, the method comprises depositing a substrate, a semiconductor buffer layer and one or more epitaxial layers of the same material.

(46) 4. Growing a Thin Layer (M0)

(47) Another step, or the step 4, of the method is depositing or growing a thin layer (M0) on a topmost epitaxial layer; wherein the said thin layer (M0) is configured to adjust profiles of implanted ions, for example to scatter the implanted ions or to set a peak dopant concentration at near-surface depths; and to protect the topmost epitaxial layer during patterning the masks M1 and M2.

(48) 5. Patterning the First Hard Mask Material to Produce a First Hard Mask (M1)

(49) A further step, or the step 5, of the method is depositing and patterning the first hard mask material to produce a first hard mask (M1); the first hard mask material can be for example silicon dioxide, silicon nitride, polysilicon, or any combination of them; the thickness of the deposited hard mask material must be chosen to block the implanted ions; the first hard mask (M1) is produced by patterning the first hard mask material, typically by the photolithography and dry etching.

(50) 6. Forming the Body Region of the Second Conductivity Doping Type

(51) A further step, or the step 6, of the method is using the first hard mask (M1) as a mask to form the body region of the second conductivity doping type by ion implantation. The regions between the body regions are named the JFET (Junction Field-Effect Transistor) regions. In contrary to a photoresist mask, a hard mask enables processing at elevated temperatures, e.g. the ion implantation (typically around 500 C.) or deposition of another layer on top of the mask. Furthermore, a range of implanted ions in a hard mask is typically smaller than in a photoresist mask, which enables usage of higher ion implantation energies.

(52) 7. Depositing a Second Hard Mask Material on Top of the First Hard Mask (M1)

(53) A further step, or the step 7, of the method is depositing a second hard mask material on top of the first hard mask (M1) and the thin layer (M0). The first hard mask material can be for example silicon dioxide, silicon nitride, polysilicon, or my combination of them. A variety of processes, which could be used for the deposition, includes, but is not limited to LPCVD (low pressure chemical vapor deposition) and PECVD (plasma enhanced chemical vapor deposition). In one preferred embodiment, LPCVD is used, which offers good layer thickness conformity. It means that the thickness of the deposited second hard mask material is substantially the same on the top (mesa) of the hard mask M1, on the top of the layer M0 (bottom of trench-etched in the hard mask M1) and on the sidewalls of the hard mask M1.

(54) 8. Etching the Second Hard Mask Material to Create a Second Hard Mask (M2)

(55) Referring to FIG. 5, a further step, or step 8, of the method is etching the second hard mask material to create a second hard mask (M2) on the sidewalls of the first hard mask. This process is a spacer formation process. The spacer mask (the second hard mask M2) is formed on the sidewalls of the first hard mask M1, while the second hard mask material is removed from the top of the first hard mask M1 and from the top of the layer M0. Upon using a LPCVD for the second hard mask material deposition, the width of the spacer is precisely controlled in a manner that the width of the spacer equals the thickness of the deposited second hard mask material.

(56) 9. Forming a Source Region

(57) Referring to FIG. 5, a further step, or step 9, of the method is forming a source region of the first conductivity doping type by ion implantation, using the first hard mask (M1) and the second hard mask (M2), making the source region self-aligned with the body region, creating a channel between the JFET region and the source region at a shallow depth in the body region. The channel length is defined by and equal to the spacer width, therefore comprising controlling a width of the spacer by controlling a thickness of the deposited second hard mask material, controlling the channel length by the spacer width.

(58) 10. Forming a Body Contact Region

(59) Referring to FIG. 6, a further step, or step 10, of the method is forming a body contact region of the second conductivity doping type by ion implantation, using the first hard mask (M1) and the second hard mask (M2), making the body contact region self-aligned with the body region and with the source region; the body contact region is self-aligned on the source region, so it is also self-aligned on the body region. The width of the body contact region is inherited or substantially the same as the width of the source region due to using the same masks M1 and M2 for the ion implantation. The only little difference in width of both regions could be due to different lateral scattering of the opposite conductivity doping type ions implanted with different energies and doses. The implantation energy and dose for the body contact region must be chosen in order to bury that region below the source region and not to affect the electrical properties of the source contact on the source region.

(60) 11. Removing all the Masks and Layers M2, M1 and M0

(61) A further step, or step 11, of the method is to remove all the masks and layers M2, M1 and M0, as depicted in FIG. 7. The masks are removed by wet etching or dry etching with very high selectivity to the semiconductor material.

(62) 12. Continuing a Standard FET Process Flow

(63) Another further step, or step 12, of the method is to continue the process according to a standard FET (Field-Effect Transistor) process flow, including steps such as post-implantation annealing, formation of an active area oxide, formation of gate insulator (7), formation of a gate (8), and deposition of an interlayer dielectric (11), as shown in FIG. 8.

(64) 13. Etching an Ohmic Contact Via and Etching a Trench in the Source Region

(65) Another further step, or step 13, of the method is to etch an ohmic contact via using a contact mask and use the same contact mask to etch a trench in the source region to access the body contact region. The trench is narrower than the body contact region, along the lateral direction of the cell, opposite to the etching direction or the depth direction of the cell.

(66) 14. Deposition of Ohmic Metal

(67) A further step in the method, step 14, involves removing the contact mask and depositing an ohmic metal layer on the top and sidewalls of the interlayer dielectric and on the bottom and sidewalls of the semiconductor trench, as illustrated in FIG. 10. The term ohmic metal refers to a metal that forms an ohmic contact with the semiconductor material, enabling current to flow easily in both directions with minimal resistance and without rectification. Achieving an effective ohmic contact is crucial for making efficient, low-resistance connections between the metal electrodes and the semiconductor.

(68) In the scope of the present invention, achieving an ohmic contact depends on factors like the choice of metal, the work function of the metal relative to the semiconductor, the doping level of the semiconductor, and the post-deposition thermal treatment. In one embodiment, nickel and nickel-based alloys are selected for their ability to form reliable ohmic contacts, particularly with silicon carbide.

(69) 15. First Contact Annealing Process

(70) A further step, or step 15, of the method is annealing the ohmic metal using a first contact annealing process to alloy it with the semiconductor and to form a self-aligned alloy on the trench bottom and sidewalls.

(71) Annealing the ohmic metal using the first contact annealing process serves to alloy the metal with the underlying semiconductor material, facilitating the formation of a stable and low-resistivity contact. The alloyed metal and semiconductor layer is formed in a self-aligned manner on the trench bottom and sidewalls, meaning that the alloy forms precisely where the metal and semiconductor are in contact, without the need for additional masking or alignment steps. This self-alignment ensures that the alloy is positioned exactly where it is needed.

(72) 16. Removal of Unalloyed Metal and Second Annealing Process

(73) A further step, step 16 of the method is removing the unalloyed ohmic metal from the interlayer dielectric and semiconductor, leaving the metal and semiconductor alloy intact, and annealing the metal and semiconductor alloy using a second contact annealing process to achieve final properties of ohmic contacts; source contact defined by an overlap of the alloy with the source region on the sidewalls of the semiconductor trench, body contact defined by an overlap of the alloy with the body contact region on the bottom of the semiconductor trench.

(74) In step 16, the unalloyed ohmic metal is removed from the interlayer dielectric and semiconductor, leaving the metal alloy intact. The remaining metal alloy is then subjected to a second contact annealing process to achieve the final properties of the ohmic contacts. This process defines the source contact by the overlap of the alloy with the source region on the sidewalls of the semiconductor trench, and the body contact by the overlap of the alloy with the body contact region on the bottom of the semiconductor trench. The steps 14-16 together constitute a third self-aligned process, the self-aligned ohmic metal process.

(75) The steps 14-16 require two annealing steps, where the first one is to form the alloy of metal with semiconductor and the second one is to get ohmic contact properties. Between the two annealing steps, the unalloyed metal is removed from the structure there formed. In the invention, the metal alloy is formed on the trench bottom and sidewalls.

(76) 17. Final Device Processing

(77) A further step, step 17 of the method, is processing the semiconductor device, including etching a gate contact via, depositing and patterning front side metallization, depositing and patterning passivation, and forming backside metallization.

(78) The process is distinct from prior art, such as that from GeneSiC of comparative example 2, as it enables a smaller device structure by burying the body contact region below the source region in one self-aligned process and by eliminating the ohmic contacts on the semiconductor surface.

(79) 18. Continuation with Standard FET Process Flow

(80) A further step 18 of the method is to continue the process according to the standard FET process flow, including steps such as etching a gate contact via, depositing, and patterning front side metallization (12), depositing and patterning passivation, and forming backside metallization (16), as shown in FIG. 17.

(81) Etching Gate Contact Via

(82) The process begins with etching a gate contact via. This involves precisely removing material to create a pathway that will later be filled with the from side metallization, establishing the electrical connection to the gate of the FET. This step is crucial for defining the control terminal of the transistor, which regulates the flow of current through the device.

(83) Front-Side Metallization

(84) Following the gate contact etching, front-side metallization is carried out. In this step, metal layers are deposited and patterned on the front side of the wafer to form electrical connections to the source and gate.

(85) Passivation

(86) After front-side metallization, passivation layers are deposited. Passivation involves covering the semiconductor surface with protective dielectric layers, which serve multiple purposes: they protect the device from environmental contamination, reduce surface states that could affect device performance, and enhances the overall reliability of the FET.

(87) Backside Metallization

(88) Finally, backside metallization is performed. This step involves depositing a metal layer on the backside of the wafer, which is done to form the drain contact of the FET. The backside metal provides a robust, low-resistance connection, ensuring efficient current flow through the device during operation.

Comparative Example 1, FIGS. 17-21

(89) To more effectively elucidate the present invention and its intricate details, a comparative example 1, an alternative implementation, is provided. This approach serves to highlight the unique aspects of the present invention, providing a clearer understanding of its distinctions and advantages over other possible implementations. Such comparisons facilitate a comprehensive explanation, ensuring that the novelty and distinctiveness of the invention are thoroughly articulated within the context of existing technologies.

(90) Referring to the FIGS. 17-2, an example of an alternative self-aligned channel process is described below. A first hard mask material, e.g. polysilicon, silicon dioxide or silicon nitride, is deposited on an epitaxial layer (3) and the mask material is patterned using photolithography in order to produce a first hard mask (M1). Instead depositing the first hard mask material directly on the epitaxial layer, the first hard mask material can be deposited on a thin layer (M0), e.g. silicon dioxide, on top of the topmost epitaxial layer, as presented in FIG. 18. There are two main functions of the layer M0: 1) adjust profiles of implanted ions, 2) protect the topmost epitaxial layer.

(91) The first hard mask is used as a mask for the implantation of the body regions (4). A second hard mask material, e.g. polysilicon, silicon dioxide or silicon nitride, is deposited on top of the first hard mask M1 and the thin layer M0, as presented in FIG. 19. The second hard mask material is deposited using a process with high conformity, i.e. the material thickness in trenches, on mesas and on sidewalls is approximately the same. The second mask material is etched using a dry etching process in order to create a second hard mask (M2) on the sidewalls of the first hard mask, as presented in FIG. 20. A process of creation of the second hard mask is called the spacer process. The first and second hard masks are used as a mask for the implantation of the source region (5). A self-aligned channel is formed between the JFET region (13) and the source region (5) at a shallow depth in the body region (4). During the process, the body contact region (6) is masked from co-implantation with a source region implantation profile. The body contact region (6) can be implanted prior to the self-aligned channel process or after it, as presented in FIG. 21.

Benefits of the Present Invention Over the Comparative Example 1

(92) Despite using the self-aligned channel, the cell pitch of the device described in the comparative example 1 is not only slightly reduced comparing to a device using two independent photolithography layers for the source and body regions (non-self aligned channel device).

(93) The cell of the comparative example 1 comprises of the body contact region (6) located between the source regions (5), as presented in FIG. 17. In this configuration during the device fabrication, the body contact region must be masked from co-implantation with the source profile. The masking is done by the hard masks M1 and M2, as presented in FIG. 20, which means that the width of the body contact region (6) being the minimal distance between the source regions (5) is a function of the minimal feature size for the hard mask M1 and the channel length (spacer width). This situation is displayed in FIG. 23, where L1 is the minimal feature size for the hard mask, M1, C is the channel length, and L1+2C is the distance between the source regions (5). While the minimum feature size for the hard mask M1 is a photolithography-dependent fixed value, the channel length is a variable. The fabrication process used by the comparative example 1 might be suitable for short channel lengths, however for longer channels the method is not useful, as it results wide spacings between the source regions and consequently in long cell pitches.

(94) Advantage of the self-aligned processes in the present invention is that the body contact region is buried below the source region and it does not increase the cell pitch for any applied channel length. The distance between the source regions (5) depends solely on the minimal feature size for the trench etching process and on the ohmic metal process. This distance, noted in FIG. 24 as L2, is much smaller than the distance between the source regions defined for the comparative example 1; L2<L1+2C.

(95) Comparative example 2, structure from GeneSiC, US11049962B2, US10916632B2

(96) A device disclosed in US11049962B2 and US10916632B2 shares some similarities with the present invention. It is planar-gate device (a channel is oriented parallel to the semiconductor surface) with a self-aligned channel, which incorporates a trench and a body contact region (p-type sinker #1) below the trench bottom. The function of the p-type sinker #1 is to improved the avalanche ruggedness. However, the fabrication method of this device and the resulting structures are different than for the present invention. The comparative example 2 comprises of three independently implanted p-type regions. The p-type inker #1 below the trench is implanted below the trench after the trench etching, which means that its width is the same as the width of the trench. The p-type sinker #1 is not aligned with the source region nor with the body region. In addition, for all embodiments, there is a source contact present on the top semiconductor surface.

(97) The advantage of the invention over the comparative example 2 is no presence of the source contact on the top semiconductor surface, which results in a smaller cell pitch. In addition, the invented fabrication method uses less fabrication due to three self-aligned processes, particularly due to the body contact region self-aligned on the source region. While the comparative example #2 focuses on the avalanche ruggedness, the main scope of the invention is to get a possible smallest pitch of the elementary cell.

(98) Device Structure

(99) On the second aspect of the present invention, a semiconductor device is disclosed, which includes a planar Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and an Insulated Gate Bipolar Transistor (IGBT).

(100) In the scope of the present invention, the semiconductor device is a cell. It may further comprise neighboring cells. The terms cell, elementary cell, device and structure are used interchangeably.

(101) The semiconductor device comprises a substrate (1), which serves as the foundational layer.

(102) A buffer layer (2) of a first conductivity doping type is formed on top of the substrate (1).

(103) One or more epitaxial layers (3) of the first conductivity doping type, r positioned atop the buffer layer (2).

(104) A body region (4) of a second conductivity doping type, is formed within the topmost layer and serves as a critical region for channel formation.

(105) A source region (5) of the first conductivity doping type, is placed within the body region (4).

(106) A body contact region (6) of the second conductivity doping type is buried below the source region (5) to reduce the semiconductor device pitch.

(107) A trench (16) is formed within the source region (5), making direct electrical access to the underlying body contact region (6) while maintaining a width that is narrower than that of the body contact region (6).

(108) An ohmic contact forming a source contact (9), overlaps the source region on the sidewalls of the trench.

(109) At ohmic contact forming a body contact (10), overlaps the body contact region (6) at the trench bottom.

(110) A Junction Field-Effect Transistor (JFET) region (13) is formed between the body regions (4) of the neighboring cells.

(111) A self-aligned channel (14) is formed between the source region (5) and the JFET region (13) at a shallow depth in the body region (4). The channel opens or closes the electrical current path between the source electrode and the drain electrode, controlling device operation. The source region (5) and the body contact region (6) exhibit identical widths.

(112) Furthermore, the semiconductor device comprises a gate insulator (7) and a gate (8). The gate insulator (7) and the gate (8) are placed above a portion of the body region (4) and a portion of the source region (5), and above the entire JFET region (13), effectively controlling the carrier concentration in the channel and thus the operation of the device.

(113) Additionally, the cell further comprises an interlayer dielectric (11), which separates the gate (8) from the source contact (9). This dielectric layer provides crucial electrical isolation between the gate and source contacts, preventing an excessive leakage current and ensuring device reliability.

(114) Moreover, a top metallization layer (12) is positioned above the interlayer dielectric (11). This metallization layer is electrically connected to both the source contact (9) and the body contact (10), collectively functioning as the source electrode (S). The top metallization provides a robust and low-resistance pathway for current flow, which is essential for the effective operation of the semiconductor device.

(115) Additionally, a bottom metallization layer (15) is provided, which serves as the drain electrode (D). This bottom metallization layer establishes the necessary connection to the semiconductor substrate. The gate (8) itself acts as the gate electrode (G), completing the three-terminal configuration of the MOSFET/IGBT device. The proper formation and placement of these metallization layers are critical for ensuring device efficiency and reliability.

(116) Further, in the semiconductor device of the present invention, the source region (5) and the body contact region (6) are formed using a self-aligned process in conjunction with the body region (4). The self-aligned nature of this process ensures that the source region (5) and the body contact region (6) are precisely aligned with the body region (4) and their widths are identical.

(117) Moreover, in the semiconductor device of the present invention, the trench (16) can be formed such that it indents into the body contact region (6). The source contact (9) is positioned on the trench (16) sidewalls on the source region (5), while the body contact (10) is located on the trench (16) sidewalls and bottom on the body contact region (6).

(118) In one embodiment of the semiconductor device, the substrate, buffer layer, and one or more epitaxial layers are composed of silicon carbide (SiC), a material known for its excellent thermal conductivity and high critical field. The first conductivity doping type ions are nitrogen (N) or phosphorus (P), which are selected for their ability to donate electrons and thereby create n-type regions within the silicon carbide. The second conductivity doping type ion is aluminum (Al), chosen for its ability to accept electrons and create p-type regions. The ohmic contacts, crucial for low-resistance electrical connections, are formed from materials such as nickel (Ni), titanium (Ti), aluminum (Al), or their compounds.

(119) In another embodiment of the semiconductor device, the substrate, buffer layer, and one or more epitaxial layers are also composed of silicon carbide (SiC). However, in this embodiment, the first conductivity doping type ion is aluminum (Al), used to create p-type regions, while the second conductivity doping type ions are nitrogen (N) or phosphorus (P), which create n-type regions. The ohmic contacts are similarly formed from materials such as nickel (Ni), titanium (Ti), aluminum (Al), or their compounds, ensuring low-resistance electrical paths.

(120) Further, in one instance, the body region (4) is characterized by a depth of at least 0.4 micrometers (um) and exhibits a peak doping concentration ranging between 5e17 cm.sup.3 and 1e19 cm.sup.3.

(121) Further, in another instance, the source region (5) is characterized by a depth of at least 0.1 micrometers (um) and has a peak doping concentration ranging between 1e19 cm.sup.3 and 1e21 cm.sup.3.

(122) Further, in yet another instance, the body contact region (6), which is buried below the source region (5), is characterized by a depth of at least 0.1 micrometers (um) from the junction between the body contact region and the source region, with a peak doping concentration ranging between 1e19 cm.sup.3 and 1e21 cm.sup.3. This precise doping profile is necessary to ensure effective ohmic contact formation:

(123) Referring to FIG. 14, in one embodiment, the depth of the body contact region (6) is bigger than the depth of the body region (4).

(124) Referring to FIG. 15, in one embodiment, wherein the trench indents into the body contact region (6), the source contact (9) is located on the source region (5) on the trench (16) sidewalls, the body contact (10) is located on the body contact region (6) on the trench (16) sidewalls and bottom.

(125) Lastly, in one embodiment, referring to FIG. 16, the trench (16) indents into the body contact region (6) and the depth of the body contact region (6) is bigger than the depth of the body region (4).

(126) The device structure of the present invention offers significant and multifaceted advantages. Firstly, due to the shift of the body contact region below the source region and elimination of the source contacts from the top semiconductor surface, the cell pitch is reduced, which allows for reduction of the resistance of an integrated circuit or for usage of smaller semiconductor area for device fabrication. Secondly utilization of three self-aligned processes reduces complexity and the number of fabrication steps, which decreases the total device cost. The self-aligned processes due to their reproducibility can enhance the yield and device reliability. For one embodiment presenting a structure with a body contact region deeper than the body region, the avalanche ruggedness will be improved and the number of process steps will be further reduced, if the same implantation profile used for the body contact region and for the edge termination of the device.

(127) Obviously, the above-mentioned embodiments are only examples for clearly illustrating the present invention, and are not intended to limit the implementations. A person with ordinary skill in the art may further make other changes or variations in a different form on the basis of the above description. Herein, examples are unnecessarily provided for all implementation manners. However, the obvious changes or modifications derived from this are still within the protection scope of the present invention.