Semiconductor device with a side surface having different partial regions

Abstract

A semiconductor device with a semiconductor body is specified, the semiconductor body extending in a vertical direction between a first main surface and a second main surface opposite the first main surface. The semiconductor body comprises a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type different from the first conductivity type thereby forming a first pn junction, wherein the first semiconductor layer is more heavily doped than the second semiconductor layer. A side surface of the semiconductor body extending between the first main surface and the second main surface delimits the semiconductor body in a lateral direction comprises a first partial region and a second partial region, wherein the first partial region and the second partial region delimit the first semiconductor layer in regions.

Claims

1. A semiconductor device with a semiconductor body, the semiconductor body extending in a vertical direction between a first main surface and a second main surface opposite the first main surface, wherein the semiconductor body comprises a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type different from the first conductivity type thereby forming a first pn junction; the first semiconductor layer is more heavily doped than the second semiconductor layer; a side surface of the semiconductor body extending between the first main surface and the second main surface delimits the semiconductor body in a lateral direction; the side surface of the semiconductor body comprises a first partial region and a second partial region; the first partial region and the second partial region delimit the first semiconductor layer in regions; the first partial region delimits the first pn junction in the lateral direction; the second partial region is spaced apart from the first pn junction in the vertical direction; and the first partial region is arranged at a first angle and the second partial region is arranged at a second angle with respect to the first pn junction wherein the first angle is larger than the second angle; the side surface comprises a third partial region, the first partial region being arranged between the second partial region and the third partial region, the third partial region directly adjoining the first partial region; the semiconductor body further comprises a second pn junction, the third partial region delimiting the second pn junction in the lateral direction; and the first partial region, the second partial region and the third partial region are flat in a cross-sectional view; the third partial region is arranged at a third angle with respect to the first pn junction, wherein the third angle is larger than the first angle; and the third angle is between 20 and 60 inclusive.

2. The semiconductor device according to claim 1, wherein the first angle is between 5 and 20 inclusive.

3. The semiconductor device according to claim 1, wherein the second angle is between 0.8 and 5 inclusive.

4. The semiconductor device according to claim 1, wherein a lateral extent of the first partial region is smaller than a lateral extent of the second partial region when seen along the vertical direction.

5. The semiconductor device according to claim 1, wherein the first angle is constant within the first partial region and the second angle is constant within the second partial region.

6. The semiconductor device according to claim 1, wherein the first partial region and the second partial region exhibit traces of a mechanical ablation method.

7. The semiconductor device according to claim 1, wherein the first partial region and the second partial region exhibit traces of a laser ablation method.

8. The semiconductor device according to claim 1, wherein the second pn junction is formed between the second semiconductor layer and a third semiconductor layer of the first conductivity type.

9. The semiconductor device according to claim 1, wherein the semiconductor device is a thyristor.

10. The semiconductor device according to claim 9, wherein the thyristor has a positive-negative bevel design, wherein the negative bevel comprises the first and second partial region.

Description

IN THE FIGURES

(1) FIG. 1 shows an exemplary embodiment of a semiconductor device in sectional view;

(2) FIG. 2 shows a further exemplary embodiment of a semiconductor device in sectional view;

(3) FIG. 3A shows simulation results of the electric field for a semiconductor device according to an embodiment of the semiconductor device described herein;

(4) FIG. 3B shows simulation results of the electric field for a reference semiconductor device;

(5) FIG. 4 shows measurements of the blocking voltage Vdc for different semiconductor devices.

(6) The elements illustrated in the figures and their size relationships among one another are not necessarily true to scale. Rather, individual elements or layer thicknesses may be represented with an exaggerated size for the sake of better representability and/or for the sake of better understanding.

(7) An exemplary embodiment of a semiconductor device 1 is illustrated in FIG. 1 in cross-sectional view. In this exemplary embodiment, the semiconductor device 1 is embodied as a semiconductor device having two blocking pn junctions for forward and reverse blocking. However, the invention may also be used for semiconductor devices having only one pn junction or more than two pn junctions.

(8) Metal electrodes of the semiconductor device 1 such as cathode, anode and gate electrode are not explicitly shown in the Figures.

(9) The semiconductor device 1 comprises a semiconductor body 2 that extends in a vertical direction between a first main surface 21 and a second main surface 22. The semiconductor body 2 comprises a plurality of differently doped partial regions. For the sake of simplicity only, a first semiconductor layer 31, a second semiconductor layer 32 and a third semiconductor layer 33 are shown. However, the semiconductor body may comprise more than three semiconductor layers or differently doped semiconductor regions.

(10) The semiconductor body 2 is arranged on a carrier 6. For instance the semiconductor body 2 is fixed to the carrier 6 by means of a connecting layer such as an adhesive or a solder (not explicitly shown in the figures).

(11) For example the carrier 6 comprises molybdenum or consists of molybdenum. However, other materials may be used for the carrier 6 as well.

(12) A first pn junction 41 is formed between the first semiconductor layer 31 and the second semiconductor layer 32. For instance, the second semiconductor layer 32 is n-doped and the first semiconductor layer 31 and the third semiconductor layer 33 are p-doped or vice versa. For instance the semiconductor body 2 is configured as a semiconductor disk. The semiconductor disk is a silicon wafer, for example. However, other semiconductor materials such as silicon carbide or gallium nitride may also be used.

(13) The first pn junction 41 and the second pn junction 42 extend in lateral direction between side surfaces 5 that laterally delimit the first pn junction 41 and the second pn junction 42. The side surface 5 comprises a first partial region 51, a second partial region 52 and a third partial region 53. These partial regions differ from one another with respect to the angle of the side surface 5 in the respective region with respect to the first pn junction 41.

(14) The first pn junction 41 is laterally delimited by the first partial region 51. Thus, the first partial region 51 laterally delimits in regions the first semiconductor layer 31 and the second semiconductor layer 32. The second partial region 52 extends between the first partial region and the first main surface 21. The second partial region 52 is spaced apart from the first pn junction 41 in vertical direction.

(15) The first angle (cf. FIG. 2) is between 5 and 20 inclusive, for instance, for example 10 or 14. The second angle is between 0.8 and 5 inclusive, for instance, for example 1.

(16) The first semiconductor layer 31 is more heavily doped than the second semiconductor layer 32 so that the cross-section of the semiconductor device decreases towards the more heavily doped layer. Consequently, the first partial region 51 together with the second partial region 52 forms a negative bevel design for the first pn junction 41.

(17) The third semiconductor layer 33 is more heavily doped than the second semiconductor layer 32 so that the third partial region 53 forms a positive bevel design for the second pn junction 42. The third angle between the third partial region 53 and the first pn junction 41 is between 20 and 60 inclusive, for example.

(18) Within the first partial region 51, the second partial region 52 and the third partial region 53, the angle of the side surface 5 with respect to the first pn junction 41 is constant. Partial regions of the side surface 5 being flat in a cross-sectional view may be formed efficiently using a mechanical ablation method. Such a method may result in traces 55 characteristic of the respective ablation method, such as a grinding method. The traces are schematically shown in an enlarged section of the side surface 5 in FIG. 1.

(19) The grinding may be performed such that also material of the carrier 6 is removed so that at least part of a side surface 60 of the carrier 6 has the same angle with respect to the first pn junction 41 as the third partial region 53. Other ablation methods may also be used, for example a laser ablation method, resulting in characteristic traces 55.

(20) FIG. 2 illustrates an exemplary embodiment of a semiconductor device 1 wherein the structure of the semiconductor body is shown in more detail. The description of FIG. 1 applies to FIG. 2 as well unless otherwise indicated.

(21) When seen from the first main surface 21 towards the second main surface 22, the semiconductor body 2 comprises a fourth semiconductor layer 34 acting as an n.sup.+ layer, the first semiconductor layer 31 as p-layer, the second semiconductor layer 32 as n.sup. layer, the third semiconductor layer 33 as p-layer and a fifth semiconductor layer 35 as a p.sup.+ layer.

(22) Between the fourth semiconductor layer 34 and the first semiconductor layer a further pn junction is formed. This further pn junction, however, does not extend to the side surface 5 in lateral direction.

(23) The above layer structure may be used for a PCT thyristor, for instance. However, the layer structure may be modified within wide limits depending on the application of the semiconductor device 1.

(24) The first main surface 21 represents a cathode side and the second main surface 22 an anode side of the semiconductor body 2, for instance.

(25) The first partial region 51 is used to extend the shallow bevel region formed by the second partial region 52 through the deeply diffused cathode side first pn junction 41.

(26) The side surface 5 of the semiconductor body 2 is surrounded by an insulator 7, such as rubber, in order to protect the otherwise exposed first and second pn junctions 41, 42 at the side surface 5.

(27) When seen along the vertical direction, a lateral extent w1 of the first partial region 51 is smaller than a lateral extent w2 of the second partial region.

(28) For example the lateral extent w1 amounts to 1 mm and the lateral extent w2 of the second partial region 52 amounts to 2.1 mm for a semiconductor body with a thickness (i.e. extent in vertical direction) of 1.42 mm for a thyristor configured for a rated reverse blocking voltage of 8.5 kV.

(29) FIG. 3A illustrates results of electrical simulations of the electrical field for a semiconductor device as described in connection with FIG. 2 at a voltage of 7 kV applied in reverse direction. The simulation is based on a device with a first angle of 10.

(30) For comparison FIG. 3B shows simulation results for a reference structure without a first partial region between the second partial region 52 and the third partial region 53.

(31) FIG. 3B illustrates that a punch through of the electrical field occurs at a voltage of 7 kV caused by the upturning of the electrical field near the transition to the positive bevel, i.e. between the two different partial regions of the side surface 5.

(32) The simulation results shown in FIG. 3A, in contrast, confirm that high blocking capabilities can be obtained using the described configuration of the side surface 5 of the semiconductor body 2 as a punch through can be avoided.

(33) This has also been confirmed experimentally as shown by means of the experimental results illustrated in FIG. 4. For the measurements, samples are used having different values w1 for the lateral extent of the first partial 51 wherein a value of 0 mm corresponds to a conventional device with only two different bevels. In each case, the first angle amounts to 14.

(34) At 25 C. the DC blocking voltage is significantly increased for the samples having a bevel length of 1 mm or 1.6 mm and an angle of 14 compared to the reference sample with w1=0 mm.

(35) Consequently, the proposed design of the surface 5 of the semiconductor body allows to obtain a semiconductor device 1 such as a thyristor with high blocking voltage characteristics via a modified side surface of the semiconductor body. Thus, it is not necessary to increase the width of the n-base (the second semiconductor layer) of the thyristor until the punch through voltage is moved above the device maximum rated voltage. This solution would have the drawback that an increased thickness of the n-base would reduce the performance of the thyristor.

(36) This patent application claims the priority of European patent application EP 20210372.7, the disclosure content of which is hereby incorporated by reference.

(37) The invention described herein is not restricted by the description given with reference to the exemplary embodiments. Rather, the invention encompasses any novel feature and any combination of features, including in particular any combination of features in the claims, even if this feature or this combination is not itself explicitly indicated in the claims or exemplary embodiments.

LIST OF REFERENCE SIGNS

(38) 1 semiconductor device 2 semiconductor body 21 first main surface 22 second main surface 31 first semiconductor layer 32 second semiconductor layer 33 third semiconductor layer 34 forth semiconductor layer 35 fifth semiconductor layer 41 first pn junction 42 second pn junction 5 side surface 51 first partial region 52 second partial region 53 third partial region 55 traces 6 carrier 60 side surface of carrier 7 insulator first angle second angle third angle w1 lateral extent of first partial region w2 lateral extent of second partial region