SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Abstract

A semiconductor device includes a substrate, a drift region, a well region, a first shield region, a junction gate field-effect transistor (JFET) region, a source region and a gate structure. The first shield region is located in the drift region, in which a bottom surface of the first shield region is lower than a bottom surface of the well region and a carrier concentration of the first shield region is greater than a carrier concentration of the well region. The JFET region is located in the drift region, in which a bottom surface of the JFET region is lower than a bottom surface of the first shield region. A first portion of the first shield region is located between the well region and the JFET region. The source region is adjacent to the well region. The gate structure is located on the drift region.

Claims

1. A semiconductor device, comprising: a substrate; a drift region located in the substrate; a well region located in the drift region; a first shield region located in the drift region, wherein a bottom surface of the first shield region is lower than a bottom surface of the well region and a carrier concentration of the first shield region is greater than a carrier concentration of the well region; a junction gate field-effect transistor (JFET) region located in the drift region, wherein a bottom surface of the JFET region is lower than a bottom surface of the first shield region, a first portion of the first shield region is located between the well region and the JFET region; a source region adjacent to the well region; and a gate structure located on the drift region.

2. The semiconductor device of claim 1, wherein the carrier concentration of the first shield region is in a range of 110.sup.17 cm.sup.3 to 110.sup.19 cm.sup.3.

3. The semiconductor device of claim 1, wherein the carrier concentration of the well region is in a range of 510.sup.16 cm.sup.3 to 110.sup.18 cm.sup.3.

4. The semiconductor device of claim 1, wherein a second portion of the first shield region extends to the bottom surface of the well region.

5. The semiconductor device of claim 1, wherein a sidewall of the first shield region is align to a sidewall of the well region.

6. The semiconductor device of claim 1, further comprising: a second shield region located in the drift region.

7. The semiconductor device of claim 1, further comprising: a drain pad located on a side of the substrate opposite to the gate structure.

8. The semiconductor device of claim 1, further comprising: a source pad located on the drift region and the gate structure.

9. A semiconductor device, comprising: a substrate; a gate structure located on the substrate; a plurality of well region located in the substrate and at two sides of the gate structure; a plurality of first shield region located in the substrate and at two sides of the gate structure, wherein a bottom surface of the first shield region is lower than a bottom surface of the well region and a carrier concentration of the first shield region is greater than a carrier concentration of the well region; a plurality of second shield region located in the substrate and at two sides of the gate structure, wherein a bottom surface of the second shield region is lower than a bottom surface of the first shield region and a carrier concentration of the second shield region is greater than a carrier concentration of the first shield region; a junction gate field-effect transistor (JFET) region located in the substrate, wherein a bottom surface of the JFET region is lower than a bottom surface of the second shield region; and a source region adjacent to the well region.

10. The semiconductor device of claim 9, wherein the carrier concentration of the first shield regions is in a range of 110.sup.17 cm.sup.3 to 110.sup.19 cm.sup.3.

11. The semiconductor device of claim 9, wherein the carrier concentration of the second shield regions is in a range of 210.sup.17 cm.sup.3 to 210.sup.19 cm.sup.3.

12. The semiconductor device of claim 9, wherein the carrier concentration of the second shield regions is about twice as the carrier concentration of the first shield regions.

13. The semiconductor device of claim 9, wherein a sidewall of one of the second shield regions is align to a sidewall of one of the first shield regions.

14. The semiconductor device of claim 9, wherein a top surface of one of the second shield regions is lower than a top surface of the substrate.

15. The semiconductor device of claim 14, wherein the top surface of the second shield region is lower than a top surface of one of the first shield regions.

16. A manufacturing method of a semiconductor device, comprising: forming a drift region in a substrate; forming a first shield region in the drift region; forming a second shield region in the drift region, wherein a carrier concentration of the first shield region is greater than a carrier concentration of the second shield region; forming a well region in the drift region, wherein the carrier concentration of the second shield region is greater than a carrier concentration of the well region; forming a source region in the well region; forming a junction gate field-effect transistor (JFET) region in the drift region; and forming a gate structure on the drift region.

17. The manufacturing method of the semiconductor device of claim 16, wherein the carrier concentration of the second shield region is in a range of 110.sup.17 cm.sup.3 to 110.sup.19 cm.sup.3.

18. The manufacturing method of the semiconductor device of claim 16, wherein the carrier concentration of the first shield region is in a range of 210.sup.17 cm.sup.3 to 210.sup.19 cm.sup.3.

19. The manufacturing method of the semiconductor device of claim 16, wherein the carrier concentration of the well region is in a range of 510.sup.16 cm.sup.3 to 110.sup.18 cm.sup.3.

20. The manufacturing method of the semiconductor device of claim 16, wherein forming a second shield region in the drift region such that a sidewall of a portion of the second shield region is align to a sidewall of the first shield region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0012] FIG. 1 to FIG. 4 are cross-sectional views of a semiconductor device during intermediate stages of manufacturing according to one embodiment of the present disclosure.

[0013] FIG. 5 is a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure.

[0014] FIG. 6 is a cross-sectional view of a semiconductor device according to yet another embodiment of the present disclosure.

[0015] FIG. 7 is a cross-sectional view of a semiconductor device according to yet another embodiment of the present disclosure.

DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

[0017] Further, spatially relative terms, such as beneath, below, lower, above, upper and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0018] FIG. 1 to FIG. 4 are cross-sectional views of a semiconductor device 100 during intermediate stages of manufacturing according to one embodiment of the present disclosure. Refer to FIG. 1 and FIG. 2, the manufacturing process of the semiconductor device is, firstly, forming a drift region 112 in a substrate 110. Thereafter, forming a first shield region 120 in the drift region 112. The first shield region 120 can use diffusion, ion implantation or any suitable method to form.

[0019] Thereafter, forming a second shield region 130 in the drift region 112, in which a carrier concentration of the first shield region 120 is greater than a carrier concentration of the second shield region 130. In some embodiments, the carrier concentration of the first shield region 120 is about twice as the carrier concentration of the second shield regions 130. For example, the carrier concentration of the second shield region is in a range of 110.sup.17 cm.sup.3 to 110.sup.19 cm.sup.3, and the carrier concentration of the first shield region is in a range of 210.sup.17 cm.sup.3 to 210.sup.19 cm.sup.3. The formation of the second shield region 130 can use diffusion, ion implantation or any suitable method. Moreover, a portion 124 of the first shield region 120 extends under the bottom surface 131 of the second shield region 130.

[0020] Refer to FIG. 2, thereafter, forming a well region 140 in the drift region 112, in which the carrier concentration of the second shield region 130 is greater than a carrier concentration of the well region 140. For example, the carrier concentration of the well region 140 is in a range of 510.sup.16 cm.sup.3 to 110.sup.18 cm.sup.3. In other words, in some embodiments, the doping concentration of the first shield region 120 is greater than the doping concentration of the second shield region 130, and the doping concentration of the second shield region 130 is greater than the doping concentration of the well region 140. In some embodiments, the first shield region 120, the second shield region 130 and the well region can have a same first conductivity type, such as P type area, and can include P type dopant. The formation of the well region 140 can use diffusion, ion implantation or any suitable method. Moreover, a first portion 132 of the second shield region 130 is located between the well region 140 and the first shield region 120.

[0021] Refer to FIG. 3, thereafter, forming a source region 150 in the well region 140. The formation of the source region 150 can use diffusion, ion implantation or any suitable method. Thereafter, forming a junction gate field-effect transistor (JFET) region 160 in the drift region 112. In some embodiments, the bottom surface 161 of the JFET region 160 is lower than the bottom surface 121 of the first shield region 120, and a first portion 122 of the first shield region is located between the well region 140 and the JFET region 160. In some embodiment, the drift region 112 and the JFET region 160 can have a same second conductivity type, such as N type area, and can includes N type dopant.

[0022] Refer to FIG. 4, thereafter, forming a gate structure 170 on the drift region 112. The gate structure 170 includes a gate conducting layer 172 and a gate dielectric layer 174. In some embodiments, the gate dielectric layer 174 will evenly cover on the drift region 112 by depositing or other suitable method. Thereafter, depositing the gate conducting layer 172. Thereafter, patterning the gate dielectric layer 174 and the gate conducting layer 172 to form the gate structure 170. In some embodiments, the gate conducting layer 172 includes a conducting material, such as metal or poly silicon, but not limited to these. The gate dielectric layer 174 includes dielectric materials, such as silicon dioxide (SiO.sub.2), aluminum oxide (Al.sub.2O.sub.3) or high-k dielectric material, but not limited to these.

[0023] Thereafter, forming a dielectric layer 173 to cover the gate structure 170. In some embodiments, the dielectric layer 173 can include suitable dielectric materials, such as silicon oxide, silicon nitride, or the like.

[0024] Thereafter, forming a source pad 190 on the gate structure 170 and the drift region 112. In some embodiments, the source pad 190 includes a conducting material, such as metal or poly silicon, but not limited to these. Thereafter, forming a drain pad 180 on a side of the substrate 110 opposite to the drift region 112. After that, the semiconductor device 100 is complete. In some embodiments, the drain pad 180 includes a conducting material, such as metal or poly silicon, but not limited to these.

[0025] Since there are shield regions (such as, first shield region 120, second shield region 130) between the JFET region 160 and well region 140, the problem of drain-source leakage current can be significantly solved, which decrease the effect of the drain-source leakage current on the power consumption of the device.

[0026] In the following description, different types of semiconductor device are described.

[0027] FIG. 5 is a cross-sectional view of a semiconductor device 100a according to another embodiment of the present disclosure. Refer to FIG. 5, a semiconductor device 100a includes a substrate 110, a gate structure 170, a plurality of well region 140, a plurality of first shield region 120a, a plurality of second shield region 130, a JFET region 160 and a source region 150. The gate structure 170 is located on the substrate 110. The well region 140 is located in the substrate 110 and at two sides of the gate structure 170. The second shield region 130 is located in the substrate 110 and at two sides of the gate structure 170, in which a bottom surface 131 of the second shield region 130 is lower than a bottom surface 141 of the well region 140 and a carrier concentration of the second shield region 130 is greater than a carrier concentration of the well region 140. The first shield region 120a is located in the substrate 110 and at two sides of the gate structure 170, in which a bottom surface 121a of the first shield region 120a is lower than a bottom surface 131 of the second shield region 130 and a carrier concentration of the first shield region 120a is greater than a carrier concentration of the second shield region 130. The JFET region 160 is located in the substrate 110, in which a bottom surface 161 of the JFET region 160 is lower than a bottom surface 121a of the first shield region 120a. The source region 150 is adjacent to the well region 140. The gate structure 170 includes a gate conducting layer 172, a dielectric layer 173 and a gate dielectric layer 174. Moreover, the semiconductor device 100a also includes a drain pad 180 and a source pad 190. The drain pad is located on a surface of the substrate 110 opposite to the drift region 112. The source pad 190 is located on the drift region 112 and the gate structure 170. Moreover, in the present embodiment, the top surface 123a of the first shield region 120a is lower than the top surface 113 of the substrate 110.

[0028] FIG. 6 is a cross-sectional view of a semiconductor device 100b according to yet another embodiment of the present disclosure. Refer to FIG. 6, a semiconductor device 100b includes a substrate 110, a gate structure 170, a plurality of well region 140, a plurality of first shield region 120b, a plurality of second shield region 130, a JFET region 160 and a source region 150. The gate structure 170 is located on the substrate 110. The well region 140 is located in the substrate 110 and at two sides of the gate structure 170. The second shield region 130 is located in the substrate 110 and at two sides of the gate structure 170, in which a bottom surface 131 of the second shield region 130 is lower than a bottom surface 141 of the well region 140 and a carrier concentration of the second shield region 130 is greater than a carrier concentration of the well region 140. The first shield region 120b is located in the substrate 110 and at two sides of the gate structure 170, in which a bottom surface 121b of the first shield region 120b is lower than a bottom surface 131 of the second shield region 130 and a carrier concentration of the first shield region 120b is greater than a carrier concentration of the second shield region 130. The JFET region 160 is located in the substrate 110, in which a bottom surface 161 of the JFET region 160 is lower than a bottom surface 121b of the first shield region 120b. The source region 150 is adjacent to the well region 140. The gate structure 170 includes a gate conducting layer 172, a dielectric layer 173 and a gate dielectric layer 174. Moreover, the semiconductor device 100b also includes a drain pad 180 and a source pad 190. The drain pad is located on a surface of the substrate 110 opposite to the drift region 112. The source pad 190 is located on the drift region 112 and the gate structure 170. Moreover, in the present embodiment, a sidewall 125b of the first shield region 120b is align to a sidewall 133 of the second shield region 130.

[0029] FIG. 7 is a cross-sectional view of a semiconductor device 100c according to yet another embodiment of the present disclosure. Refer to FIG. 7, a semiconductor device 100c includes a substrate 110, a drift region 112, a well region 140, a first shield region 120, a JFET region 160, a source region 150 and a gate structure 170. The drift region 112 is located in the substrate 110. The well region 140 is located in the drift region 112. The first shield region 120 is located in the drift region 112, in which a bottom surface 121 of the first shield region 120 is lower than a bottom surface 141 of the well region 140 and a carrier concentration of the first shield region 120 is greater than a carrier concentration of the well region 140. The JFET region 160 is located in the drift region 112, in which a bottom surface 161 of the JFET region 160 is lower than a bottom surface 121 of the first shield region 120. A first portion 122 of the first shield region 120 is located between the well region 140 and the JFET region 160. A second portion 124 of the first shield region 120 extends to the bottom surface 141 of the well region 140. The source region 150 is adjacent to the well region 140. The gate structure 170 is located on the drift region 112. The gate structure 170 includes a gate conducting layer 172, a dielectric layer 173 and a gate dielectric layer 174. Moreover, the semiconductor device 100b also includes a drain pad 180 and a source pad 190. The drain pad is located on a surface of the substrate 110 opposite to the drift region 112. The source pad 190 is located on the drift region 112 and the gate structure 170.

[0030] The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.