SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD

Abstract

In one embodiment, the semiconductor device (1) comprises a semiconductor body (2), a gate electrode (33) and a first electrode (31), whereinthe semiconductor body (2) comprises a first region (21) which is a source region or an emitter region, and comprises a well region (22), the first region (21) is of a first conductivity type and the well region (22) is of a different, second conductivity type,the well region (22) is separated from the gate electrode (33) by a gate insulator layer (4),the first region (21) is electrically contacted by means of the first electrode (31) which is a source electrode or an emitter electrode,in the first region (21) there is at least one current limiting region (5), andthe at least one current limiting region (5) is of at least one electrically insulating material.

Claims

1. A semiconductor device comprising a semiconductor body, a gate electrode and a first electrode, wherein the semiconductor body comprises a first region which is a source region or an emitter region, and comprises a well region located next to the first region, the first region is of a first conductivity type and the well region is of a different, second conductivity type, the well region is adjacent to the gate electrode and is separated from the gate electrode by a gate insulator layer, and the first region is electrically contacted by means of the first electrode which is a source electrode or an emitter electrode, characterized in that in the first region there is a plurality of current limiting regions, the current limiting regions are each of at least one electrically insulating material, and the current limiting regions are distant from one another, seen in top view of the semiconductor body.

2. The semiconductor device according to claim 1, wherein, seen in top view of the semiconductor body, the gate electrode as well as the first electrode overlap with the first region, and the current limiting regions are distant from the gate electrode as well as from the first electrode.

3. The semiconductor device according to claim 1, wherein, seen in top view of the semiconductor body, the first region completely extends between the current limiting regions and the first electrode as well as between the current limiting regions and the gate electrode, the current limiting regions are located between the first electrode and the gate electrode.

4. The semiconductor device according to claim 1, wherein, seen in cross-section of the semiconductor body through the first region and through the gate electrode, the first region extends all around the current limiting regions in directions towards the well region so that the first region is embedded in the well region and so that the current limiting regions are embedded in the first region.

5. The semiconductor device according to claim 1, wherein a volume of the current limiting regions is at least 10% and at most 95% of an overall volume of the at current limiting regions together with the first region.

6. The semiconductor device according to claim 1, wherein the current limiting regions are of a metal oxide or of a semiconductor oxide, wherein the current limiting regions are recesses in the first region and the at least one electrically insulating material fills said recesses, and wherein the least one electrically insulating material terminates aligned with the first region.

7. The semiconductor device according to claim 1, wherein the semiconductor body further comprises a drift region which is of the first conductivity type and also comprises a second region which is a drain region or a collector region, wherein the drift region is located between the well region and the second region, wherein the semiconductor device further comprises a second electrode which is a collector electrode or a drain electrode, the second electrode is located on a side of the second region remote from the drift region, and wherein the semiconductor body is of SiC.

8. The semiconductor device according to claim 1, wherein, seen in top view of the semiconductor body, the gate electrode and the first electrode each extend along a straight line, the first region extends in parallel with the gate electrode and the first electrode, or wherein, seen in top view of the semiconductor body, the gate electrode and the first electrode each comprise a plurality of sub-sections arranged along at least one arrangement line, the first region extends between adjacent sub-sections of the gate electrode and the first electrode.

9. The semiconductor device according to claim 1, which is of planar design so that the gate insulation layer and the gate electrode are applied on a planar section of a top side of the semiconductor body, the first region is located at the top side.

10. The semiconductor device according to claim 1, which is of trench design so that the gate insulation layer and the gate electrode are at least partly arranged in a trench in the semiconductor body, a depth of the trench exceeds a depth of the well region, starting from a top side of the semiconductor body, the first region is located at the top side.

11. The semiconductor device according to claim 1, wherein the current limiting regions are arranged along one stripe or along a plurality of stripes.

12. The semiconductor device according to claim 1, wherein, seen in top view of the semiconductor body, the current limiting regions are shaped as at least one of: triangle, square, rectangle, hexagon, circle.

13. A manufacturing method for a semiconductor device according to claim 1, the method comprises: providing the semiconductor body, forming the first region and the well region in the semiconductor body, etching recesses into the first region and filling the recesses with the at least one electrically insulating material so that the current limiting regions are created, applying the gate insulator layer to the semiconductor body, and applying the gate electrode and the first electrode to the semiconductor body.

14. The method according to claim 13, wherein the recesses are etched into the semiconductor body, and then at least some of a doping of the first region is applied into the semiconductor body through the recesses, and then the at least one electrically insulating material is filled into the recesses.

15. The method according to claim 13, further comprising forming at least one plug region into the semiconductor body, the at least one plug region is of the second conductivity type and has a maximum doping concentration higher than a maximum doping concentration of the well region, the at least one plug region is for electrically contacting the well region, wherein the first region reaches deeper into the semiconductor body than the at least one plug region.

16. The method according to claim 13, wherein creating the first region includes two different doping steps so that, seen in cross-section, a doping profile of the first region is of a stepped manner.

17. (canceled)

18. (canceled)

Description

[0066] A semiconductor device and a method described herein are explained in greater detail below by way of exemplary embodiments with reference to the drawings. Elements which are the same in the individual figures are indicated with the same reference numerals. The relationships between the elements are not shown to scale, however, but rather individual elements may be shown exaggeratedly large to assist in understanding.

[0067] In the figures:

[0068] FIG. 1 is a schematic sectional perspective view of an exemplary embodiment of a semiconductor device described herein,

[0069] FIGS. 2 to 4 are schematic sectional views of exemplary embodiments of semiconductor devices described herein,

[0070] FIGS. 5 and 6 are schematic sectional perspective views of exemplary embodiments of semiconductor devices described herein,

[0071] FIG. 7 is a schematic sectional view of an exemplary embodiment of a semiconductor device described herein,

[0072] FIGS. 8 to 11 are schematic diagrams of electric characteristics of simulations of semiconductor devices described herein, compared with corresponding semiconductor devices free of the at least one current limiting region,

[0073] FIG. 12 is a schematic block diagram of an exemplary embodiment of a method for manufacturing semiconductor devices described herein, and

[0074] FIGS. 13 and 14 are schematic top views of exemplary embodiments of semiconductor devices described herein.

[0075] FIG. 1 illustrate an exemplary embodiment of a semiconductor device 1. The semiconductor device 1 comprises a semiconductor body 2 which is, for example, of SiC. In the semiconductor body 2, there is a first region 21, a well region 22 and a drift region 23. There is a plug region 25 for electrically contacting the well region 22.

[0076] Further, the semiconductor device 1 comprises a gate electrode 33 which is separated from the semiconductor body 2 by means of a gate insulator layer 4. Further, there is a first electrode 31 which electrically contacts the first region 21 and the plug region 25. The gate insulator layer 4 and the first electrode 31 are located at a top side 20 of the semiconductor body 2. The top side 20 is of planar fashion. The gate electrode 33 and the first electrode 31 may each extend along a straight line along a direction perpendicular to the cross-section illustrated in FIG. 1.

[0077] For example, the first region 21 and the drift region 23 are n-doped and the well region 22 and the plug region 25 are p-doped. If the semiconductor device 1 is an insulated-gate bipolar transistor, IGBT or a reverse-conducting insulated-gate bipolar transistor, RC-IGBT, then the first region 21 is an emitter region and the first electrode 31 is an emitter electrode. If the semiconductor device 1 is a junction gate field-effect transistor, JFET, a metal-insulator-semiconductor field-effect transistor, MISFET, or a metal-oxide-semiconductor field-effect transistor, MOSFET, then the first region 21 is a source region and the first electrode 31 is a source electrode.

[0078] In the first region 21, there is a current limiting region 5. The current limiting region 5 is of an electrically insulating material, for example, SiO.sub.2. The current limiting region 5 runs along a straight line in parallel with the gate electrode 33 and the first electrode 31. The current limiting region 5 is located directly at the top side 20, like the first region 21.

[0079] A depth of the first region 21 into the semiconductor body 2 exceeds a depth of the current limiting region 5 into the semiconductor body 2, starting from the top side 20. Towards the well region 22 in which the first region 21 is embedded, all around the current limiting region 5 there is the first region 21, seen in cross-section.

[0080] Optionally, the at least one current limiting region 5 is arranged mirror symmetrically in the first region 21, seen in top view as well as seen in cross-section. For example, seen in top view of the top side 20, the current limiting region 5 is arranged symmetrically in the first region 21 and between the electrodes 31, 33. Hence, there can be a line M of mirror symmetry concerning the current limiting region 5 and the first region 21

[0081] Thus, FIG. 1 depicts the basic concept of the proposed semiconductor device 1, where a recess is etched inside the first region 21. The etched and filled recess can have different shapes and depths and can be uniform or also non-uniform along the direction perpendicular to the cross-section of FIG. 1, see also FIGS. 2 to 7 below.

[0082] With the proposed at least one current limiting region 5, the total source area or emitter area is reduced, and the carriers' channel-to-contact path is increased. Both effects lead to an increased value of the source resistance R.sub.S or correspondingly of an emitter resistance. Increasing the value of R.sub.S will turn into a reduction of the saturation current I.sub.SAT, during a short circuit condition. A depth d of the current limiting region 5 and its length L in parallel with the top side 20 and along the cross-section of FIG. 1 could be properly designed to achieve the desired effect on the short circuit current, while keeping negligible its impact during conduction in nominal conditions, for example, on the total R.sub.DS,on.

[0083] The semiconductor device 1 of FIG. 1 is of a planar design. Contrary to that, the semiconductor device 1 of FIG. 2 is of a trench design. Thus, the gate electrode 33 and the gate insulator layer 4 are at least partially located in a trench into the semiconductor body 2. Accordingly, the top side 20 is not of planar fashion as it is penetrated by said trench, contrary to what is the case in FIG. 1. The gate electrode 33 reaches deeper into the semiconductor body 2 than the well region 22, for example, starting from the top side 20.

[0084] Further, in FIG. 2 it is shown that there are multiple first regions 21 and, thus, current limiting regions 5, arranged symmetrically with respect to the gate electrode 33. There can be a plurality of the units illustrated in FIG. 2 next to one another so that there can be a plurality of stipes of the gate electrode 33 as well as of the first electrode 31 running perpendicular to the plane of projection of FIG. 2.

[0085] This symmetric arrangement of FIG. 2, see also FIG. 13, and/or the trench design of FIG. 2 can of course be applied analogously to all other embodiments, too.

[0086] The current limiting regions 5, one per first region 21, of FIG. 2 are of the same design as in FIG. 1, that is, of a trough with cuboid shape. According to FIG. 2, the trough has sharp edges and corners; according to FIG. 1, the trough has rounded edges and corners. Both designs are possible in all embodiments, depending on the manufacturing process of the at least one current limiting region 5.

[0087] Moreover, in FIG. 2 it is shown that there is a second electrode 32, and the semiconductor body 2 comprises a second region 24. For example, the second region 24 is a substrate on which the other regions 23, 22, 21, 25 are formed by means of growth and/or doping, like ion implantation. In case of an IGBT or RC-IGBT, the second electrode 32 is a collector electrode, and the second region is a collector region which is of the same doping type as the well region. In case of a MOSFET or MISFET, the second electrode 32 is a drain electrode, and the second region is a drain region which is of the same doping type as the first region. The same applies for all other embodiments of the semiconductor device 1. For example, in FIG. 1 there can be the second region 24 and the second electrode 32 directly on a side of the drift region 23 facing away from the top side 20, analogously to FIG. 2.

[0088] Further, according to FIG. 2 the plug region 25 reaches deeper into the semiconductor body 2, starting from the top side 20, than the first region 21. Otherwise, see FIG. 1, the plug region 25 can have the same depth as the first region 21 or can also be shallower or deeper than the first region 21. Both possibilities can apply in all the embodiments.

[0089] As in FIG. 1, also in FIG. 2 the at least one current limiting region 5 per first region 21 is distant from the first electrode 31, from the gate electrode 33 and from the gate insulator layer 4.

[0090] For example, maximum doping concentrations of the first region 21, the second region 24 and the at least one plug region 25 are at least 110.sup.18 cm.sup.3 or are at least 510.sup.18 cm.sup.3 or at least 110.sup.19 cm.sup.3 and/or at most 510.sup.20 cm.sup.3 or at most 210.sup.20 cm.sup.3 or at most 110.sup.20 cm.sup.3. Further, a maximum doping concentration of the well region 22 and, thus, of a channel region next to the gate insulator layer 4 may be at least 510.sup.16 cm.sup.3 or at least 110.sup.17 cm.sup.3 and/or at most 510.sup.19 cm.sup.3 or at most 510.sup.18 cm.sup.3. Depending on the voltage class of the semiconductor device 1, a maximum doping concentration of the drift region 23 may be at least 110.sup.11 cm.sup.3 or at least 110.sup.12 cm.sup.3 or at least 110.sup.13 cm.sup.3 and/or at most 110.sup.17 cm.sup.3 or at most 510.sup.16 cm.sup.3 or at most 110.sup.16 cm.sup.3. For example, a thickness of the gate insulator layer 4 is between 10 nm and 250 nm or between 80 nm and 150 nm. These parameters may individually or collectively apply for all other embodiments, too.

[0091] Otherwise, the same as to FIG. 1 may also apply to FIG. 2, and vice versa.

[0092] In FIGS. 3 and 4, like in FIG. 1, there is one current limiting region 5 per first region 21. The current limiting region 5 can be arranged mirror symmetrically in the first region 25, the axis of mirror symmetry runs perpendicular to the top side 20.

[0093] Contrary to what is shown in FIG. 1, according to FIGS. 3 and 4 the current limiting region 5 extends beyond the gate insulator layer 4 as well as the gate electrode 33. Such an arrangement is possible in all other embodiments, too. Otherwise, contrary to what is shown in FIGS. 3 and 4, the current limiting region 5 may be located non-mirror symmetrically in the first region 21 so that the current limiting region 5 ends distant from the gate insulator layer 4 and, thus, may not run beyond the gate electrode 33. This is possible as well in all other embodiments.

[0094] According to FIG. 3, the current limiting region 5 is formed as a shallow trough in the first region 21 which is also formed as one trough. The depth d of the current limiting region 5 amounts, for example, between 10% and 90% or between 40% and 80% of a depth D of the first region 21. The first region 21 and the plug region 25 may be of the same depth, for example, within manufacturing tolerances. For example, the depth D of the first region 21 is at least 0.1 m and/or is at most 2 m.

[0095] According to FIG. 4, the current limiting region 5 is formed as a deep trough in the first region 21 which is formed as two troughs, one above the other, wherein the trough next to the top side 20 has a larger extent in parallel with the plane of projection of FIG. 4. In this case, too, the maximum depth d of the current limiting region 5 can amount between 10% and 90% or between 40% and 80% of the overall depth D of the overall first region 21 which is composed of the two troughs. Because of the design with two stacked troughs, the first region 21 can run deeper into the semiconductor body 2 than the plug region 25. It is possible that the plug region 25 is of the same depth as the trough of the first region 21 next to the top side 20, for example, within manufacturing tolerances. For example, the depth D of the first region 21 is at least 0.2 m and/or is at most 4 m.

[0096] For example, first the trough next to the top side 20 is formed by corresponding doping, and then the recess for the current limiting region 5 is formed, and then the doping for the trough remote from the top side 20 is provided through the recess before the electrically insulating material is applied. Hence, the trough of FIG. 4 has a step-like design, seen in cross-section. Otherwise, a deep trough with the rectangular shape with rounded corners, for example, as depicted in FIG. 3, is likewise possible in the configuration of FIG. 4.

[0097] Both designs with a shallow or a deep first region 21 as shown in FIGS. 3 and 4 are possible in all other embodiments, too.

[0098] For example, the length L of the current limiting region 5 is between 10% and 90% or between 40% and 80% or between 50% and 70% of a width B of the first region 21. This is possible as well in all other embodiments.

[0099] Otherwise, the same as to FIGS. 1 and 2 may also apply to FIGS. 3 and 4, and vice versa.

[0100] According to FIGS. 5 to 7, there are multiple current limiting regions 5 per first region 21. Concerning the parameters d, D, B, L as stated above for the case of a single current limiting region 5 per first region 21, the same applies for the case for multiple current limiting regions 5 per first region 21, wherein L corresponds to an overall width of all the respective current limiting regions 5, compare, for example, FIG. 6. By means of the plurality of current limiting regions 5, there are more design parameters to achieve an optimized first region.

[0101] In case of just one current limiting region 5 in the direction perpendicular to the gate electrode 33 and/or the first electrode 31, see FIG. 5, the overall width L is the same as a width W of an individual, insular current limiting region 5 as illustrated in FIG. 4.

[0102] However, according to FIG. 5 there is one stripe of subsequent current limiting regions 5 extending in parallel with the electrodes 31, 33. Seen in top view, the current limiting regions 5 are of rectangular or square shape, optionally with rounded corners, each having the width W and a length extent V. For example, V is between 0.5 L and 100 L or is between 0.5 L and 10 L or is between 0.7 L and 5 L.

[0103] For example, a distance Zs between adjacent current limiting regions 5 along the stripe is between 10% and 75% or between 10% and 40% of the width W and/or of the length extent V. The individual current limiting regions 5 in the stripe can be arranged in an equidistant manner or, other than shown in FIG. 5, with varying distances to one another. These aspects may also apply for all other embodiments, individually or collectively.

[0104] Other than shown, the current limiting regions 5 need not be of square shape, seen in top view, but can also be of rectangular, hexagonal, regular or irregular polygonal or circular shape, seen in top view. The same applies for all other embodiments.

[0105] According to FIGS. 5 to 7, all the current limiting regions 5 per first region 21 are of the same shape. This is not absolutely necessary. That is, differently shaped current limiting regions 5 may be combined within one first region 21.

[0106] There can be N stripes of the current limiting regions 5 between the electrodes 31, 33, where N is a natural number larger than or equal to two. For example, N is at most ten or is at most four. According to the example of FIG. 6, N is two. For example, it applies that 0.1 B/NW0.99 B/N or 0.4 B/NW0.95 B/N or 0.7 B/NW0.90 B/N. Alternatively, or additionally, for example, a distance Zt between adjacent current limiting regions 5 in a traverse direction perpendicular to the stripes is between 10% and 75% or between 10% and 40% of the length extent V. Alternatively, or additionally, for example, it applies that 0.1 B/NV100 B/N or 0.4 B/NV10 B/N or 0.7 B/NV5 B/N. The current limiting regions 5 can be arranged in an equidistant manner in parallel as well as perpendicular to the electrodes 31, 33.

[0107] As shown in FIG. 6, all the N stripes have the same number of current limiting regions 5 so that there are in each case K current limiting regions 5 next to one another in a direction in parallel with the stripes. Consequently, a regular array of NK current limiting regions 5 is formed, and all the current limiting regions 5 are of the same shape.

[0108] However, this is not necessary. That is, current limiting regions 5 of different shapes and sizes can be combined with each other, and there can be different numbers K of current limiting regions 5 per stripe and/or different numbers N of current limiting regions 5 in the direction in parallel with the width L. For example, there are current limiting regions 5 of different widths W so that there may be rows in parallel with the direction along the width L having a single broad current limiting region 5 and alternating with rows having a plurality of narrower current limiting regions 5, by way of example.

[0109] In FIG. 7 it is illustrated that N is three. As an option, the stripe most distant from the first electrode 31 reaches beyond the gate insulator layer 4. However, other than shown in FIG. 7, all the stripes can be distant from the gate electrode 33, for example, seen in top view of the top side 20.

[0110] Each one of the stripes of FIG. 7 can be composed of multiple current limiting regions 5, as in FIGS. 5 and 6, or there is only a single current limiting region 5 per stripe, as in FIGS. 1 to 4. The same applies for all other embodiments.

[0111] The current limiting regions 5 of FIGS. 5 to 7 are of shallow design, compare, for example, FIG. 3 above. It is also possible that all or some of the current limiting regions 5 per first region 21 are of the deep design as depicted in context with FIG. 4.

[0112] Otherwise, the same as to FIGS. 1 to 4 may also apply to FIGS. 5 to 7, and vice versa.

[0113] FIGS. 8 to 11 show a simulated isothermal output J.sub.D vs. V.sub.DS at a gate-source voltage V.sub.GS=15 V and at a temperature of 300 K, and the electrothermal short-circuit waveforms at a drain-source voltage V.sub.DS=600 V and at V.sub.GS,Swing=5 V/+15V for a semiconductor device 1, E1 of FIG. 1, compared to a corresponding reference MOSFET design 9 without any current limiting region, see FIGS. 8 and 9. In FIGS. 10 and 11, corresponding data is shown for two semiconductor device 1, E2, E3 having a deep current limiting region 5 as illustrated in FIG. 4. In the device E1 corresponding to FIG. 1, the quotient d/D of the depth d of the current limiting region 5 and the depth D of the first region 21 is 0.65. The devices E2 and E3 corresponding to FIG. 4 have quotients d/D of 1.40 and 2.00, respectively, wherein D refers to the depth of the first region 21 of FIG. 1. The quotient L/B of the length L of the current limiting region 5 and the width B of the first region 21 is 0.5.

[0114] It can be noted that the achieved reduction of a maximum saturation current I.sub.SAT,peak during short-circuit is larger than the increase of the resistance in the on-state, R.sub.DS,on. Since the energy the device is subjected to during short circuit is directly related to the maximum value of I.sub.SAT, the semiconductor devices 1 described herein improve the short-circuit withstanding time without significantly affecting the conduction losses.

[0115] In FIG. 12, a method for producing the semiconductor devices 1 is illustrated. In a method step S1, the semiconductor body 2 is provided. For example, the semiconductor body 2 provides the drift region 23. Then, in a method step S2, the first region 21 and the well region 22 are formed in the semiconductor body 2, as well as the plug region 25.

[0116] Next, in step S3 at least one recess is etched into the first region 21 and the at least one recess is filled with the at least one electrically insulating material so that the at least one current limiting region 5 per first region 21 is created.

[0117] Then, in step S4, the gate insulator layer 4 is applied, followed by step S5 in which the gate electrode 33 and the first electrode 31 are applied to the semiconductor body 2, and optionally the second electrode 32 as well.

[0118] The method steps may not necessarily be performed in the stated order. Further, it is possible that the method steps may be intermixed, for example, some of the electrodes 31, 32, 33 may be applied before the etching, and some of the electrodes 31, 32, 33 may be applied after the etching.

[0119] In FIG. 13 an example of the semiconductor device 1 is shown in top view. It can be seen that the stripe of the gate electrode 33 is located, for example, in a symmetric manner, between two stripes of a half of the first electrode 31 and, thus, between two stripes of the first region 21 having the current limiting region 5. The structure in FIG. 13 corresponds to a unit cell which can be multiplied so that a plurality of the unit cells can be arranged next to one another.

[0120] This stripe design can also be applied to the embodiments of FIGS. 1 and 3 to 7 analogously; in FIG. 2, this kind of symmetric design is already shown.

[0121] Otherwise, the same as to FIGS. 1 to 12 may also apply to FIG. 13, and vice versa.

[0122] Further, see FIG. 14, the semiconductor device 1 can also be of a cellular design, seen in top view, so that a rectangular or square unit cell can arise. For example, in the centre of the unit cell there is the first electrode 31 which is surrounded by the gate electrode 33 in a frame-like manner. Such unit cells can be arranged two-dimensionally so that the semiconductor device 1 can comprise a large number of such unit cells.

[0123] Otherwise, the same as to FIG. 13 may also apply to FIG. 14, and vice versa.

[0124] The components shown in the figures follow, unless indicated otherwise, exemplarily in the specified sequence directly one on top of the other. Components which are not in contact in the figures are exemplarily spaced apart from one another. If lines are drawn parallel to one another, the corresponding surfaces may be oriented in parallel with one another. Likewise, unless indicated otherwise, the positions of the drawn components relative to one another are correctly reproduced in the figures.

[0125] The invention described here is not restricted by the description on the basis of the exemplary embodiments. Rather, the invention encompasses any new feature and also any combination of features, which includes in particular any combination of features in the patent claims, even if this feature or this combination itself is not explicitly specified in the patent claims or exemplary embodiments.

LIST OF REFERENCE SIGNS

[0126] 1 semiconductor device [0127] 2 semiconductor body [0128] 20 top side of the semiconductor body [0129] 21 first region (source region or emitter region) [0130] 22 well region [0131] 23 drift region [0132] 24 second region (drain region or collector region) [0133] 25 plug region [0134] 31 first electrode (source electrode or emitter electrode) [0135] 32 second electrode (drain electrode or collector electrode) [0136] 33 gate electrode [0137] 4 gate insulator layer [0138] 5 current limiting region [0139] 9 comparative example of a semiconductor device [0140] B width of the first region [0141] d depth of the current limiting region [0142] D depth of the first region [0143] E1 first example of the semiconductor device [0144] E2 first example of the semiconductor device [0145] E3 first example of the semiconductor device [0146] L length of the current limiting region [0147] M line of mirror symmetry [0148] S . . . method step [0149] T time in us [0150] J.sub.D current density in the drain region in A/cm.sup.2 [0151] V.sub.DS voltage between the drain electrode and the source electrode in V [0152] V length extent of the current limiting regions [0153] W with of an insular current limiting region [0154] Zs distance between current limiting regions along a stripe [0155] Zt distance between current limiting regions in a traverse direction