Device for determining existence of damage in semiconductor device and method related thereto

Abstract

A semiconductor device may include a semiconductor substrate, a wire placed along at least a portion of a perimeter of the semiconductor substrate, and processing circuitry connected to the wire, the processing circuitry to, based on a signal from the wire, determine whether or not the semiconductor device is damaged.

Claims

1. A semiconductor device comprising: a semiconductor substrate; a single wire placed only on a top surface of the semiconductor substrate along at least a portion of a perimeter of the semiconductor substrate, the single wire running along the at least a portion of the perimeter in a single conductive path; and processing circuitry connected to the single wire, the processing circuitry to, based on a signal from the single wire, determine whether or not the semiconductor device is damaged.

2. The semiconductor device of claim 1, comprising a seal ring placed along the perimeter of the semiconductor substrate, wherein the single wire is placed near the seal ring such that the seal ring surrounds the single wire.

3. The semiconductor device of claim 2, wherein the single wire is positioned at a distance of 1-100 micrometers from the seal ring.

4. The semiconductor device of claim 1, wherein the processing circuitry is further configured to generate an input signal and to compare the input signal to the signal from the single wire to determine whether or not the semiconductor device is damaged.

5. The semiconductor device of claim 4, wherein the signal from the single wire comprises a voltage change detected from a first end of the single wire to a second end of the single wire.

6. The semiconductor device of claim 1, wherein the processing circuitry is further configured, based on the signal from the single wire, to determine a location at which the semiconductor device is damaged.

7. A device comprising: a support structure comprising an integrated circuit, a single wire placed only on a top surface of the support structure along at least a portion of a perimeter of the support structure, the single wire running around the support structure in a single conductive path; and a controller configured to receive a signal from the single wire and, based on the signal, to determine if the support structure is damaged.

8. The device of claim 7, comprising a seal ring placed along the perimeter of the support structure, wherein single wire is placed near the seal ring such that the seal ring surrounds the single wire.

9. The device of claim 8, wherein the single wire is positioned at a distance of 1-100 micrometers from the seal ring.

10. The device of claim 7, wherein the controller is further configured to determine damage to the support structure, based upon the signal from the single wire, during an assembly process of the device.

11. The device of claim 7, wherein the controller is further configured to generate an input signal and to compare the input signal to the signal from the single wire to determine whether or not the support structure is damaged.

12. The device of claim 11, wherein the signal received from the single wire comprises a voltage change detected from a first end of the single wire to a second end of the single wire.

13. The device of claim 7, wherein the controller is further configured, based on the signal from the single wire, to determine a location at which the support structure is damaged.

14. A method of determining damage in a semiconductor substrate, the method comprising: receiving a signal from a single wire placed only on a top surface of the semiconductor substrate along at least a portion of a perimeter of the semiconductor substrate, the single wire running along the at least a portion of the perimeter in a single conductive path; and based on the signal, determining whether or not the semiconductor substrate is damaged.

15. The method of claim 14, wherein receiving the signal comprises detecting a voltage change from a first end of the single wire to a second end of the single wire.

16. The method of claim 15, further comprising generating an input signal, and comparing the input signal to the signal from the single wire, such that determining whether or not the semiconductor substrate is damaged is based on the comparison of the input signal to the signal from the single wire.

17. The method of claim 16, wherein comparing comprises determining if there is a voltage change from a first end of the single wire to a second end of the single wire.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) For a better understanding of embodiments of the invention and to show how the same can be carried into effect, reference will now be made, purely by way of example, to the accompanying drawings in which like numerals designate corresponding elements or sections throughout.

(2) In the accompanying drawings:

(3) FIG. 1A is a schematic illustration of a device for determining existence of damage in a substrate or support structure of the device, according to some embodiments of the invention;

(4) FIGS. 1B and 1C are schematic illustrations of the device including a wire placed within a support structure of the device, according to some embodiments of the invention;

(5) FIGS. 1D and 1E are schematic illustrations of the device including the wire placed within an integrated circuit of the device, according to some embodiments of the invention;

(6) FIG. 1F is a schematic illustration of the device including processing circuitry positioned external to the integrated circuit of the device, according to some embodiments of the invention;

(7) FIG. 2 is a schematic illustration of the device including wires placed at different positions along a perimeter of the support structure of the device, according to some embodiments of the invention;

(8) FIGS. 3A and 3B are schematic illustrations of the device including wires placed in different layers of the support structure of the device, according to some embodiments of the invention; and

(9) FIG. 4 is a flowchart of a method of determining damage in a semiconductor substrate, according to some embodiments of the invention.

(10) It will be appreciated that, for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.

DETAILED DESCRIPTION OF THE INVENTION

(11) In the following description, various aspects of the present invention are described. For purposes of explanation, specific configurations and details are set forth in order to provide a thorough understanding of the present invention. However, it will also be apparent to one skilled in the art that the present invention can be practiced without the specific details presented herein. Furthermore, well known features may have been omitted or simplified in order not to obscure the present invention. With specific reference to the drawings, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of the present invention only and are presented in the cause of providing what is believed to be the most useful and readily understood description of the principles and conceptual aspects of the invention. In this regard, no attempt is made to show structural details of the invention in more detail than is necessary for a fundamental understanding of the invention, the description taken with the drawings making apparent to those skilled in the art how the several forms of the invention can be embodied in practice.

(12) Before at least one embodiment of the invention is explained in detail, it is to be understood that the invention is not limited in its application to the details of construction and the arrangement of the components set forth in the following description or illustrated in the drawings. The invention is applicable to other embodiments that can be practiced or carried out in various ways as well as to combinations of the disclosed embodiments. Also, it is to be understood that the phraseology and terminology employed herein is for the purpose of description and should not be regarded as limiting.

(13) Reference is now made to FIG. 1A, which is a schematic illustration of a device 100 for determining existence of damage in a substrate or support structure of device 100, according to some embodiments of the invention. FIG. 1A shows a schematic top view of device 100.

(14) Reference is also made to FIGS. 1B and 1C, which are schematic illustrations of device 100 including a wire 130 placed within a support structure 110 of device 100, according to some embodiments of the invention. FIG. 1B shows a schematic top view of device 100. FIG. 1C shows a schematic section view of device 100 along line AA of FIG. 1B.

(15) Reference is also made to FIGS. 1D and 1E, which are schematic illustrations of device 100 including wire 130 placed within an integrated circuit 120 of device 100, according to some embodiments of the invention. FIG. 1D shows a schematic top view of device 100. FIG. 1E shows a schematic section view of device 100 along line BB of FIG. 1D.

(16) Reference is also made to FIG. 1F, which is a schematic illustration of device 100 including processing circuitry 140 positioned external to integrated circuit 120 of device 100, according to some embodiments of the invention.

(17) Device 100, such as semiconductor device, may include a substrate or support structure 110. Support structure 110 may be made of or may include a semiconductor material such as, e.g., silicon. Support structure 110 may be a substrate including an integrated circuit 120.

(18) Device 100 may include a wire (e.g., a metal wire) 130. Wire 130 may be connected to, e.g. input/output 122 of integrated circuit 120. In some embodiments, wire 130 may be placed on a top flat surface of support structure 110 (e.g., as shown in FIG. 1A). Wire 130 may be placed along at least a portion of an outer edge or a perimeter 111 of support structure 110. Wire 130 may surround integrated circuit 120 and may be placed in a region between integrated circuit 120 and outer edge or perimeter 111 of support structure 110. For example, device 100 may include a seal ring 114 placed along outer edge or perimeter 111 of support structure 110 and surrounding integrated circuit 120 (e.g., as shown in FIG. 1A). In this example, wire 130 may be placed in a region between integrated circuit 120 and seal ring 114 (e.g., adjacent to seal ring 114) such that seal ring 114 surrounds wire 130 (e.g., as shown in FIG. 1A). Wire 130 may be placed adjacent to seal ring 114, for example at a distance of 1-100 micrometer from seal ring 114. The distance of wire 130 from seal ring 114 may be dictated by, for example, design constraints or considerations of device 100 and/or by respective manufacturing process constraints or considerations of device 100. In some embodiments, the distance of wire 130 from seal ring 114 may be set to be close to a minimal distance allowed according to the design constraints of device 100, e.g. the wire 130 is placed as near as possible to the seal ring 114.

(19) In some embodiments, wire 130 may be placed within support structure 110. For example, wire 130 may be placed within support structure 110, e.g., in a region between integrated circuit 120 and outer surfaces 112 of support structure 110, e.g., as schematically shown in FIGS. 1B-1C.

(20) In some embodiments, wire 130 may be placed within integrated circuit 120. For example, wire 130 may be placed within integrated circuit 120, e.g., along outer surfaces 112 of support structure 110, e.g., as schematically shown in FIGS. 1B-1C.

(21) Device 100 may include one or more wires (e.g., such as wire 130) placed in different portions of support structure 110 than shown or described.

(22) Device 100 may include processing circuitry (e.g., a controller) 140. In some embodiments, processing circuitry 140 may be part of integrated circuit 120 (e.g., as schematically shown in FIGS. 1A-1E). In some embodiments, processing circuitry 140 may be positioned external to integrated circuit 120. For example, processing circuitry 140 may be positioned on a support structure 150, wherein support structure 150 is external to and is not part of support structure (e.g. semiconductor substrate) 110, e.g., as schematically shown in FIG. 1F. In some embodiments, processing circuitry 140 may be included in or may be connected to an input/output (IO) pad or circuitry positioned between integrated circuit 120 and seal ring 114. Processing circuitry 140 may be connected to wire 130. Processing circuitry 140 may determine, based on a signal from wire 130, whether or not support structure 110 is damaged. Processing circuitry 140 may be analog, digital or a combination thereof.

(23) For example, during an assembly process, or at another time, support structure 110 of device 100 may be damaged, e.g., broken. Such damage typically occurs along outer edge or perimeter 111 of support structure 110. Damage of support structure 110 may cause damage of wire 130 placed along outer edge or perimeter 111 of support structure 110. Based on the signal from wire 130, processing circuitry 140 may determine whether or not wire 130 and thus support structure 110 are damaged. For example, if no signal is received from wire 130 or if the signal from wire 130 is different from the input signal provided to wire 130, it may be determined that wire 130 and thus supporting structure 110 are damaged. The signal may be digital or analog.

(24) Reference is now made to FIG. 2, which is a schematic illustration of device 100 including wires 131, 132 placed at different positions along perimeter 111 of support structure 110 of device 100, according to some embodiments of the invention. FIG. 2 shows a schematic top view of device 100.

(25) Device 100 may include two or more wires, for example a wire 131 and a wire 132. Each of wires 131, 132 may be placed on the top flat surface of support structure 110 in the region between integrated circuit 120 and outer edge or perimeter 111 or seal ring 114 along a different portion of outer edge or perimeter 111 of support structure 110 of device 100. Each of wires 131, 132 may be connected to processing circuitry 140. Processing circuitry 140 may determine, based on signals from wires 131, 132, a location at which support structure 110 is damaged (e.g., as described above with respect to FIGS. 1A-1F). For example, if no signal from wire 131 is received, it may be determined that wire 131 and a portion of support structure 110 along wire 131 are damaged.

(26) While two wires 131, 132 are shown, device 100 may include a plurality of wires each placed along a different portion of outer edge or perimeter 111 of support structure 110.

(27) Reference is now made to FIGS. 3A and 3B, which are schematic illustrations of device 100 including wires 133, 134, 135 placed in different layers 110a, 110b, 110c of support structure 110 of device 100, according to some embodiments of the invention. FIG. 3A shows a schematic top view of device 100. FIG. 3B shows a schematic section view of device 100 along line CC of FIG. 3A.

(28) Support structure 110 of device 100 may include two or more layers, for example layers 110a, 110b, 100c schematically shown in FIG. 3B. Device 100 may include two or more wires, for example a wire 133, a wire 134 and a wire 135, each placed in one or more of the layers of support structure 110, e.g., in regions between integrated circuit 120 and outer surfaces 112 of support structure 110, as schematically shown in FIG. 3B. Each of wires 133, 134, 135 may be connected to processing circuitry 140. Processing circuitry 140 may determine, based on signals from wires 133, 134, 135, a location at which support structure 110 is damaged (e.g., as described above with respect to FIGS. 1A-1F). For example, if no signal from wire 133 is received, it may be determined that wire 133 and layer 110a of support structure 110 accommodating wire 133 are damaged.

(29) While three layers 110a, 110b, 110c and three wires 133, 134, 135 are shown, support structure 110 may include a plurality of layers and device 100 may include a plurality of wires, wherein each of the wires may be placed in one or more of the plurality of layers. For example, a single wire may be placed in two layers of supporting structure 110. In another example, a single layer may include two or more wires each placed, for example, along a different portion of the perimeter of support structure 110 (e.g., as described above with respect to FIG. 2).

(30) Reference is now made to FIG. 4, which is a flowchart of a method of determining damage in a semiconductor substrate, according to some embodiments of the invention.

(31) In operation 202, a signal from a wire placed along at least a portion of a perimeter of a semiconductor substrate may be received. For example, the semiconductor substrate and the wire may be similar to support structure 110 and wire 130, respectively, described above with respect to FIGS. 1A-1F. The signal may be generated by a circuit (e.g., processing circuitry 140) within the semiconductor placing a voltage on the wire at a first end of the wire; damage to the wire alters the voltage detected at a second end of the wire.

(32) In operation 204, based on the signal, it may be determined whether or not the semiconductor substrate is damaged. For example, existence or absence of damage may be determined by processing circuitry 140 as described above with respect to FIGS. 1A-1F.

(33) In some embodiments, the semiconductor substrate may include a plurality of wires each placed along a different portion of the perimeter of semiconductor substrate (e.g., as described above with respect to FIG. 2). In operation, based on the signals from the plurality of wires, a location at which the semiconductor substrate is damaged may be determined (e.g., as described above with respect to FIG. 2).

(34) In some embodiments, the semiconductor substrate may include a plurality of layers and a plurality of wires, wherein each of the wires may be placed in one or more of the plurality of layers (e.g., as described above with respect to FIGS. 3A and 3B). In operation, based on the signals from the plurality of wires, a location at which the semiconductor substrate is damaged may be determined (e.g., as described above with respect to FIGS. 3A and 3B).

(35) Embodiments of the invention may provide simple solution for determining existence or absence of damage in semiconductor substrates of semiconductor devices (e.g., bare semiconductor devices). Embodiments of the invention may reduce time and engineering efforts involved in failure analysis of damaged semiconductor devices.

(36) In the above description, an embodiment is an example or implementation of the invention. The various appearances of one embodiment, an embodiment, certain embodiments or some embodiments do not necessarily all refer to the same embodiments. Although various features of the invention can be described in the context of a single embodiment, the features can also be provided separately or in any suitable combination. Conversely, although the invention can be described herein in the context of separate embodiments for clarity, the invention can also be implemented in a single embodiment. Certain embodiments of the invention can include features from different embodiments disclosed above, and certain embodiments can incorporate elements from other embodiments disclosed above. The disclosure of elements of the invention in the context of a specific embodiment is not to be taken as limiting their use in the specific embodiment alone. Furthermore, it is to be understood that the invention can be carried out or practiced in various ways and that the invention can be implemented in certain embodiments other than the ones outlined in the description above.

(37) The invention is not limited to those diagrams or to the corresponding descriptions. For example, flow need not move through each illustrated box or state, or in exactly the same order as illustrated and described. Meanings of technical and scientific terms used herein are to be commonly understood as by one of ordinary skill in the art to which the invention belongs, unless otherwise defined. While the invention has been described with respect to a limited number of embodiments, these should not be construed as limitations on the scope of the invention, but rather as exemplifications of some of the preferred embodiments. Other possible variations, modifications, and applications are also within the scope of the invention. Accordingly, the scope of the invention should not be limited by what has thus far been described, but by the appended claims and their legal equivalents.