Method for manufacturing a set of electronic components on the front of a semiconductor substrate

Abstract

The invention concerns a method of manufacturing an assembly of electronic components on a front surface of a semiconductor substrate comprising a plurality of field areas, each field area comprising at least one field and each field comprising at least one electronic component, the method comprising a plurality of photolithography steps to form a stack of layers forming each electronic component, each photolithography step defining a mask level and comprising the application of a mask successively on each field in photolithography equipment, the positioning of said mask on each field being performed relative to a reference mask level, one of the masks being designated as identification mask. The manufacturing method is remarkable in that: at the photolithography step defining a mask level associated with the identification mask, said mask is positioned with a predetermined offset with respect to the reference mask level, the offset being different for each field area, the electronic component(s) of a field area have an identification element appearing as a predetermined offset between a pattern defined at the reference mask level and a pattern defined at the identification mask level.

Claims

1. A method, comprising: manufacturing an assembly of electronic components on a front surface of a semiconductor substrate that includes a plurality of field areas, each field area including at least one field and each field including at least one electronic component, the manufacturing including: performing a first photolithography step for an opening of contacts of electronic components; performing a second plurality of photolithography steps forming a stack of layers forming each electronic component, each second photolithography step defining a mask level and applying a mask successively on each field in photolithography equipment, a positioning of the mask on each field being performed relative to a reference mask level, one of the masks being an identification mask, the performing including: applying the mask that corresponds to the identification mask at the first photolithography step for the opening of contacts; at the first photolithography step for the opening of contacts, defining a mask level that corresponds to the identification mask, positioning the identification mask with a predetermined offset with respect to the reference mask level, the offset being different for each field area, the electronic component(s) of a field area exhibit an identification element appearing as the predetermined offset between a pattern defined at the reference mask level and a pattern defined at the identification mask level.

2. The manufacturing method according to claim 1, wherein the predetermined offset varies between a minimum optically-detectable offset and a maximum offset that degrades the performance of the electronic components.

3. The manufacturing method according to claim 2, wherein the predetermined offset comprises a first offset amplitude along a first axis of a main plane parallel to the front surface of the substrate, and a second offset amplitude along a second axis of the main plane.

4. The manufacturing method according to claim 1, wherein the reference mask level is defined by a third photolithography step, prior to the first photolithography step for the opening of contacts, for the forming of a last metallization layer of the stack of layers forming each electronic component.

5. The manufacturing method according to claim 1, wherein the predetermined offset has a first offset amplitude and a second offset amplitude, in the range from 1 m to 100 m.

6. The manufacturing method according to claim 1, wherein each field area comprises a single field.

7. The manufacturing method according to claim 1, wherein each field comprises a single electronic component.

8. The manufacturing method according to claim 1, wherein the electronic components comprise high electron mobility transistors based on III-N materials.

9. A method, comprising: forming plurality of electronic components on a semiconductor substrate, each component including an identification element that enables, after singulation of the components, to identify back a location of the components on the substrate, the substrate includes a first area having a first field, a second area having a plurality of second fields, and a third area having a plurality of third fields, the forming the plurality of electric components including: forming a stack of layers with a plurality of photolithography steps in photolithography equipment; for each first photolithography step, applying a mask successively on each of the first field, the plurality of second fields, and the plurality of third fields; and forming an identification mask with a plurality of offsets with respect to a reference mask, each offset being different for each of the first, second, and third fields, wherein: each identification element comprises a first pattern and a second pattern such that the first pattern and the second pattern are situated at different layers of the multilayer structure, the first pattern is covered by the second pattern, and a predetermined offset exists between the first pattern and the second pattern; and an area of the first pattern is entirely contained within an area of the second pattern, as viewed from above the main plane.

10. The method of claim 9, wherein forming the identification mask includes forming a second photolithography step that is after the first photolithography steps.

11. The method of claim 10, wherein forming the identification mask includes forming a plurality of contact openings with each of the plurality of electronic components.

12. The method of claim 11, wherein each offset is in the range of 1 micrometer and 100 micrometers.

13. The method of claim 9, wherein the first field, each of the plurality of second fields, and each of the plurality of third fields are each a single electronic component.

14. The method of claim 13, wherein each of the plurality of the second fields is a first type of electronic component and the first field is a second type of electronic component.

15. The method of claim 14, wherein the plurality of third fields comprise a third type of electronic component.

16. The method of claim 9, wherein the layer with the first pattern is a contact opening layer.

17. An electronic component, comprising: a substrate; a multilayer structure on the substrate; and an identification element comprising a first pattern and a second pattern, the first pattern and the second pattern at different layers of the multilayer structure, the first pattern covered by the second pattern, a predetermined offset between the first pattern and the second pattern, the predetermined offset comprises a first offset amplitude along a first axis of a main plane parallel to the front surface of the substrate, and a second offset amplitude along a second axis of the main plane, wherein an area of the first pattern is entirely contained within an area of the second pattern, as viewed from above the main plane.

18. The electronic component according to claim 17, wherein the first offset amplitude and the second offset amplitude are in the range from 1 m to 100 m, inclusive.

19. The electronic component according to claim 17, wherein the predetermined offset varies between a minimum optically-detectable offset and a maximum offset that degrades the performance of the electronic component.

20. The electronic component according to claim 17, wherein the layer with the first pattern is a contact opening layer, and the layer with the second pattern is a metal layer.

21. The electronic component according to claim 17, wherein the layer with the first pattern is a contact opening layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other features and advantages of the invention will appear from the following detailed description in relation with the appended drawings, in which:

(2) FIG. 1 shows an electronic structure formed of an assembly of electronic components arranged on the front surface of a semiconductor substrate, obtained by a manufacturing method according to the invention;

(3) FIG. 2a shows an alignment of patterns conventionally performed between a mask level L.sub.n and a reference mask level L.sub.ref;

(4) FIG. 2b shows several possibilities of predetermined offset D.sub.ZC between the patterns of an identification mask level L.sub.i and the patterns of a reference mask level L.sub.ref, said predetermined offset D.sub.ZC being applied during a photolithography step of the manufacturing method according to the invention;

(5) FIG. 2c shows an example of implementation of the manufacturing method according to the invention, with predetermined offsets D.sub.ZC applied to each field area ZC1, ZC2, ZC3, ZC4, ZC5 of the substrate having the electronic components formed thereon;

(6) FIG. 3a shows an alignment of marks conventionally performed between a mask level L.sub.n and a reference mask level L.sub.ref;

(7) FIG. 3b shows several possibilities of predetermined offset D.sub.ZC between the alignment mark of an identification mask level L.sub.i and the alignment mark of a reference mask level L.sub.ref, said predetermined offset being performed during a photolithography step of the manufacturing method according to the invention.

(8) The figures are simplified representations which, for readability purposes, are not necessarily to scale. The same reference numerals in the drawings may be used for elements of same nature. The different possibilities (variants and embodiments illustrated and/or detailed in the following description) should be understood as being non-exclusive from one another and may be combined together.

DETAILED DESCRIPTION OF THE INVENTION

(9) The invention relates to an assembly of electronic components. Electronic component designates any component of micrometer-range to millimeter-range size, formed of a stack of layers, capable of using electric currents to transmit, process, or store information. Each electronic component may thus be formed of or comprise for example a resistor, a capacitor, a coil, a transistor, an integrated circuit, any combination or any assembly of these elements, or also other elements or assemblies of elements well known by those skilled in the art. Preferably, but without for this to be limiting for the invention, the electronic components may in particular comprise high electron mobility transistors formed on a substrate based on III-N materials.

(10) More generally, electronic components 3 are formed on a front surface of a semiconductor substrate 1 (FIG. 1). Substrate 1 preferentially appears in the form of a circular wafer, having a diameter in the range from 100 mm to 450 mm and a thickness in the range from 100 to 1,500 micrometers. Semiconductor substrate 1 may comprise any semiconductor material, for example, silicon, and more specifically, as previously mentioned, a stack of binary, ternary, or quaternary III-N materials, such as for example gallium nitride (GaN), aluminum gallium nitride (AlGaN), etc.

(11) Of course, the invention is by no way limited to such shapes, dimensions, or composition of semiconductor substrate 1.

(12) The front surface of semiconductor substrate 1 extends in a main plane (x, y) and the stack of layers forming the electronic components is formed along an axis z normal to this plane (x, y). The forming of this stack requires a succession of steps of manufacturing, namely steps of layer deposition, of lithography to define the structuring of said layer, of etching to structure the layer, of surface treatment, etc.

(13) As reminded in the introductive portion of the present application, during a photolithography step, the application of the photolithography mask corresponding to the step and the exposure to light are performed field 2 by field 2. A field 2 (also called exposure field 2) may comprise a single electronic component 3 or a plurality of electronic components 3, typically between two and several hundreds. For simplification in FIG. 1, components 3 have only been shown on four fields 2, in the case in point nine components 3 per field 2.

(14) As shown in FIG. 1, the front surface of semiconductor substrate 1 comprises a plurality of field areas ZC (the example of FIG. 1 schematically shows five field areas ZC1, ZC2, ZC3, ZC4, ZC5). Each field area ZC comprises one field 2 or a plurality of fields 2.

(15) Generally, the number and the distribution of the fields 2 in each field area ZC may be identical for all areas 4, or different from one area to the other.

(16) As will be subsequently described, the invention provides the possibility of gathering a plurality of fields 2 into field areas ZC, so that the fields 2 of a same area ZC have similar characteristics, while the fields 2 of different areas ZC have recognizable different characteristics.

(17) In the simplified example of FIG. 1, first area ZC1 comprises a single field, positioned at the center of semiconductor substrate 1. Second area ZC2 comprises eight fields, third area ZC3 comprises sixteen fields, fourth area ZC4 comprises twenty-four fields, and fifth area ZC5 comprises twenty fields. For simplification, the components 3 per field 2 have only been shown on two fields of second area ZC2 and on one field of the third ZC3 and fourth ZC4 field areas.

(18) The shape and the size of field areas ZC may be freely chosen, within the limit of the fact that they are formed of one or a plurality of fields 2. Preferably, when semiconductor substrate 1 is circular, areas ZC may be selected to be concentric, as in the example of FIG. 1. As a variant, each area ZC may extend over one quarter of semiconductor substrate 1, for example, half or one quarter of said substrate. Generally, areas ZC may extend over all portions of substrate 1 comprising one or a plurality of contiguous or non-contiguous fields.

(19) Returning to the manufacturing method according to the invention, such a method comprises a plurality of photolithography steps to form a stack of layers forming each electronic component 3. These steps, specifically defined to form said stack of layers, are manufacturing photolithographic steps. These photolithography steps are separated by other well known steps enabling to form the stack, such as thermal treatment, deposition, etching, cleaning, doping, or polishing steps. The different steps of forming of a stack forming an electronic component are quite conventional and known by those skilled in the art and will be only briefly discussed.

(20) The thermal treatment steps are typically carried out at temperatures in the range from 200 C. to 1,200 C., particularly to form silicon nitride or oxide layers, to degas layers, or to perform a rearrangement of the crystal lattices.

(21) The deposition steps may be performed by various known physical or chemical techniques, such as vapor deposition, sputtering, or epitaxy, for example, according to the desired type of layers and to the compatibility, particularly in terms of temperature, of the stack. The deposited layers may be of various natures: semiconductor, insulating, or conductive.

(22) The etch steps may be carried out in baths of chemical solutions (wet etching) or in plasma or reactive ion etching (dry etching) equipment. The cleaning steps are usually performed in chemical baths.

(23) Steps of surface treatment, such as chemical-mechanical polishing, may also be applied to the stack of layers to planarize certain layers or remove local overthicknesses.

(24) During each photolithography step, semiconductor substrate 1 is arranged in photolithography equipment (not shown). After a resist layer has been deposited, generally over the front surface of substrate 1, each photolithography step comprises the application of a mask successively on each field 2. When it is applied to a field 2, the latter is exposed to a light source of low wavelength, generally ultraviolet or X-ray, to project the image of the mask into the resist layer, thus defining patterns in the resist layer.

(25) Etch steps then enable to duplicate the pattern of the resist layer in the layer of the stack located underneath and thus to structure the latter. The patterns may for example be formed of an arrangement of fingers interdigited to form gate, source, and drain electrodes of a transistor, or of a network of openings to form electrically-conductive interconnection vias, or also a plurality of contact pads intended to connect each component 3. In all cases, the patterns are functional, that is, their shape and their layout are defined to make electronic component 3 functional.

(26) As an example, when electronic component 3 comprises a transistor, the stack of layers comprises an active semiconductor layer, having a plurality of interconnection layers typically formed of an alternation of uniform or structured, insulating or metallic, layers and eventually of an upper passivation layer, stacked thereon.

(27) It is usual to speak of a mask level to qualify the patterns defined by a photolithography step in a layer n of the stack. The first mask levels (L.sub.1, L.sub.2, L.sub.3, . . . ), which aim at structuring the active layer of semiconductor substrate 1, are associated with masks (m.sub.1, m.sub.2, m.sub.3, . . . ) forming patterns of very small dimensions (typically in the order of some ten or some hundred nanometers) and requiring a high resolution at the photolithography step. In addition to the accuracy of definition of the patterns on the actual mask, this high resolution includes the fact of positioning (in the main plane (x,y)) the mask m.sub.n of mask level L.sub.n very accurately with respect to the previous mask level L.sub.n-1. A photolithography step thus generally requires an accurate alignment between the successive mask levels L.sub.n. This alignment is performed by means of crosses and/or alignment marks respectively present on masks m.sub.n and printed in the layers at the different mask levels L.sub.n-1, which enable to position mask m n on a field 2 with respect to a previous mask level (corresponding to a lower level in the stack of layers).

(28) In practice, the positioning (in the main plane (x,y)) of the successive masks is performed with respect to a reference mask level L.sub.ref, which may be the first mask level implemented in the stack of layers or, more generally, a previous mask level.

(29) The higher the masks levels L.sub.n (typically, to structure the metal interconnection layers or open the contacts of the electronic components), the more masks m.sub.n form patterns of large dimensions: for example, for the last metallization stage of the stack of layers of an electronic component of field-effect transistor type, the patterns may measure in the order of from a few tens to a few hundreds of micrometers.

(30) In the manufacturing method according to the invention, a mask m.sub.n used during one of the manufacturing photolithography steps is designated as identification mask m.sub.i in the present description. The mask level L.sub.i associated with identification mask m.sub.i is called identification mask level L.sub.i hereafter.

(31) Thus, according to the invention, at the photolithography step defining the mask level L.sub.i associated with identification mask m.sub.i, said mask m.sub.i is positioned, in the main plane (x,y), with a predetermined offset D.sub.zc with respect to reference mask level L.sub.ref and offset D.sub.zc is different for each field area ZC.

(32) The electronic component(s) 3 of a field area ZC then has (have) an identification element appearing as a predetermined offset D.sub.zc, in the main plane (x,y), between a pattern defined at reference mask level L.sub.ref and a pattern defined at identification mask level L.sub.i.

(33) Thereby, after the cutting of electronic components 3, it is possible to recognize the field area ZC of substrate 1 from which each component 3 originates by measuring the predetermined offset D.sub.ZC between a pattern defined at reference mask level L.sub.ref and a pattern defined at identification mask level L.sub.i. The manufacturing method according to the invention thus enables, without carrying out an additional photolithography step (i.e., by only performing the manufacturing photolithography steps) and particularly with no additional mask to be applied, to identify the location of components 3 per area ZC of semiconductor substrate 1, by the controlled variation of the offset between identification mask level L.sub.i and reference mask level L.sub.ref, from one field area ZC to another.

(34) In the example shown in FIG. 1, the components in the fields 2 of second field area ZC2 will exhibit an identical identification element, corresponding to a predetermined offset D.sub.ZC2, but different from the identification elements of components 3 in the fields 2 of the other field areas ZC1, ZC3, ZC4, ZC5, themselves different from one another.

(35) Advantageously, to be able to locate and to reliably characterize the identification element, for each field area ZC, the predetermined offset D.sub.zc varies between a minimum optically-detectable offset and a maximum offset likely to degrade the performance of electronic components 3. Indeed, if the offset between identification mask level L.sub.i and reference mask level L.sub.ref is too large, the functional patterns present in identification mask level L.sub.i will no longer be correctly arranged in the stack of layers to provide the electronic components with the desired electric characteristics. Of course, the maximum offset will depend on the mask level L.sub.n selected to form identification mask level L.sub.i.

(36) Examples of minimum and maximum offsets are given hereafter, in reference with different choices of identification mask level L.sub.i.

(37) According to an advantageous embodiment, to avoid intervening on the most sensitive and functional layers in the stack, associated with the first mask levels, identification mask m.sub.i corresponds to the mask applied at the photolithography step for the opening of contacts of electronic components 3. This is typically the last photolithography step (last mask level) which is carried out on the stack of layers of substrate 1. It comprises defining openings in the upper passivation layer of the stack, opposite the electric contact pads of each component 3, to give access to an electric connection from component 3 to the outside.

(38) In this embodiment, reference mask level L.sub.ref is preferably defined by a photolithography step, prior than that for the opening of contacts, performed for the forming of a last metallization layer of the stack of layers: the mask level defined by this step is usually called last metal level.

(39) FIG. 2a illustrates a standard alignment, usually performed between a mask level L.sub.n and reference masking level L.sub.ref. The pattern of upper mask level L.sub.n is centered on the pattern of the lower mask level L.sub.n-1 (L.sub.ref in this specific case). In the previously-mentioned advantageous embodiment, lower mask level L.sub.n-1 is the last metal level: the associated patterns correspond to the contact metal pads. Upper mask level L.sub.n is the contact opening level: the associated patterns correspond to the window to be opened to provide access to the underlying metal contact pads. FIG. 2b shows a plurality of possible predetermined offsets D.sub.ZC, implemented during the application of the identification mask m.sub.i corresponding to the contact opening mask level (L.sub.i in the drawing). The predetermined offsets D.sub.zc are characterized:by a first offset amplitude A.sub.x along a first x axis in the main plane (x, y) parallel to the front surface of substrate 1 (FIG. 2b (i)), or by second offset amplitude A.sub.y along a second axis y in the main plane (x, y) parallel to the front surface of substrate 1 (FIG. 2b (ii)), or also by a first offset amplitude A.sub.x and a second offset amplitude A.sub.y, respectively along the first x axis and the second y axis in the main plane (x, y) (FIG. 2b (iii)).

(40) Offset amplitudes A.sub.x, A.sub.y represent the deviations with respect to a standard alignment of identification mask m.sub.i on reference mask level L.sub.ref, in the processed field 2. The standard alignment corresponds to spacings X and Y, between the patterns of two mask levels, respectively, along the x and y axes, as illustrated in FIG. 2a. It is of course required to apply measurable and recognizable offset amplitudes: the latter should thus be greater than the alignment and centering uncertainties usually encountered between the considered mask levels.

(41) It should be noted that these offset amplitudes A.sub.x, A.sub.y are predefined for each field area ZC and stored in the photolithography equipment, which will automatically implement them on application of identification mask m.sub.i (mask level L.sub.i) on each field 2, according to the field area ZC to which it belongs.

(42) In the described advantageous embodiment, the lateral dimensions of the contacts of components 3 at the last metal level (reference mask level L.sub.ref) are typically in the range from 50 to 5,000 micrometers; the lateral dimensions of the opening window in the upper passivation layer, which should be defined at the contact opening mask level (identification mask level L.sub.i), are typically in the order of from 30 to 3,000 micrometers. Thus, it is possible to apply predetermined offsets D.sub.zc for which the first A.sub.x and/or the second A.sub.y offset amplitude is (are) for example in the range from 1 micrometer to 100 micrometers, between the patterns of reference mask level L.sub.ref and the patterns of identification mask level L.sub.i as illustrated in FIG. 2b.

(43) Referring to the previously-mentioned embodiment, an example of implementation is shown in FIG. 2c. Field areas ZC are those defined in FIG. 1 and the predetermined offsets D.sub.zc, associated with each field area ZC, are the following: D.sub.zc1: A.sub.x=0, A.sub.y=0; D.sub.zc2: Ax=+10 micrometers, Ay=+10 micrometers; D.sub.zc3: Ax=10 micrometers, Ay=10 micrometers; D.sub.zc4: Ax=10 micrometers, Ay=+10 micrometers; D.sub.zc5: Ax=+10 micrometers, Ay=10 micrometers;

(44) The value of 10 micrometers for the first A.sub.x and second A.sub.y offset amplitudes is here arbitrarily provided: these amplitudes might take different values in the range from 1 to 100 micrometers. Negative values indicate an offset, with respect to the standard alignment, in the reverse direction of the considered x or y axis.

(45) After the singulation of the electronic components in the form of individual chips, it will be possible to trace back for each component its original field area ZC on substrate 1, only by observation and measurement of the predetermined offset D.sub.zc between the patterns of the last metal level (reference mask level L.sub.ref) and the patterns of the contact opening level (identification mask level L.sub.i). This offset forms an identification element which adds no complexity to the method of manufacturing the assembly of components 3 on substrate 1.

(46) According to another example of implementation, field areas ZC comprise a single field 2. Given the larger number of field areas ZC, the predetermined offsets D.sub.zc associated with each area ZC are more accurately defined than in the previous case with five field areas ZC. One may for example choose to vary amplitudes A.sub.x and A.sub.y in increasing fashion as the distance to the central field increases.

(47) After the singulation of electronic components 3 in the form of individual chips, it will be possible to trace back for each component, its original field area ZC on substrate 1, only by observation and measurement of the predetermined offset D.sub.zc between the patterns of the last metal level (reference mask level L.sub.ref) and the patterns of the contact opening level (identification mask level L.sub.i). This example of implementation provides additional accuracy regarding the original location of components 3 since each field area ZC comprises a single field. In the case where each field 2 comprises a single component 3, it is thus possible to trace back the original location of each component due to the identification element.

(48) According to a variant, the predetermined offset D.sub.zc may be defined between alignment marks or crosses and not directly between functional patterns of the considered mask levels. As illustrated in FIG. 3a, the pattern of upper mask level L.sub.n is centered on the pattern of lower mask level L.sub.n-1, due to the centering of the cross in the square, the latter forming the respective alignment marks of the two mask levels. The predetermined offsets D.sub.zc may be applied to the alignment marks (FIG. 3b i) and ii)).

(49) The identification element is then present at the level of the upper passivation layer of the stack, and has the advantage of being visible in the context of a visual examination. An observation with an optical microscope of the singulated component may thus enable to trace back the original location thereof on semiconductor substrate 1. Of course, other optical methods than the simple observation with an optical microscope may be used to analyze the identification elements, such as an optical analysis by means of pattern recognition software, for example.

(50) According to other embodiments, the identification mask(s) correspond to the mask(s) applied at the photolithography step for any mask level. The predetermined offset D.sub.zc is then adapted to the patterns of the identification L.sub.i and reference L.sub.ref mask levels.

(51) The present invention also concerns an electronic structure formed of an assembly of electronic components 3 arranged on the front surface of a semiconductor substrate 1, and capable of being formed based on the previously described manufacturing method.

(52) Semiconductor substrate 1 comprises a plurality of field areas ZC. Each area ZC comprises at least one field 2 and each field 2 comprises at least one electronic component 3. Each electronic component 3 is formed of a stack of layers. Each component 3 further comprises an identification element appearing as a predetermined offset D.sub.zc between: a pattern, defined at a reference mask level L.sub.ref during a photolithography step of the structure manufacturing method, in a layer of the stack forming said component 3, and a pattern, defined at an identification mask level L.sub.i during a subsequent photolithography step of the structure manufacturing method, in another layer of the stack.

(53) The predetermined offset is different according to the field areas ZC: a specific offset is thus representative of a field area ZC of the electronic structure.

(54) The identification element is thus recognizable and different for each field ZC, which enables, once the cutting of the electronic structure around each electronic component 3 has been performed, to be able to identify if need be the field area ZC of substrate 1 from which electronic component 3 originates.

(55) Of course, the invention is not limited to the described embodiments and alternative embodiments may be brought thereto without departing from the framework of the invention such as defined by the claims.