Abstract
We herein describe a method of manufacturing a semiconductor device having one or more trenches with an insulation layer. The one or more trenches with an insulation layer are manufactured using the steps of performing an etching process to form the one or more trenches, forming a first insulation layer on a lower surface and sidewalls of the one or more trenches, depositing a hydrophilic layer over the first insulation layer, depositing a photoresist material in the one or more trenches, wherein depositing a photoresist material comprises exposing the hydrophilic layer on an upper region of a first side of the one or more trenches, performing a wet etch process to etch the insulation layer on the sidewall of the first side of the one or more trenches to a predetermined distance below a surface of the photoresist material, removing the photoresist material, removing the hydrophilic layer, and after performing the wet etch process, removing the photoresist material, and removing the hydrophilic layer, and forming a second insulation layer on the sidewall of the first side of the one or more trenches.
Claims
1. A method of manufacturing a semiconductor device having one or more trenches with an insulation layer, wherein the one or more trenches with an insulation layer are manufactured using the steps of: performing an etching process to form the one or more trenches; forming a first insulation layer on a lower surface and sidewalls of the one or more trenches; depositing a hydrophilic layer over the first insulation layer; depositing a photoresist material in the one or more trenches, wherein depositing a photoresist material comprises exposing the hydrophilic layer on an upper region of a first side of the one or more trenches; performing a wet etch process to etch the insulation layer on the sidewall of the first side of the one or more trenches to a predetermined distance below a surface of the photoresist material; removing the photoresist material; removing the hydrophilic layer; and after performing the wet etch process, removing the photoresist material, and removing the hydrophilic layer; forming a second insulation layer on the sidewall of the first side of the one or more trenches.
2. A method according to claim 1, wherein forming a first insulation layer comprises forming a thick insulation layer, and wherein the hydrophilic layer is deposited over the thick insulation layer, and wherein forming a second insulation layer comprises forming a thin insulation layer on the sidewall of the first side of the one or more trenches, wherein the thin insulation layer is thinner than the thick insulation layer.
3. A method according to claim 1, wherein forming a first insulation layer comprises forming a thin insulation layer, and wherein forming a second insulation layer comprises forming a thick insulation layer over the thin insulation layer, wherein the thin insulation layer is thinner than the thick insulation layer.
4. A method according to claim 1, wherein the method further comprises depositing a filling material after growing the thin insulation layer.
5. A method according to claim 1, wherein the hydrophilic layer comprises nitride.
6. A method according to claim 1, wherein the hydrophilic layer has a thickness between 1000 Å and 2500 Å.
7. A method according to claim 1, wherein the step of performing a wet etch is carried out using a buffered oxide etch.
8. A method according to claim 7, wherein the buffered oxide etch comprises hydrofluoric acid.
9. A method according to claim 1, wherein forming a thick insulation layer comprises thermally growing a thick oxide layer using a local oxidation of silicon process.
10. A method according to claim 1, wherein forming a thick insulation layer comprises depositing a thick oxide layer.
11. A method according to claim 10, wherein depositing a thick oxide layer is carried out using Tetraethyl Orthosilicate (TEOS).
12. A method according to claim 1, wherein the thick insulation layer has a thickness between 1800 Å and 5000 Å.
13. A method according to claim 1, wherein growing a thin insulation layer comprises thermally growing a thin oxide layer at 900° C. to 1100° C.
14. A method according to claim 1, wherein the thin insulation layer has a thickness between 500 Å to 1800 Å.
15. A method according to claim 1, wherein the method comprises manufacturing one or more trenches with an asymmetric insulation layer.
16. A method according to claim 1, wherein the method comprises manufacturing one or more trenches with a symmetric insulation layer, and wherein depositing a photoresist material comprises exposing the hydrophilic layer on an upper region of two sides of the one or more trenches, and wherein the method further comprises: performing a wet etch process to etch the insulation layer on two sidewalls of the one or more trenches to a predetermined distance below a surface of the photoresist material; and growing a thin insulation layer on the two sidewalls of the one or more trenches.
17. A method according to claim 1, wherein the method comprises manufacturing at least two trenches each with an insulation layer, wherein a first trench is separated from a second trench by a mesa region between the two trenches; and wherein the first side of the first trench is adjacent to the first side of the second trench; and wherein depositing a photoresist material comprises exposing the hydrophilic layer in the mesa region between the first and second trenches.
18. A method according to claim 17, wherein the method further comprises removing the hydrophilic layer in the mesa region between the two trenches.
19. A method according to claim 18, wherein removing the hydrophilic layer in the mesa region comprises removing the hydrophilic layer such that a top surface of the hydrophilic layer is recessed relative to a surface of the thick oxide layer.
20. A method according to claim 17, wherein the method further comprises performing a wet etch process to etch the insulation layer on the mesa region.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0044] The present disclosure will be understood, by way of example only, from the detailed description that follows and from the accompanying drawings in which:
[0045] FIGS. 1(a) and 1(b) illustrate steps of manufacturing trenches with asymmetric insulation layers, according to the state of the art;
[0046] FIGS. 2(a) to 2(j) illustrate steps of manufacturing trenches with asymmetric insulation layers, according to an embodiment of the disclosure;
[0047] FIG. 3 illustrates schematically a semiconductor device having trenches manufactured using a method according to an embodiment of the disclosure;
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0048] FIGS. 2(a) to 2(j) illustrate steps within the manufacturing process of trenches with asymmetric insulation layers, according to an embodiment of the disclosure.
[0049] FIG. 2(a) illustrates the first step of manufacturing two trenches with asymmetric insulation layers, which is as follows: [0050] (a) Step 1 [0051] A thin oxide layer 204 is deposited on a silicon substrate 206. The thin oxide layer has thickness of approximately 500 Å to 1800 Å.
[0052] FIG. 2(b) illustrates the second step of manufacturing two trenches, which is as follows: [0053] (b) Step 2 [0054] Photolithography and then a dry etch step using plasma source to form trenches to desired depth z in the silicon substrate 206. In this embodiment, the desired depth z of the trenches is 3 μm to 6 μm.
[0055] FIG. 2(c) illustrates the third step of manufacturing two trenches, which is as follows: [0056] (c) Step 3 [0057] A thick oxide layer 204 is thermally grown or deposited on the sidewalls and bottom surface of the trenches. The thick oxide layer 204 may be deposited using TEOS. The thick oxide layer has a thickness of approximately 1800 Å to 5000 Å. [0058] A hydrophilic layer 206 such as nitride is deposited over the oxide layer 204. The nitride layer 206 has a thickness of approximately 1000 Å to 2500 Å.
[0059] FIG. 2(d) illustrates the fourth step of manufacturing two trenches, which is as follows: [0060] (d) Step 4 [0061] The trenches are filled with a photoresist material 208. [0062] The photoresist 208 is deposited such that the hydrophilic layer 206 is exposed on a first side of each trench for which asymmetric oxide will be manufactured, and in the mesa region between trenches. [0063] The first side of each trench (the side where the hydrophilic layer 206 is exposed) is the side of the trench that will be manufactured to have a thin oxide layer, whilst the side of each trench that will be manufactured to have thick oxide remains covered by the photoresist. [0064] The thickness of the photoresist is 1.0 μm to 1.5 μm for a 1.5 μm width trench.
[0065] FIG. 2(e) illustrates the fifth step of manufacturing two trenches, which is as follows: [0066] (e) Step 5 [0067] An etch process is performed on the exposed hydrophilic layer 206. The etch process can be a wet or dry etch, and stops on the thick oxide layer 204 in the mesa region. [0068] In embodiments where the hydrophilic layer 206 is nitride, the etch process may be done in plasma ambient (an atmosphere or environment of plasma, created by a mixture of gases) using CF4/HBr chemistry. [0069] The hydrophilic layer 206 is etched such that the edges of the hydrophilic layer 206 are recessed relative to the surface of the thick oxide 204.
[0070] FIG. 2(f) illustrates the sixth step of manufacturing two trenches, which is as follows: [0071] (f) Step 6 [0072] The whole wafer is immersed in a BOE (buffered oxide etch) such as 7:1 HF. The buffered oxide etchant etches the oxide layer 204 on the exposed mesa region and the trench sidewalls extending down from the exposed mesa region to a desired depth Y below the surface of the trench. [0073] The hydrophilic layer 206 creates a capillary action so that the etchant etches the oxide layer 204 along the narrow channel between the hydrophilic layer itself 206 and the silicon 202. [0074] The presence of the hydrophilic layer 206 allows control of the etch depth and uniformity of the etch process. The hydrophilic layer 206 reduces defects formed during the etch process.
[0075] FIG. 2(g) illustrates the seventh step of manufacturing two trenches, which is as follows: [0076] (g) Step 7 [0077] The photoresist is stripped (removed) using any suitable wet (such as hot phosphoric acid) or dry (such as a mixture of CF4 and HBr gases in a plasma etch chamber) chemistry.
[0078] FIG. 2(h) illustrates the eighth step of manufacturing two trenches, which is as follows: [0079] (h) Step 8 [0080] The hydrophilic layer is stripped (removed) using any suitable wet or dry chemistry. This leaves the trenches having only oxide 204 on regions not exposed in Steps 4 and 5.
[0081] FIG. 2(i) illustrates the ninth step of manufacturing two trenches, which is as follows: [0082] (i) Step 9 [0083] A thin oxide layer 210 is grown on the exposed silicon in a furnace step at 900° C. to 1100° C. The thin oxide layer grows on the first side of each trench in which the hydrophilic layer was exposed in Step 4, and in the mesa region between the trenches. [0084] The thin oxide layer has thickness of approximately 500A to 1800A.
[0085] FIG. 2(j) illustrates the tenth step of manufacturing two trenches, which is as follows: [0086] (j) Step 10 [0087] Polysilicon 212 is deposited to fill the trenches. The polysilicon 212 is planarised by etching the top of the polysilicon 212 to level off with the silicon 202 in the mesa region between the trenches.
[0088] FIG. 3 illustrates schematically a semiconductor device having trenches manufactured using a method according to an embodiment of the disclosure. In this device, the active gates T1, each have asymmetric trench oxide insulation layers, whilst the dummy (or auxiliary trenches) T2 have symmetric thick oxide insulation layers.
[0089] The active trenches T1 shown in this embodiment each have an asymmetric oxide. In this embodiment only the electron conduction channel region has thin oxide 210, and the remaining sidewall and bottom of each of the active trenches T1 have thick oxide 204. The thin oxide 210 in the channel region reduces the input capacitance (C.sub.in) and C.sub.GC. This results in reduced gate charge and faster turn-off and turn-on times, therefore reducing E.sub.ON and E.sub.OFF respectively.
[0090] Whilst the auxiliary trenches T2 are shown as having thick oxide insulation 204, alternatively the disclosed method could be used to manufacture a semiconductor device having auxiliary trenches with symmetric thin oxide or having variable oxide thickness.
[0091] FIGS. 4(a) to 4(i) shows steps in the manufacturing method of a semiconductor device, according to an embodiment of the disclosure;
[0092] FIG. 4(a) illustrates the first step of manufacturing the trenches of the semiconductor device, which is as follows: [0093] (a) Step 1 [0094] Trenches 905 are etched. [0095] An initial oxide layer 910 is formed over the trenches. The initial oxide layer 910 is a sacrificial oxidation layer. It is an oxide layer created immediately after silicon etch to create trenches. The main purpose of this layer is to remove surface roughness created by the trench etch process. Traditionally, this oxide is later removed prior to formation of the thin gate oxide. [0096] A hydrophilic layer 915 such as nitride is deposited over the initial oxide layer 910. The nitride layer 915 has a thickness of approximately 1000 Å to 2500 Å. [0097] A thin oxide layer 920 is deposited using TEOS over the hydrophilic layer 915. The thin oxide layer 920 has thickness of approximately 500 Å to 1800 Å.
[0098] FIGS. 4(b) and 4(c) illustrates the second step of manufacturing the trenches of the semiconductor device, which is as follows: [0099] (b) Step 2 [0100] Photolithography is performed to apply a photoresist mask 925 that fills the trenches, where the mask ends in the centre of one trench 930 (for example, the active trench) and at least one other trench 935 (for example, a dummy trench). This leaves half of the active trench and the dummy trench exposed, as well as the mesa region between the trenches. The mask 925 may be applied in a two-step process as shown in which the mask is deposited and then etched to expose the TEOS 920. [0101] The photoresist 925 is deposited such that the thin oxide layer 920 is exposed on a first side of each trench for which asymmetric oxide will be manufactured, and in the mesa region 940 between trenches. [0102] The first side of each trench (the side where the thin oxide layer 920 is exposed) is the side of the trench that will be manufactured to have a thick oxide layer, whilst the side of each trench that will be manufactured to have thin oxide or oxide of different thickness remains covered by the photoresist.
[0103] FIG. 4(d) illustrates the first step of manufacturing the trenches of the semiconductor device, which is as follows: [0104] (d) Step 3 [0105] A wet etch is performed on the thin oxide layer 920. The etch may be performed by immersing the whole wafer in a BOE (buffered oxide etch) such as 7:1 HF. The buffered oxide etchant etches the oxide layer 920 on the exposed mesa region 940, the exposed trench sidewalls and bottom, and the trench sidewalls extending up from the trench bottom to a desired height Y above the bottom surface of the trench. [0106] The hydrophilic layer 915 creates a capillary action so that the etchant etches the oxide layer 920 along the narrow channel between the hydrophilic layer 915 itself and the photoresist 925. [0107] The presence of the hydrophilic layer 915 allows control of the etch depth and uniformity of the etch process. The hydrophilic layer 915 reduces defects formed during the etch process.
[0108] FIG. 4(e) illustrates the first step of manufacturing the trenches of the semiconductor device, which is as follows: [0109] (e) Step 4 [0110] The photoresist is stripped (removed) using any suitable wet or dry chemistry. [0111] An etch process is performed to remove the exposed regions of the hydrophilic layer 915. The etch process can be a wet or dry etch, and stops on the initial oxide layer 910. [0112] In embodiments where the hydrophilic layer 915 is nitride, the etch process may be done in plasma ambient using CF4/HBr chemistry.
[0113] FIG. 4(f) illustrates the first step of manufacturing the trenches of the semiconductor device, which is as follows: [0114] (f) Step 5 [0115] A thick oxide layer 945 is thermally grown or deposited on the sidewalls and bottom surface of the trenches in areas without the hydrophilic layer 915 remaining. The thick oxide layer 945 may be deposited using loyal oxidation of silicon (LOCOS). The thick oxide layer 945 has a thickness of approximately 1800 Å to 5000 Å.
[0116] FIG. 4(g) illustrates the first step of manufacturing the trenches of the semiconductor device, which is as follows: [0117] (g) Step 6 [0118] An etch process is performed to remove the remaining regions of the hydrophilic layer 915 and the remaining TEOS 920.
[0119] FIG. 4(h) illustrates the first step of manufacturing the trenches of the semiconductor device, which is as follows: [0120] (h) Step 7 [0121] Photolithography is performed to apply a photoresist mask 950 that fills the active trench 930, where the mask leaves the dummy trenches 935 exposed. [0122] A wet etch process is performed that strips the dummy trenches 935 to the silicon layer.
[0123] FIG. 4(i) illustrates the first step of manufacturing the trenches of the semiconductor device, which is as follows: [0124] (i) Step 8 [0125] A thin oxidation layer 955 is grown on the dummy trenches having a constant thickness on the sidewalls and bottom surfaces. The thin oxide 955 layer may be is grown in a furnace step at 900° C. to 1100° C. The thin oxide layer 955 has thickness of approximately 500 Å to 1800 Å. [0126] The photoresist is stripped (removed) using any suitable wet or dry chemistry. [0127] Polysilicon 960 is deposited to fill the trenches. The polysilicon 960 is planarised by etching the top of the polysilicon 960 to level off with the silicon in the mesa region between the trenches.
[0128] FIG. 5 shows an example of a semiconductor device manufactured using the steps of FIGS. 4(a) to 4(h).
[0129] The skilled person will understand that in the preceding description and appended claims, positional terms such as ‘above’, ‘overlap’, ‘under’, ‘lateral’, etc. are made with reference to conceptual illustrations of an apparatus, such as those showing standard cross-sectional perspectives and those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a device when in an orientation as shown in the accompanying drawings.
[0130] It will be appreciated that all doping polarities mentioned above could be reversed, the resulting devices still being in accordance with embodiments of the present invention.
[0131] Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure, which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.
