A semiconductor structure includes a substrate, a first gate structure and a second gate structure disposed over the substrate, and an isolation feature extending through the substrate and disposed between the first gate structure and the second gate structure. A top surface of the isolation feature is above a topmost surface of the first gate structure.

A semiconductor device includes a fin structure that protrudes vertically out of a substrate, wherein the fin structure contains silicon germanium (SiGe). An epi-silicon layer is disposed on a sidewall of the fin structure. The epi-silicon layer contains nitrogen. One or more dielectric liner layers are disposed on the epi-silicon layer. A dielectric isolation structure is disposed over the one or more dielectric liner layers.

Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.

An electronic device is provided that includes a board equipped with a pair of differential transmission lines that each have an opening extending between two line terminals. Moreover, the device includes a capacitor module that includes a support and two capacitors that each have two capacitor terminals, respectively, connected to the two line terminals of one line of the pair of transmission lines. In addition, the support includes a separating region between the two capacitors that has at least one cavity disposed between the two capacitors.

A trench isolation structure and method of making the same is provided. The trench isolation structure comprises a trench in a substrate, the trench having a bottom surface and sidewalls. A polycrystalline material is at least partially in the trench and an amorphous layer is over the polycrystalline material.

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a vertical nanosheet transistor, the vertical nanosheet transistor includes a first and a second vertical nanosheet horizontally separated by a gap; a metal gate surrounding the first and the second vertical nanosheet respectively at a top, a bottom, and a left and a right sidewall thereof; and a first and a second source/drain region in contact with the first and the second vertical nanosheet; where the first and the second vertical nanosheet and the gap between the first and the second vertical nanosheet are vertically above a raised portion of a backside inter-level dielectric layer. A method of manufacturing the semiconductor structure is also provided.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a buried conductive layer including a bottom portion positioned in the substrate, and a top portion positioned in the substrate and on the bottom portion; an isolation layer positioned in the substrate; an air gap structure positioned in the isolation layer; and an in-recess spacer positioned in the substrate, surrounding the bottom portion and covered by the top portion. A top surface of the top portion and a top surface of the substrate are substantially coplanar. A bottom surface of the in-recess spacer and a bottom surface of the bottom portion are substantially coplanar. A sidewall of the in-recess spacer and a sidewall of the top portion are substantially coplanar.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a buried conductive layer including a bottom portion positioned in the substrate, and a top portion positioned in the substrate and on the bottom portion; an isolation layer positioned in the substrate; an air gap structure positioned in the isolation layer; and an in-recess spacer positioned in the substrate, surrounding the bottom portion and covered by the top portion. A top surface of the top portion and a top surface of the substrate are substantially coplanar. A bottom surface of the in-recess spacer and a bottom surface of the bottom portion are substantially coplanar. A sidewall of the in-recess spacer and a sidewall of the top portion are substantially coplanar.

A wafer configured as an ISP including a first area and a second area. The wafer, in the first area, comprises a first gate structure disposed around a first edge of a first active region and a second edge of a second active region extending along a first lateral direction and spaced from each other along the first lateral direction. The wafer, in the second area, comprises a second gate structure disposed around a third edge of a third active region and a fourth edge of a fourth active region extending along the first lateral direction and spaced from each other along the first lateral direction. The first gate structure has a first width along the first lateral direction and the second gate structure has a second width along the first lateral direction, the first width is substantially shorter than the second width.

An integrated device comprising a buried oxide layer within a trench within a top surface of a substrate. A silicon layer formed over the buried oxide layer and the top surface of the substrate.