Intrinsic biasing method for a dual DC/DC converter

Abstract

The present invention refers to a method of intrinsically biasing a dual DC/DC converter by means of an active pre-charging of the internal side of the converter prior to its connection with the batteries and a soft biasing of the batteries after the connection of the converter with the batteries. This has the advantage of having a dual DC/DC converter capable of charging isolated batteries in photovoltaic installations in a pole to ground configuration, eliminating the biasing transient that occurs when connecting the battery by means of passive resistive soft charging to the internal capacitor bus of the DC/DC converter, and also eliminating the biasing transient that occurs when starting the DC/DC converter for its normal operation.

Claims

1. An intrinsic biasing method for a dual DC/DC converter, wherein the dual DC/DC converter comprises: an internal bus on a photovoltaic solar field side which in turn comprises: a first transistor, a second transistor, a third transistor, and a fourth transistor connected in series; resistors and capacitors connected in series; wherein the transistors connected in series are connected in parallel to the resistors and the capacitors connected in series; and wherein the internal bus on the photovoltaic solar field side is connectable to a photovoltaic solar field by means of second closure means; an internal bus on a battery side which in turn comprises: a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor connected in series; resistors and capacitors connected in series; wherein the transistors connected in series are connected in parallel to the resistors and the capacitors connected in series; and wherein the internal bus on the battery side is connectable to a battery rack by means of first closure means; wherein the method comprises the following steps: i) connecting the dual DC/DC converter with the photovoltaic solar field by closing the second closure means and isolating the dual DC/DC converter from the battery rack by opening the first closure means; ii) pre-charging the internal bus on the battery side at the same voltage with respect to ground that the battery rack has with energy from the photovoltaic solar field by means of predefined switching of the transistors of the battery side and the transistors of the photovoltaic solar field side; iii) isolating the internal bus on the battery side from the internal bus on the photovoltaic solar field side until the internal bus on the battery side is biased equal to the battery rack, leaving the transistors of the internal bus on the photovoltaic solar field side open; iv) connecting the internal bus on the battery side with the battery rack, closing the first closure means; v) opening the first transistor, the fourth transistor, the fifth transistor and the eighth transistor; vi) biasing the internal bus on the battery side at a voltage with respect to ground by means of synchronized switching of the second transistor, the third transistor, the sixth transistor and the seventh transistor, wherein the synchronized switching of the transistors is carried out in periods of time T with increasing duty cycles in time increments from a minimum value equivalent to a switching time of the second transistor, the third transistor, the sixth transistor and the seventh transistor to a maximum value where the second transistor, the third transistor, the sixth transistor and the seventh transistor are closed.

2. The method of claim 1, wherein the step ii) additionally comprises the dual DC/DC converter working as a buck type converter when a voltage in the battery rack is lower than a voltage in the photovoltaic solar field.

3. The method of claim 1, wherein the step ii) additionally comprises the dual DC/DC converter working as a boost type converter when a voltage in the battery rack is higher than a voltage in the photovoltaic solar field.

4. The method of claim 2, wherein the step ii) additionally comprises: opening the sixth transistor and the seventh transistor; closing the fifth transistor and the eighth transistor; switching the first transistor, the second transistor, the third transistor, and the fourth transistor.

5. The method of claim 3, wherein the step ii) additionally comprises: opening the second transistor and the third transistor; closing the first transistor and the fourth transistor; switching the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor.

6. A dual DC/DC converter comprising: an internal bus on a photovoltaic solar field side which in turn comprises: a first transistor, a second transistor, a third transistor, and a fourth transistor connected in series; resistors and capacitors connected in series; wherein the transistors connected in series are connected in parallel to the resistors and the capacitors connected in series; and wherein the internal bus on the photovoltaic solar field side is connectable to a photovoltaic solar field by means of second closure means; an internal bus on a battery side which in turn comprises: a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor connected in series; resistors and capacitors connected in series; wherein the transistors connected in series are connected in parallel to the resistors and the capacitors connected in series; and wherein the internal bus on the battery side is connectable to a battery rack by means of first closure means; wherein the dual DC/DC converter comprises control means connected to at least the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the first closure means, the second closure means, wherein the control means are configured to carry out the intrinsic biasing method for the dual DC/DC converter defined in claim 1.

7. The dual DC/DC converter of claim 6, wherein the control means are selected from among a microcontroller, a microprocessor and an FPGA.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a dual type differential DC/DC converter connected to a photovoltaic solar field and a battery rack.

(2) FIG. 2 shows the transients experienced by the positive and negative poles of the battery rack when the dual DC/DC converter of the prior art is connected to the battery rack.

(3) FIG. 3 shows a dual type differential DC/DC converter connected to a photovoltaic solar field and a battery rack, where the dual DC/DC converter has a passive soft charge resistor and RFI filters.

(4) FIG. 4 shows a flowchart of the method of the present invention.

(5) FIG. 5 shows components that are activated to carry out the biasing of the battery rack.

DESCRIPTION OF THE INVENTION

(6) FIG. 1 shows a dual type differential DC/DC converter 10 connected to a photovoltaic solar field PV 21 and a battery rack BSS 20. The dual DC/DC converter 10 has the internal bus on the photovoltaic solar field side 11 and the internal bus on the battery side 12.

(7) The internal bus on the photovoltaic solar field side 11 has the first transistor 1B, the second transistor 2B, the third transistor 3B and the fourth transistor 4B connected in series. Additionally, the internal bus on the photovoltaic solar field side 11 has the first resistor 1R, the first capacitor 1C, the second resistor 2R and the second capacitor 2C connected in series, which in turn are connected in parallel to the four transistors 1B-4B, as shown in FIG. 1. In FIG. 1 it is also be observed that the midpoint 14 of the branch of the four transistors 1B-4B is connected to the midpoint 13 of the branch of the capacitors and resistors 1R-1C-2R-2C. The internal bus on the photovoltaic solar field side 11 is connected to ground 17, which results in the pole to ground configuration of the photovoltaic solar field side 21.

(8) The internal bus on the battery side 12 has the fifth transistor 5B, the sixth transistor 6B, the seventh transistor 7B and the eighth transistor 8B connected in series. Additionally, the internal bus on the battery side 12 has the third resistor 3R, the third capacitor 3C, the fourth resistor 4R and the fourth capacitor 4C connected in series, which in turn are connected in parallel to the four transistors 5B,6B,7B,8B, as shown in FIG. 1. In FIG. 1 it is also be observed that the midpoint 15 of the branch of the four transistors 5B-8B is connected to the midpoint 16 of the branch of the capacitors and resistors 3R-3C-4R-4C. The internal bus on the battery side 12 is not connected to ground, which results in the isolated pole configuration of the battery side 20.

(9) Finally, in FIG. 1, it can be observed that the internal bus on the photovoltaic solar field side 11 and the internal bus on the battery side 12 are connected to each other by coils and resistors. Specifically, the connection point 18A between the first transistor 1B and the second transistor 2B is connected to the connection point 18B between the fifth transistor 5B and the sixth transistor 6B, by means of the first coil 1L and the fifth resistor 5R. Additionally, the connection point 19A between the third transistor 3B and the fourth transistor 4B is connected to the connection point 19B between the seventh transistor 7B and the eighth transistor 8B, by means of the second coil 2L and the sixth resistor 6R.

(10) FIG. 2 shows the biasing transients experienced by the positive and negative poles of the battery rack when the dual DC/DC converter from the prior art is connected to the battery rack and these do not occur when applying the method of the present invention.

(11) FIG. 3 shows the dual type differential DC/DC converter 10 of FIG. 1 connected to the photovoltaic solar field 21 by means of contactors 27. Additionally, the dual DC/DC converter 10 is connected to the battery rack 20 through a soft charge configuration formed by the resistor R.sub.SC 22 and the contactors 25. And once the soft charging has finished, the battery rack 20 is connected to the dual DC/DC converter by means of the contactors 26, as known in the prior art.

(12) Continuing with FIG. 3, it is also known in the prior art that even though the internal bus on the battery side 12 of the dual DC/DC converter is not directly connected to ground in the isolated poles configuration, said internal bus on the battery side 12 is connected to ground by means of RFI filters 23 in charge of filtering out high frequencies. In the case shown in FIG. 3, the RFI filters are formed by three capacitors 23C and a resistor 23R connected in parallel and by a resistor 24 that connects each branch of the internal bus on the battery side 12 to ground.

(13) For the configuration of a dual type differential DC/DC converter 10 as shown in FIGS. 1 and 3, the present invention discloses an intrinsic biasing method for the dual DC/DC converter which, by means of a pre-charging and an internal biasing, is capable of eliminating the biasing transient when connecting the batteries to the internal bus of the dual DC/DC converter and the biasing transient when starting the dual DC/DC converter for normal operation.

(14) Therefore, the method of the present invention comprises performing an active pre-charging of the dual DC/DC converter. First, however, the dual DC/DC converter 10 has to be connected to the photovoltaic solar field PV 21 and disconnected from the battery rack BSS 20. That is, contactors 27 are closed and contactors 25 and 26 of FIG. 3 are open. Therefore, the first step of the method is to connect (FIG. 4-30) the dual DC/DC converter 10 to the photovoltaic solar field 21 by closing contactor 27 and keeping the DC/DC converter 10 isolated from the battery rack 20 by keeping contactors 25 and 26 open. Next (FIGS. 4-31), active pre-charging is carried out, which comprises equalizing in a controlled and progressive manner the internal voltage (the voltage of the internal buses of batteries 12 and PV 11) with respect to the ground of the dual DC/DC converter 10 at the voltage value which the 20 battery rack has in differential mode equidistant from ground. For example, if the battery rack 20 has a voltage in differential mode of 1000 v (500 v and +500 v with respect to GND) and the photovoltaic solar field PV 21 has a voltage of 1200 v in differential mode (between 0 v and 1200 v with respect to GND) with respect to ground, the internal buses 11 and 12 of the dual DC/DC converter 10 are pre-charged at 1000 v in differential mode (between 0 v and 1000 v with respect to GND) with respect to ground with energy from the photovoltaic solar field PV 21. Note that the dual DC/DC converter 10 is non-isolated and the biasing of the PV solar field matches that of the internal buses when the transistors of the DC/DC converter switch.

(15) To carry out the transfer of power (energy) from the photovoltaic solar field PV 21 to the internal bus of the batteries 12, for the final transfer to the battery rack 20, it is necessary to know the voltage in the photovoltaic solar field PV 21 and the voltage in the battery rack 20. If the voltage in the battery rack 20 is less than the voltage in the photovoltaic solar field PV 21 (V.sub.BSS<V.sub.PV), the dual DC/DC converter 10 will function as a buck converter 31A where the sixth transistor 6B and the seventh transistor 7B will open, the fifth transistor 5B and the eighth transistor 8B will close, and all transistors will switch (the first transistor 1B, the second transistor 2B, the third transistor 3B, and the fourth transistor 4B) on the photovoltaic solar field PV side, generating a higher voltage at the terminals of inductance 1L than on the battery side to be charged to cause the flow of power.

(16) However, if the voltage in the battery rack 20 is higher than the voltage in the photovoltaic solar field PV 21 (V.sub.BSS>V.sub.PV), the dual DC/DC converter 10 will function as a boost converter 31B. The type of switching of the transistors for the boost case will be the opposite of that explained for the buck case, where the second transistor 2B and the third transistor 3B will open, the first transistor 1B and the fourth transistor 4B will close, and all the transistors on the battery side will switch (the fifth transistor 5B, the sixth transistor 6B, the seventh transistor 7B and the eighth transistor 8B).

(17) Once the active pre-charging makes the internal voltage (the voltage of the internal buses of batteries 12 and PV 11) of the DC/DC dual 10 in differential mode with respect to ground equal to the voltage value that the battery rack 20 has in differential mode (equidistant from ground), the next step of the method is to isolate (FIG. 4, 32) the internal bus on the battery side 12 from the internal bus on the photovoltaic solar field PV side 11 until the internal bus on the battery side 12 is biased the same as the battery rack 20. That is, to isolate the internal bus on the battery side 12 so that the internal bus on the battery side 12 naturally has the same voltage both in differential mode and with respect to ground (GND). In order to isolate the internal bus on the battery side 12, the method comprises leaving the transistors 1B, 2B, 3B and 4B of the internal bus on the photovoltaic solar field side 11 open. Continuing with the previous example, the internal bus on the battery side 12 would have a voltage of 1000 v in differential mode with respect to ground (1000 v-0 v) before isolating the internal bus itself on the battery side 12. By isolating the internal bus on the battery side 12, the internal bus on the battery side 12 naturally maintains the voltage of 1000V in differential mode but modifies its voltage in common mode or with respect to ground (500 v on GND and +500 v on GND). Taking into account that the differential mode voltage V.sub.DIFF is defined as V.sub.DIFF=V.sub.2V.sub.1; and common mode voltage V.sub.MC is defined as V.sub.MC=(V.sub.2+V.sub.1)/2, the V.sub.DIFF is held at 1000 v, but the common mode voltage V.sub.MC goes from 500 v (=(10000)/2) to 0 v (=(+500+(500))/2).

(18) Next, the method comprises connecting (FIG. 4, 33) the internal bus on the battery side 12 with the battery rack 20. Since the internal bus on the battery side 12 has the same voltage and the same biasing as the battery rack 12, the biasing transient that occurred in the prior art when connecting the batteries to the internal bus of the capacitors of the dual DC/DC converter does not occur. To connect the dual DC/DC converter 10 of FIG. 3 to the battery rack 12, soft charging is performed by means of closing contactors 25 and resistor 22 as known in the prior art. Subsequently, contactor 26 is closed.

(19) At this point, the internal bus on the battery side 12 will be biased in differential mode equidistant from ground and the internal bus on the photovoltaic solar field side 11 will be biased in differential mode with respect to ground. Continuing with the previous example, the internal bus on the battery side 12 would have a differential voltage of 1000 v, negative pole at 500 v and positive pole at +500 v, and the internal bus on the photovoltaic solar field side 11 would have a differential voltage of 1000 v, positive pole at +1000 v and negative pole at 0 v. This would cause a transient as the converter 10 starts to work normally.

(20) All of the above can be exemplified with the following table:

(21) TABLE-US-00001 TABLE 1 State Description Switching BSS internal voltage BSS voltage Contactors Prior art Off Converter No switching Negative: GND Negative: Vbss/2 Open stopped Midpoint: GND Midpoint: GND Positive: GND Positive: +Vbss/2 Passive Converter No switching With transient: With transient: Closed soft charge stopped Negative: Vbss/2 Negative: Vbss/2 Midpoint: GND Midpoint: GND Positive: +Vbss/2 Positive: +Vbss/2 Present invention Off Converter No switching Negative: GND Negative: Vbss/2 Open stopped Midpoint: GND Midpoint: GND Positive: GND Positive: +Vbss/2 On Converter The following Negative: +Vpv/2 Negative: Vbss/2 Open working transistors Midpoint: +Vpv/2 Midpoint: GND switch in Positive: +Vpv/2 Positive: +Vbss/2 Active soft pairs: Negative: +Vpv/2-Vbss/2 Negative: Vbss/2 Open charge 1B-4B/2B-3B Midpoint: +Vpv/2 Midpoint: GND 5B-8B/6B-7B Positive: +Vpv/2+Vbss/2 Positive: Vbss/2 Standby Converter No switching After the transient: Negative: Vbss/2 Open stopped Negative: Vbss/2 Midpoint: GND Midpoint: GND Positive: +Vbss/2 Positive: +Vbss/2 Passive Converter No switching Negative: Vbss/2 Negative: Vbss/2 Closed soft charge stopped Midpoint: GND Midpoint: GND Positive: +Vbss/2 Positive: +Vbss/2

(22) To avoid the start-up transient, the present invention proposes biasing the battery rack 20 in order to equalize the voltages with respect to ground GND before starting operation (ON). Biasing mainly consists of switching the power transistors in a position that does not generate a transfer of power. To do this, specific transistors are switched with a duty cycle which is as small as possible and progressive, but which progressively equalizes the potentials on both internal sides (11,12) of the dual DC/DC converter.

(23) Before starting the biasing of the battery rack 20, it is necessary to open (FIG. 4-34) the external transistors (1B,4B,5B,8B) of the dual DC/DC converter. Once the external transistors (1B,4B,5B,8B) are open, it is possible to switch (FIG. 4-35) the intermediate transistors (2B,3B,6B,7B) with the lowest possible duty cycle until the duty cycle is equal to 1 (FIG. 4-37) with time increments t (FIG. 4-36). The minimum duty cycle will be that allowed by the transistor itself depending on the technology with which the power transistor is manufactured. As an example, a time between 1-3115 can be taken as a reference with the use of IGBT type transistors. The duty cycle is progressively increased until leaving the transistors 2B,3B,6B,7B closed, at which time the biasing is complete. This causes the voltages on both internal sides (11,12) of the dual DC/DC converter 10 to begin to progressively equalize in a way that, apart from being very low in terms of energy (because the cycle is the minimum possible and is increased slowly), it is attenuated by the implicit low-pass filter of the inductances between both internal sides (11,12) of the dual DC/DC converter 10 (path marked with a dashed line in FIG. 5 where stray capacitances C of the buses are drawn). The time increments t in the duty cycle CT will depend mainly on the implicit low-pass filter of the inductances and the technology of the power transistors (1B-8B) and they must only meet the condition that there is no transfer of energy between both internal sides (11,12) of the dual DC/DC converter 10. As an example, a time between 1-3115 can be taken as a reference for the time increments t with the use of IGBT type transistors.

(24) Below is a comparison between the operation of the dual DC/DC converter according to the prior art and its operation for the biasing of the battery internal side 12, and therefore, of the battery rack 20 when both are connected:

(25) TABLE-US-00002 TABLE 2 State Description Switching PV biasing BSS biasing Prior art OFF Converter stopped No switching Negative: GND Negative: Vbss/2 Midpoint: +Vpv/2 Midpoint: GND Positive: +Vpv Positive: +Vbss/2 ON Converter working The following Negative: GND After the transient: in normal mode transistors switch in Midpoint: +Vpv/2 Negative: +Vpv/2-Vbss/2 pairs: Positive: +Vpv Midpoint: +Vpv/2 1B-4B/2B-3B Positive: +Vpv/2+Vbss/2 5B-8B/6B-7B Present invention OFF Converter stopped No switching Negative: GND Negative: Vbss/2 Midpoint: +Vpv/2 Positive: +Vbss/2 Positive: +Vpv Biasing Converter working The following Negative: GND Smooth transition to: transistors switch Midpoint: +Vpv/2 Negative: +Vpv/2-Vbss/2 synchronously: Positive: +Vpv Midpoint: +Vpv/2 2B-3B/6B-7B Positive: +Vpv/2+Vbss/2 ON Converter working The following Negative: GND Negative: +Vpv/2-Vbss/2 transistors switch in Midpoint: +Vpv/2 Midpoint: +Vpv/2 pairs: Positive: +Vpv Positive: +Vpv/2+Vbss/2 1B-4B/2B-3B 5B-8B/6B-7B

(26) To carry out the intrinsic biasing method for a dual DC/DC converter of the present invention, the dual DC/DC converter comprises control means 28 connected to at least: the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the first closure means, the second closure means. The control means can be selected from among a microcontroller, a microprocessor and an FPGA.