IN-MEMORY COMPUTATION DEVICE HAVING IMPROVED MAPPING OF COMPUTATION WEIGHTS

Abstract

A group of memory cells includes a first cell with a first number of bits, coupled to a first bit line and programmable with a first weight and a second cell with a second number of bits, coupled to a second bit line and programmable with the first weight. An activation circuit applies first and second activation signals to the first and second cells during first and second windows, respectively. The activation signals have respective durations as a function of an input value and, optionally, a number of bits of the first or second cell. A read circuit generates first and second signals indicative of a time integral of current in the first and second bit lines during the first and second windows, respectively, and outputs a digital signal indicative of a sum between the first and second signals, optionally also as a function of number of bits.

Claims

1. An in-memory computation (IMC) device, comprising: a memory array comprising at least one group of memory cells including a first memory cell coupled to a first word line and a first bit line, the first memory cell having a first number of bits and being programmable to have a first electrical quantity as a function of a first computation weight, and a second memory cell coupled to a second word line and a second bit line, the second memory cell having a second number of bits and being programmable to have a second electrical quantity as a function of the first computation weight; an activation circuit configured to provide a first activation signal to the first word line during a first computation window and a second activation signal to the second word line during a second computation window distinct from the first computation window, wherein the first activation signal has a first duration which is a function of a first input value, and wherein the second activation signal has a second duration which is a function of the first input value; wherein the first memory cell is configured to be traversed, during the first computation window, by a first cell current which is a function of the first electrical quantity and the first activation duration and the first bit line is configured to be traversed, during the first computation window, by a first bit line current which is a function of the first cell current; wherein the second memory cell is configured to be traversed, during the second computation window, by a second cell current which is a function of the second electrical quantity and the second activation duration and the second bit line is configured to be traversed, during the second computation window, by a second bit line current which is a function of the second cell current; a read circuit coupled to the first and second bit lines and configured to generate a first integration signal indicative of a time integral of the first bit line current during the first computation window, generate a second integration signal indicative of a time integral of the second bit line current during the second computation window, and provide a digital signal indicative of a sum of the first and the second integration signals; wherein the first activation duration is different from the second activation duration and at least one of the first activation duration and the second activation duration is also a function of at least one of the first number of bits and the second number of bits.

2. The IMC device according to claim 1, wherein the first activation duration is greater than the second activation duration and a ratio between the first activation duration and the second activation duration is a function of the second number of bits.

3. The IMC device according to claim 1, wherein at least one of the first activation duration and the second activation duration is a function of 2.sup.N, wherein N is the second number of bits.

4. The IMC device according to claim 1, wherein a ratio between the first activation duration and the second activation duration is a function of 2.sup.N, wherein N is the second number of bits.

5. The IMC device according to claim 1, wherein the read circuit is further configured to multiply at least one of the first integration signal and the second integration signal of at least one multiplication factor which is a function of at least one of the first number of bits and the second number of bits.

6. The IMC device according to claim 5, wherein the read circuit is configured to multiply the first integration signal by a first multiplication factor and/or the second integration signal by a second multiplication factor, wherein a ratio between the first and the second multiplication factors is a function of the second number of bits and is greater than 1.

7. The IMC device according to claim 5, wherein the at least one multiplication factor is a function of 2.sup.N, wherein N is the second number of bits.

8. The IMC device according to claim 6, wherein the ratio between the first and the second multiplication factors is a function of 2.sup.N, wherein N is the second number of bits.

9. The IMC device according to claim 6, wherein the ratio between the first and the second multiplication factors is a function of the second number of bits.

10. The IMC device according to claim 9, wherein the ratio between the first and the second multiplication factors is a function of 2.sup.N/2, wherein N is the second number of bits.

11. The IMC device according to claim 9, wherein a ratio between the first and the second activation duration is a function of 2.sup.N/2, wherein N is the second number of bits.

12. The IMC device according to claim 1, wherein the first computation window has a duration greater than or equal to the duration of the second computation window.

13. The IMC device according to claim 1, wherein the duration of the first and the duration of the second computation windows are a function of a reference duration set by a user of the IMC device before the start of the first and the second computation windows.

14. The IMC device according to claim 1, wherein the first computation weight has a total number of bits greater than the first and the second number of bits and comprises a group of most significant bits and a group of least significant bits, wherein the first electrical quantity is programmable so as to be a function of the group of most significant bits of the first computation weight, and wherein the second electrical quantity is programmable so as to be a function of the group of least significant bits of the first computation weight.

15. The IMC device according to claim 1, wherein the read circuit comprises an integrator configured to detect a first number of charge packets starting from the first bit line current during the first computation window and update the first integration signal as a function of the first number of charge packets, and configured to detect a second number of charge packets starting from the second bit line current during the second computation window and update the second integration signal as a function of the second number of charge packets.

16. The IMC device according to claim 1, wherein the first and second integration signals are each indicative of a number of charge packets detected starting from the respective bit line current during the respective computation window, the read circuit comprising a counting stage of the ripple-counter type configured to increase the digital signal as a function of the number of charge packets detected both during the first computation window and during the second computation window and as a function of the at least one multiplication factor.

17. An in-memory computation, IMC, device comprising: a memory array including at least one group of memory cells comprising a first memory cell connectable to a first word line and a first bit line, the first memory cell having a first number of bits and being programmable to have a first electrical quantity as a function of a first computation weight, and a second memory cell connectable to a second word line and a second bit line, the second memory cell having a second number of bits and being programmable to have a second electrical quantity as a function of the first computation weight; an activation circuit configured to provide a first activation signal to the first word line during a first computation window and a second activation signal to the second word line during a second computation window distinct from the first computation window, wherein the first activation signal has a first duration which is a function of a first input value, wherein the second activation signal has a second duration which is a function of the first input value, wherein the first memory cell is configured to be traversed, during the first computation window, by a first cell current which is a function of the first electrical quantity and the first activation duration, wherein the second memory cell is configured to be traversed, during the second computation window, by a second cell current which is a function of the second electrical quantity and the second activation duration, wherein the first bit line is configured to be traversed, during the first computation window, by a first bit line current which is a function of the first cell current and wherein the second bit line is configured to be traversed, during the second computation window, by a second bit line current which is a function of the second cell current, the IMC device further comprising a read circuit connectable to the first and the second bit lines and configured to generate a first integration signal indicative of a time integral of the first bit line current during the first computation window, generate a second integration signal indicative of a time integral of the second bit line current during the second computation window, and provide a digital signal indicative of a sum of the first and the second integration signals, wherein the read circuit is further configured to multiply at least one of the first integration signal and the second integration signal of at least one multiplication factor which is a function of at least one of the first number of bits and the second number of bits.

18. The IMC device according to claim 17, wherein the read circuit is configured to multiply the first integration signal by a first multiplication factor and the second integration signal by a second multiplication factor, wherein a ratio between the first and the second multiplication factors is a function of the second number of bits and is greater than 1.

19. The IMC device according to claim 18, wherein the ratio between the first and the second multiplication factors is a function of 2.sup.N, wherein N is the second number of bits.

20. The IMC device according to claim 18, wherein the ratio between the first and the second multiplication factor is a function of 2.sup.N/2, wherein N is the second number of bits.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0028] For a better understanding of the present invention, embodiments thereof are now described, purely by way of non-limiting example, with reference to the attached drawings, wherein:

[0029] FIG. 1 shows a simplified block diagram of a known in-memory computation device;

[0030] FIG. 2 shows a block diagram of an in-memory computation device;

[0031] FIG. 3 shows an enlarged portion of a group of memory cell of the device of FIG. 2;

[0032] FIG. 4 shows a block diagram of a word line activation circuit of the device of FIG. 2;

[0033] FIG. 5 shows a block diagram of a digital detector of the device of FIG. 2;

[0034] FIG. 6 shows exemplary waveforms of a method for performing a MAC operation by the device of FIG. 2;

[0035] FIG. 7 shows exemplary waveforms of a method for performing a MAC operation by the device of FIG. 2;

[0036] FIG. 8 shows exemplary waveforms of a method for performing a MAC operation by the device of FIG. 2;

[0037] FIG. 9 shows an exemplary diagram of a mapping of computation weights obtainable by the device of FIG. 2;

[0038] FIG. 10 shows a circuit diagram of an integrator of the digital detector of the device of FIG. 2;

[0039] FIG. 11 shows a circuit diagram of a counting stage of the digital detector of the device of FIG. 2; and

[0040] FIGS. 12 and 13 show exemplary diagrams of a mapping of computation weights obtainable by the device of FIG. 2.

DETAILED DESCRIPTION

[0041] FIG. 2 shows an in-memory computation device (hereinafter IMC device) 10 comprising a memory array (or matrix) 12, a word line activation unit or circuit 14, and a read unit or circuit 15 comprising herein a plurality of digital detectors 16 and digital signal processors (DSP) 17.

[0042] The memory array 12 comprises a plurality of memory cells 20 organized according to a matrix arrangement having M columns and K rows.

[0043] In particular, in this embodiment, the memory cells 20 are of the non-volatile type.

[0044] The IMC device 10 is configured to perform an in-memory operation, in particular a Multiply and Accumulate (MAC) operation between an input vector (or signal) X having input data x.sub.1, . . . , x.sub.J (in general, with JK and in particular in the embodiment of FIG. 2 with J=K) and a plurality of computation weights G, in order to generate an output vector (or signal) Y having output data y.sub.1, . . . , y.sub.L (in general, with LM and, in particular in the embodiment of FIG. 2, with L=M/2).

[0045] The memory cells 20 arranged in the same column are mutually connected through a respective bit line BL.sub.m, where m=1, . . . , M. The memory cells 20 arranged in the same row are mutually connected through a respective word line WL.sub.j, where j=1, . . . , K.

[0046] In practice, a respective word line WL.sub.j and a respective bit line BL.sub.m are associated with each memory cell 20.

[0047] Therefore, hereinafter, a generic memory cell of the plurality of memory cells 20 is identified by 20.sub.m,j, where the indices m=1, . . . , M and j=1, . . . , K indicate the column and, respectively, the row of the generic memory cell in the memory array 12.

[0048] The memory cells 20 are further organized so as to form a plurality of groups of memory cells, where each group of memory cells is indicated hereinafter by 22.sub.i,j and identified by a dash-dot line in FIG. 2 and in the respective enlarged portion of FIG. 3. Hereinafter, the plurality of groups of memory cells 22.sub.i,j may also be indicated as a whole by the reference number 22.

[0049] Each group of memory cells 22.sub.i,j is configured to store a respective computation weight G.sub.i,j that may be used to perform the MAC operation.

[0050] Each group of memory cells 22.sub.i,j comprises at least a first memory cell and a second memory cell. The first memory cell and the second memory cell may be coupled to a first and a second word line (for example corresponding to a same word line or to two word lines distinct from each other) and to a first and a second bit line.

[0051] In detail, with reference to the enlarged portion of FIG. 3, in this embodiment each group of memory cells 22.sub.i,j comprises a respective Most Significant Cell (MSC) and a respective Least Significant Cell (LSC) that belong to the plurality of memory cells 20.

[0052] In the arrangement of FIGS. 2 and 3, the most significant cell MSC and the least significant cell LSC of each group of cells 22.sub.i,j are coupled to a same word line WL.sub.j and to two adjacent bit lines BL.sub.m-1, BL.sub.m.

[0053] For example, the word line WL.sub.j having the most significant cell MSC and the least significant cell LSC coupled thereto may also be indicated as the first word line.

[0054] In practice, in this embodiment, the plurality of groups of memory cells 22 also forms a matrix having L columns and K rows, where L=M/2.

[0055] In detail, the plurality of groups of memory cells 22 comprises the groups of memory cells 22.sub.i,j, where the indices i=1, . . . , L and j=1, . . . , K indicate the column and, respectively, the row of the generic group of cells 22.sub.i,j.

[0056] A most significant bit line BL.sub.i,MSC (i.e., the bit line having the respective most significant cell MSC coupled thereto) and a least significant bit line BL.sub.i,LSC (i.e., the bit line having the respective least significant cell LSC coupled thereto) are therefore associated with each group of memory cells 22.sub.i,j.

[0057] In the example of FIGS. 2 and 3, the most significant cell MSC of the group of memory cells 22.sub.1,1 corresponds to the memory cell 20.sub.1,1 and is therefore coupled to the bit line BL.sub.1, which hereinafter will also be identified as BL.sub.1,MSC; and the least significant cell LSC of the group of memory cells 22.sub.1,1 corresponds to the memory cell 20.sub.2,1 and is therefore coupled to the bit line BL.sub.2, which hereinafter will also be identified as BL.sub.1,LSC.

[0058] In practice, in the exemplary configuration of FIG. 2, all the memory cells 20.sub.1,1, . . . , 201.sub.iK that are coupled to the bit line BL.sub.1 each form the most significant cell MSC of the respective group of memory cells 22.sub.1,1, . . . , 22.sub.1,K; and all memory cells 20.sub.2,1, . . . , 20.sub.2,K that are coupled to the bit line BL.sub.2 each form the least significant cell LSC of the respective group of memory cells 22.sub.1,1, . . . , 22.sub.1,K.

[0059] Again by way of example, all memory cells 20.sub.M-1,1, . . . , 20.sub.M-1,K that are coupled to the bit line BL.sub.M-1 each form the most significant cell MSC of the respective group of memory cells 22.sub.L,1, . . . , 22.sub.L,K; and all memory cells 20.sub.M,1, . . . , 20.sub.M,K that are coupled to the bit line BL.sub.M each form the least significant cell LSC of the respective group of memory cells 22.sub.L,1, . . . , 22.sub.L,K.

[0060] The memory cells 20 each comprise a storage element 25 and a selection element 26.

[0061] The storage element 25 of each memory cell 20.sub.1,j is a variable resistive element that may be programmed in such a way as to have a specific resistance value (or level).

[0062] In detail, each memory cell 20.sub.1,j is configured to be programmed in one of 2.sup.N resistance levels, where N is the number of bits of the memory cell 20.sub.1,j.

[0063] For simplicity of description, hereinafter it will be considered that all the memory cells have the same number of bits N. However, the memory cells 20 may have a number of bits different from each other.

[0064] Considering a generic group of memory cells 22.sub.i,j, the resistance R.sub.i,MSC of the storage element 25 of the respective most significant cell MSC and the resistance R.sub.i,LSC of the storage element 25 of the respective least significant cell LSC are programmed as a function of the weight G.sub.i,j that is desired to be mapped in the generic group of cells 22.sub.i,j.

[0065] In detail, taking into consideration a 2.sup.N-bit binary representation of a generic computation weight G.sub.i,j, the storage element 25 of the most significant cell MSC of the respective group of memory cells 22; j may be programmed in such a way as to have a resistance level R.sub.i,MSC which is a function of the N most significant bits of the computation weight G.sub.i,j; and the storage element 25 of the least significant cell LSC of the respective group of memory cells 22.sub.i,j may be programmed in such a way as to have a resistance level R.sub.i,LSC which is a function of the N least significant bits of the computation weight G.sub.i,j. However, more generally, the generic computation weight G.sub.i,j may have a binary representation having N.sub.1+N.sub.2 bit, where N.sub.1 may be the number of most significant bits and N.sub.2 the number of least significant bits.

[0066] The resistance levels R.sub.i,MSC, R.sub.i,LSC of each group of memory cell 22.sub.i,j may be associated with respective conductance levels g.sub.i,MSC, g.sub.i,LSC of the MSC and, respectively, LSC cells, where the conductance level is inversely proportional to the respective resistance level. The encoding of a weight on the conductance level may be linear increasing. In other words, the conductance level may be a linear increasing function of the absolute value of the weight.

[0067] In particular, the storage elements 25 of the memory cells 20 may be based on a Phase Change Material (PCM), for example a chalcogenide. In fact, a phase change material may have at least two phase states, for example an amorphous phase and a crystalline phase, each having a respective resistivity.

[0068] A phase change material may be transformed from one phase state to another by heat transfer, for example using current pulses.

[0069] The resistance of each storage element 25 associated with the respective phase state may be used to distinguish two or more logic states of the corresponding memory cell 20.

[0070] For example, the amorphous phase may have a higher resistance with respect to the crystalline phase. A logic state 0, or reset state, may be associated with the amorphous phase of the storage element 25. A logic state 1, or set state, may be associated with the crystalline phase of the storage element 25.

[0071] However, each storage element 25 may also be programmable in a higher number of states or levels.

[0072] The storage element 25 has a first terminal coupled to a node 28 of the respective bit line BL.sub.1 and a second terminal coupled to a reference potential node, here to ground 29, through the selection element 26.

[0073] The selection element 26 is a switch, for example a BJT transistor, a diode or a MOS transistor, here an NMOS transistor, which is arranged in series with the respective storage element 25 and whose switching is controlled by an activation signal generated by the row activation circuit 14 and provided to the respective word line WL.sub.j.

[0074] In this embodiment, the NMOS transistor forming the selection element 26 has a source coupled, here directly connected, to ground 29; a drain coupled, here directly connected, to the second terminal of the storage element 25; and a gate coupled, here directly connected, to the respective word line WL.sub.j.

[0075] In practice, the storage element 25 and the selection element 26 form a current path of the respective memory cell 20.sub.1,j; where the selection element 26, in response to receiving the respective activation signal, closes the respective current path, thereby allowing a cell current i.sub.cell to flow from the common node 28 to the ground 29.

[0076] The word line activation unit 14 receives the input vector X including the plurality of input values x.sub.1, . . . , x.sub.K, for example one for each word line WL.sub.j, and provides a plurality of activation signals 21, for example at least one for each word line WL.sub.1, . . . , WL.sub.K.

[0077] The activation signals 21 are configured to each activate the memory cells 20 coupled to a respective word line WL.sub.j, for a duration which is a function of at least the respective input datum x.sub.j.

[0078] In detail, the activation signals 21 may be pulses, in particular here rectangular pulses, each having a duration which is a function of at least the respective input value x.sub.j.

[0079] In fact, a time duration of value T(x.sub.j) which is a function of the respective input value x.sub.j may be associated with each input value x.sub.j. In particular, the time duration of value T(x.sub.j) may be proportional to the respective input value x.sub.j, in particular proportional to the absolute value and/or sign of the input value x.sub.j.

[0080] Optionally, depending on the specific embodiment, the duration of each activation signal 21 may be a function of the respective input datum x.sub.j and also of one or more control data, as discussed in detail below.

[0081] In detail, for performing a MAC operation, the word line activation unit 14 provides a plurality of most significant activation signals S.sub.1,MSC, . . . , S.sub.K,MSC, one to each word line WL.sub.j, during a most significant computation window CW.sub.1; and a plurality of least significant activation signals S.sub.1,LSC, . . . , S.sub.K,LSC, one to each word line WL.sub.j, during a least significant computation window CW.sub.2.

[0082] Without any loss of generality, the most significant activation signals and the least significant activation signals may also be referred to as the first and second activation signals; and the most significant computation window CW.sub.1 and the least significant computation window CW.sub.2 may also be referred to as the first and second computation windows.

[0083] The most significant computation window CW.sub.1 and the least significant computation window CW.sub.2 are distinct from each other (i.e., temporally separated from each other and in particular they are successive to each other) as shown in detail below in reference to FIGS. 6-8. However, the order of the windows CW.sub.1, CW.sub.2 may be different from that shown.

[0084] The IMC device 10 may modulate the durations of the computation windows CW.sub.1, CW.sub.2, as described in detail below, starting from a reference duration T.sub.R.

[0085] The reference duration T.sub.R may be, for example, of the order of a few hundred nanoseconds, or even lower than about 100 ns, and may be chosen by a user of the IMC device before the start of a new computation (i.e., before the start of the computation windows CW.sub.1, CW.sub.2).

[0086] FIG. 4 shows a detailed and exemplary embodiment of the word line activation unit 14.

[0087] The word line activation unit 14 comprises a timer (or main counter) 45 providing a timer signal TM, and a plurality of input-to-time converters 46, one for each word line WL.sub.1, . . . , WL.sub.N.

[0088] The timer signal TM may be configured to adjust the durations of the computation windows CW.sub.1, CW.sub.2.

[0089] The input-to-time converters 46 each provide the activation signals S.sub.j,MSC, S.sub.j,LSC to the respective word line WL.sub.j starting from the timer signal TM and the respective input datum x.sub.j.

[0090] The word line activation unit 14 may also receive an address signal ADR indicating which word lines WL.sub.j to activate in order to perform an in-memory calculation, for example in case only some of the word lines are to be used for the computation.

[0091] The word line activation unit 14 may also receive one or more control signals CTL, for example from a control unit 31 of the IMC device 10 or of the apparatus wherein the IMC device 10 is integrated.

[0092] The control signals CTL may, for example, indicate the current computation window (CW.sub.1 or CW.sub.2), the start of the computation windows CW.sub.1, CW.sub.2 and/or which of the two computation windows CW.sub.1, CW.sub.2 to perform first.

[0093] The read circuit 15 is coupled to the bit lines BL.sub.1, . . . , BL.sub.M, samples the bit line currents I.sub.BL,1, . . . , I.sub.BL,M that flow through the bit lines BL.sub.1, . . . , BL.sub.M and, in response, provides the output signal Y=y.sub.1, . . . , y.sub.L.

[0094] In detail, the read circuit 15 comprises a respective digital detector 16; and a respective DSP 17; for each output datum y.sub.i, with i=1, . . . , L.

[0095] Each digital detector 16; is coupled to the bit lines of the groups of memory cells 22.sub.i,1 to 22.sub.i, K.

[0096] For example, with reference to the arrangement of FIG. 2, the digital detector 161 is coupled to the bit lines BL.sub.1 and BL.sub.2 and the digital detector 16L is coupled to the bit lines BL.sub.M-1 and BL.sub.M.

[0097] Each digital detector 16; is an analog-to-digital converter (ADC) that generates a respective charge signal q.sub.i indicative of the amount of charge that has flowed in the respective bit lines BL.sub.i,MSC and BL.sub.i,LSC during the computation windows CW.sub.1, CW.sub.2.

[0098] As discussed in detail below, the charge signal q.sub.i is indicative of the MAC operation between the input data x.sub.1, . . . , x.sub.K and the computation weights G.sub.i1, . . . , G.sub.ik.

[0099] In practice, the charge signal q.sub.i is a digital signal obtained starting from the discretization of the bit line currents that have flowed in the respective bit lines BL.sub.i,MSC and BL.sub.i,LSC during the computation windows CW.sub.1, CW.sub.2.

[0100] For example, each charge signal q.sub.i may have a number of bits equal to F that may vary depending on the specific application; for example, the number F of bits may depend on the number of bits of the MSC and LSC cells, on the number of memory cells coupled to the bit line BL.sub.i, on the desired calculation accuracy, etc. For example, in case the number of bits of the MSC and LSC cells is N, F may be equal to 2N.

[0101] Each DSP 17; is coupled to the respective digital detector 16i, processes the respective charge signal q.sub.i and, in response, provides the respective output datum y.sub.i.

[0102] For example, the DSP 17; may provide the respective output datum y.sub.i in response to the comparison of the respective charge signal q.sub.i with one or more specific reference values, for example defined during the design or calibration step of the IMC device 10. Additionally, or alternatively, the DSP 17; may perform other processing steps useful for a successive processing of the same output signal y.sub.i, for example depending on the specific device to which the output signal y.sub.i is provided.

[0103] The digital detectors 16 may receive the one or more control signals CTL.

[0104] In detail, as shown in the embodiment of FIG. 5, each digital detector 16; comprises a selection circuit 50 that selects one of the respective bit lines BL.sub.i,MSC and BL.sub.i,LSC depending on the current computation window (CW.sub.1 or CW.sub.2); and an integrator 52 that provides a signal Q.sub.i,MSC indicative of the most significant charge (also indicated hereinafter for simplicity by Q.sub.i,MSC) measured starting from the current that flows in the bit line BL.sub.i,MSC and a signal Q.sub.i,LSC indicative of the least significant charge (also indicated for simplicity by Q.sub.i,LSC) measured starting from the current that flows in the bit line BL.sub.i,LSC.

[0105] The signals Q.sub.i,MSC, Q.sub.i,LSC may be discrete (digital) signals obtained starting from the sampling of the respective currents during the computation window CW.sub.1 and, respectively, CW.sub.2.

[0106] For example, the signals Q.sub.i,MSC, Q.sub.i,LSC may be binary-coded digital signals.

[0107] For example, the signals Q.sub.i,MSC, Q.sub.i,LSC may be digital signals each having 2N bits.

[0108] Optionally, for example depending on the specific embodiment, a multiplier 56 may multiply the signals Q.sub.i,MSC, Q.sub.i,LSC, as described in detail below.

[0109] An adder 58 adds the signals Q.sub.i,MSC, Q.sub.i,LSC and provides the charge signal q.sub.i.

[0110] The IMC device 10 may further comprise interface circuits 30 (FIG. 2) including row decoding and selection circuits, column decoding and selection circuits, and read-write circuits useful for the operation of the IMC device 10 and known per se. For example, the read-write circuits may be used to program the conductance value of the memory cells 20.

[0111] FIG. 6 shows an exemplary diagram of a computation method of a MAC operation by the IMC device 10, according to one embodiment.

[0112] In FIG. 6, the IMC device 10 provides the most significant activation signals S.sub.1,MSC, S.sub.K,MSC and processes the most significant bit lines BL.sub.i,MSC in the most significant computation window CW.sub.1, and provides the least significant activation signals S.sub.1,LSC, . . . , S.sub.K,LSC and processes the least significant bit lines BL.sub.1,LSC in the least significant computation window CW.sub.2.

[0113] In the embodiment of FIG. 6, the word line activation unit 14 defines the duration TC.sub.2 of the computation window CW.sub.2 in such a way that it is equal to the reference duration T.sub.R (i.e., TC.sub.2=T.sub.R); and the duration TC.sub.1 of the processing window CW.sub.1 in such a way to be a function of the number of bits N of the memory cells 20 and of the reference duration T.sub.R, in particular a function of the product between the number of levels 2.sup.N and the reference duration T.sub.R.

[0114] In the embodiment shown, the duration TC.sub.1 is proportional to the product 2.sup.N.Math.T.sub.R, in particular TC.sub.1=T.sub.R.Math.2.sup.N.

[0115] With reference to a generic word line WL.sub.j, within the computation window CW.sub.1 (which extends for example between the instants t.sub.1 and t.sub.2 of FIG. 6), the row activation unit 14 provides the respective most significant activation signal S.sub.j,MSC to the respective word line WL.sub.j. The most significant activation signal S.sub.j,MSC has an activation duration T.sub.j,MSC which is a function of the respective duration of value T(x.sub.j) and the number of bits N of the memory cells 20.

[0116] In particular, the function that associates the activation duration T.sub.j,MSC with the duration of value T(x.sub.j) and number of bits N may be the same function that associates the processing duration TC.sub.1 with respect to the reference duration T.sub.R and the number of bits N.

[0117] In the embodiment shown, T.sub.j,MSC=T(x.sub.j).Math.2.sup.N. Purely by way of example, if T(x.sub.j)=128 ns and N=2, then T.sub.j,MSC=128 ns.Math.4=512 ns.

[0118] Still with reference to the generic word line WL.sub.j, within the computation window CW.sub.2 (which extends, for example, between the instants t.sub.3 and t.sub.4 of FIG. 6), the row activation unit 14 provides the respective least significant activation signal S.sub.j,LSC to the respective word line WL.sub.j.

[0119] The least significant activation signal S.sub.j,LSC has a duration equal to the duration of value T(x.sub.j).

[0120] In practice, in the embodiment of FIG. 6, the most significant activation duration T.sub.j,MSC is greater than the respective least significant activation duration T.sub.j,LSC and the ratio T.sub.j,MSC/T.sub.j,LSC is a function of the number N of bits of the least significant cell LSC, in particular equal to 2N.

[0121] During the computation window CW.sub.1, each digital detector 16; processes (interval 60 of FIG. 6) the respective most significant bit line BL.sub.i,MSC.

[0122] For example, with reference to the configuration shown, the digital detector 161 processes the bit line BL.sub.1.

[0123] In detail, during the first computation window CW.sub.1, each most significant cell MSC is traversed by a current I.sub.MSC having a magnitude (i.e., absolute value) that depends on the resistance level R.sub.MSC programmed in the most significant cell MSC and a duration that depends on, in particular is equal to, the activation duration T.sub.j,MSC of the respective activation signal S.sub.j,MSC.

[0124] The most significant cell MSC of the group of memory cells 22.sub.i,j therefore contributes during the processing window CW.sub.1 to a charge shift Q.sub.i,j,MSC which is a function of the product between the activation duration T.sub.j,MSC and the respective conductance level g.sub.i,MSC.

[0125] Thus, overall, each most significant bit line BL.sub.i,MSC (e.g., the bit line BL.sub.1 in the configuration of FIG. 2) contributes to an overall charge shift Q.sub.i,MSC that depends on the sum of all charge contributions Q.sub.i,j,MSC

[00003]$\left(i.e.,{.Math.}_{j=1}^K{Q}_{i,j,\mathrm{MSC}}\right).$

[0126] With reference to FIG. 5, during the computation window CW.sub.1, the selection circuit 50 of the digital detector 16; selects the most significant bit line BL.sub.i,MSC, in such a way that the integrator 52 integrates the respective current I.sub.BLi,MSC and then generates in response the most significant charge signal Q.sub.i,MSC.

[0127] During the computation window CW.sub.2, each digital detector 16; processes (interval 61 of FIG. 6) the respective least significant bit line BL.sub.i,LSC.

[0128] For example, with reference to the configuration shown, the digital detector 161 processes the bit line BL.sub.2.

[0129] In detail, during the computation window CW.sub.2, each least significant cell LSC is traversed by a current I.sub.LSC having a magnitude (i.e., absolute value) that depends on the resistance level R.sub.LSC programmed in the least significant cell LSC and a duration that depends on, in particular is equal to, the activation duration T.sub.j,LSC of the respective activation signal S.sub.j,LSC.

[0130] The least significant cell LSC of the group of memory cells 22.sub.i,j therefore contributes during the computation window CW.sub.2 to a charge shift Q.sub.i,j,LSC which is a function of the product between the activation duration T.sub.j,LSC and the respective conductance level g.sub.i,LSC.

[0131] Thus, overall, each least significant bit line BL.sub.i,LSC (e.g., the bit line BL.sub.2 in the configuration of FIG. 2) contributes to an overall charge shift Q.sub.i,LSC that depends on the sum of all charge contributions Q.sub.i,j,LSC

[00004]$\left(i.e.,{.Math.}_{j=1}^K{Q}_{i,j,\mathrm{LSC}}\right).$

[0132] With reference to FIG. 5, during the computation window CW.sub.2, the selection circuit 50 of the digital detector 16; selects the least significant bit line BL.sub.i,LSC, in such a way that the integrator 52 integrates the respective current I.sub.BLi,LSC and then generates in response the least significant charge signal Q.sub.i,LSC.

[0133] In this embodiment, the most significant charge Q.sub.i,MSC and the least significant charge Q.sub.i,LSC are not subject to multiplication by the multiplier 56.

[0134] The adder 58 adds the most significant charge signal Q.sub.i,MSC and the least significant charge signal Q.sub.i,LSC, thus generating in response the charge signal q.sub.i.

[0135] The fact that both durations T.sub.j,MSC and T.sub.j,LSC are both a function of the respective input value x.sub.j but different from each other as a function of the number of bits N allows to assign a different significance to the charge contributions Q.sub.i,MSC and Q.sub.i,LSC.

[0136] In particular, the fact that the ratio between the durations T.sub.j,MSC and T.sub.j,LSC is greater than 1 and a function of 2.sup.N allows to assign to the charge contribution Q.sub.i,MSC of the most significant cells MSC a greater weight than the charge contribution Q.sub.i,LSC of the least significant cells LSC.

[0137] Since the charge contributions Q.sub.i,MSC, Q.sub.i,LSC, also depend on the resistance levels R.sub.i,MSC and, respectively, R.sub.i,LSC of each group of memory cells 22ij, the MSC, LSC cells may be used to map different groups of bits of the computation weight G.sub.i,j.

[0138] In other words, this allows to obtain a multiplication by 2N of the contribution associated with the most significant bits and add it to the contribution associated with the least significant part.

[0139] In practice, this allows to use the group of memory cells 22.sub.i,j, formed by two cells (MSC, LSC) each having a number N of bits, to map a computation weight G.sub.i,j having a number 2.sup.N of bits. In general, if the two cells MSC and LSC have respectively a number of bits N.sub.MSC and N.sub.LSC, a computation weight G.sub.i,j having a number N.sub.MSC+N.sub.LSC of bits may be mapped.

[0140] Therefore, the IMC device 10 has a high efficiency in mapping computation weights G having a high number of bits in the memory array 12.

[0141] The IMC device 10 may therefore have a high weight-mapping density in the array 12.

[0142] Furthermore, in the embodiment of FIG. 6, the fact that the duration TC.sub.2 of the computation window CW.sub.2 is equal to the reference duration T.sub.R may allow the word line activation circuit 14 to provide the least significant activation signal S.sub.j,MSC with high accuracy.

[0143] FIG. 7 shows an exemplary diagram of a computation method of a MAC operation by the IMC device 10.

[0144] Also in FIG. 7, the IMC device 10 provides the most significant activation signals S.sub.1,MSC, . . . , S.sub.K,MSC and processes the most significant bit lines BL.sub.i,MSC in the computation window CW.sub.1, and provides the least significant activation signals S.sub.1,LSC, . . . , S.sub.K,LSC and processes the least significant bit lines BL.sub.i,LSC in the computation window CW.sub.2.

[0145] In the embodiment of FIG. 7, the computation windows CW.sub.1, CW.sub.2 have a same processing duration TC.sub.3.

[0146] In particular, the processing duration TC.sub.3 may be equal to the reference duration T.sub.R, i.e. TC.sub.3=T.sub.R.

[0147] Furthermore, in this embodiment, with reference to a generic word line WL.sub.j, the most significant activation signal S.sub.j,MSC and the least significant activation signal S.sub.j,LSC have a same duration which is a function only of the respective duration of value T(x.sub.j), in particular T.sub.j, MSC=T.sub.j,LSC=T(x.sub.j). Purely by way of example, it may be T.sub.j,MSC=T.sub.j,LSC=T(x.sub.j)=128 ns.

[0148] During the computation window CW.sub.1, each digital detector 16; processes (step 60) the respective most significant bit line BL.sub.i,MSC and, during the computation window CW.sub.2, each digital detector 16; processes (step 61) the respective least significant bit line BL.sub.i,MSC, similarly to what has been discussed for the embodiment of FIG. 6.

[0149] In this embodiment, the processing also comprises a step 63 of multiplying one or more of the signals Q.sub.i,MSC, Q.sub.i,LSC.

[0150] In particular, the most significant charge signal Q.sub.i,MSC indicative of the charge measured during the computation window CW.sub.1 is multiplied, by the multiplier 56, by a multiplication factor P.sub.MSC which is a function of the number of bits N of the least significant cell LSC of the group of memory cells 22.sub.i,j.

[0151] In detail, the multiplication factor P.sub.MSC may be proportional to the total number of levels 2.sup.N at which the least significant cell LSC may be programmed. In particular, in this embodiment, P.sub.MSC=2N.

[0152] The least significant charge signal Q.sub.i,LSC indicative of the charge measured during the computation window CW.sub.2 may be multiplied, by the multiplier 56, by a multiplication factor P.sub.LSC that may be a function of the number of bits N of the least significant cell LSC of the group of memory cells 22.sub.i,j. In particular, in this embodiment, P.sub.LSC=1 (i.e., the least significant charge signal Q.sub.i,LSC does not undergo any multiplication).

[0153] The charge signal q.sub.i provided by the adder 58 is therefore given, in this embodiment, by 2.sup.N.Math.Q.sub.i,MSC+Q.sub.i,LSC.

[0154] The fact that the most significant charge signal Q.sub.i,MSC is multiplied by a different factor with respect to the least significant charge signal Q.sub.i,LSC allows to assign a different significance to the charge contributions Q.sub.i,MSC and Q.sub.i,LSC.

[0155] In particular, the fact that the ratio P.sub.MSC/P.sub.LSC is a function of 2.sup.N allows to assign to the charge contribution Q.sub.i,MSC of the most significant cells MSC a greater significance with respect to the charge contribution Q.sub.i,LSC of the least significant cells LSC.

[0156] Since the charge contributions Q.sub.i,MSC, Q.sub.i,LSC also depend on the resistance levels R.sub.i,MSC and, respectively, R.sub.i,LSC of each group of memory cells 22ij, the MSC, LSC cells may be used to map different groups of bits of the computation weight G.sub.i,j.

[0157] In practice, this allows to use the group of memory cells 22.sub.i,j, formed by two cells (MSC, LSC) each having a number N of bits, to map a computation weight G.sub.i,j having a number 2.sup.N of bits.

[0158] The method described with reference to FIG. 7 allows to maintain the activation times of the memory cells low and therefore to reduce the overall computation time (i.e., the overall duration given by the sum of the computation windows CW.sub.1 and CW.sub.2) with respect to the method described with reference to FIG. 6.

[0159] FIG. 8 shows an exemplary diagram of a method for performing a MAC operation by the IMC device 10.

[0160] In this embodiment, the computation window CW.sub.1, wherein the most significant cells MSC are activated, has a duration TC.sub.4 equal to the reference duration T.sub.R, and the computation window CW.sub.2, wherein the least significant cells LSC are activated, has a duration TC.sub.5 lower than the reference duration T.sub.R.

[0161] In detail, the duration TC.sub.5 of the second computation window CW.sub.2 is equal to the reference duration T.sub.R reduced by a reduction factor which is a function of the number of bits N of the least significant cells LSC, in particular a function of the respective number of resistance levels 2.sup.N.

[0162] In the embodiment shown, the reduction factor is equal to 2.sup.N/2.

[0163] Consequently, the duration T.sub.j,MSC of the most significant activation signal S.sub.j,MSC is equal to the duration of value T(x.sub.j) and the duration T.sub.j,LSC of the least significant activation signal S.sub.j,LSC is equal to the duration of value T(x.sub.j) decreased by the reduction factor, in particular 2.sup.N/2.

[0164] Purely by way of example, if T.sub.j,MSC=T(x.sub.j)=128 ns and N=4, then T.sub.j,LSC=128 ns/4=32 ns.

[0165] Similarly to what has been described for the embodiment of FIG. 7, also in this embodiment the processing also comprises a step, here indicated by 65, of multiplying one or more of the signals Q.sub.i,MSC, Q.sub.i,LSC.

[0166] In detail, the most significant charge signal Q.sub.i,MSC is multiplied by a multiplication factor P.sub.MSC which is a function of the number of bits N of the respective least significant cell LSC.

[0167] In particular, the multiplication factor P.sub.MSC may be equal to the reduction factor 2.sup.N/2, i.e. 2.sup.N/2.Math.Q.sub.i,MSC. Purely by way of example, if N=4, then P.sub.MSC=4.

[0168] Also in this embodiment, P.sub.LSC=1.

[0169] Therefore it is clear that, similarly to what has been described in reference to the embodiments of FIGS. 6 and 7, in the embodiment of FIG. 8 the different significance between the most significant charge signal Q.sub.i,MSC and the least significant charge signal Q.sub.i,LSC is obtained both through a different duration between the signals S.sub.j,MSC and S.sub.j,LSC, and through a different multiplication factor P.sub.MSC, P.sub.LSC of the signals Q.sub.i,MSC, Q.sub.i,LSC.

[0170] Therefore, also according to what has been described in reference to FIG. 8, the group of memory cells 22.sub.i,j, formed by two cells (MSC, LSC) each having a number N of bits may be used, to map a computation weight G.sub.i,j having a number 2.sup.N of bits; thus obtaining a high efficiency.

[0171] Furthermore, according to the embodiment of FIG. 8, a high versatility in mapping the computation weights G.sub.i,j may be obtained.

[0172] In practice, as shown in the schematic representation of FIG. 9, the methods described in reference to FIGS. 6-8 allow to map in each group of memory cells 22.sub.i,j, using two memory cells (MSC and LSC) each having N bits, a respective computation weight G.sub.i,j having a number of bits equal to 2N, i.e. equal to the sum of the number of bits of the most significant cell MSC and the least significant cell LSC.

[0173] In other words, for each group of memory cells 22.sub.i,j, the described methods allow, during the computation, to assign to the resistance value or level stored in the respective most significant cell MSC a greater significance with respect to the resistance value or level stored in the respective least significant cell LSC.

[0174] According to one embodiment, each digital detector 16; may be configured to generate the signals Q.sub.i,MSC, Q.sub.i,LSC by converting the current that flows in the bit lines BL.sub.i,MSC and BL.sub.i,LSC during the respective computation windows CW.sub.1, CW.sub.2 into a number of charge packets and counting the number of charge packets.

[0175] In detail, the digital detector 16; may perform a number of successive sampling iterations of the current that flows in the respective bit line. In each sampling iteration, the digital detector 16; may: generate an integral signal (e.g., a voltage) indicative of the time integral of the bit line current; compare the integral signal with a threshold and; in response to the integral signal reaching the threshold, reset the first integral signal and update the charge signal Q.sub.i,MSC, Q.sub.i,LSC.

[0176] In particular, each digital detector 16; may be the same as the digital detectors 22, 322, or 422 of United States Patent Application Publication No. 2024/0212751 (corresponding to European patent application No. 23216192.7) incorporated herein by reference.

[0177] For example, the integrator 52 may be the same as one of the integration stages described in above-mentioned patent applications; for example, it may be the same as the integration stage 33 described with reference to FIGS. 2-4, the integration stage 330 of FIG. 12, or the integration stage 430 of FIG. 14 of the above-mentioned patent applications.

[0178] With reference to FIG. 10, one embodiment of the integrator, here indicated by 105, of any of the digital detectors 16; is briefly described hereinbelow, in a case wherein the integrator is the same as the integration stage 33 described in above-mentioned patent applications. The integrator 105 may comprise a first integration circuit 121, a second integration circuit 122 and a switching circuit 123 coupled between the first and the second integration circuits 121, 122.

[0179] The first and the second integration circuits 121, 122 are coupled to an input node 116 from which it receives a current indicative of the bit line current, for example k.Math.I.sub.BL,1.

[0180] The first integration circuit 121 comprises a first inverter 124 having an output 125, a capacitor 127 of capacitance CA coupled to the output 125 of the first inverter 124, and a second inverter 128 whose input is coupled to the output 125 of the first inverter 124.

[0181] The first inverter 124 has a supply node coupled to the input node 116 of the integrator 105 and receives at input a first control signal IN.sub.A.

[0182] In practice, the first inverter 124 is biased by the current k.Math.I.sub.BL,1.

[0183] The capacitor 127 has a first terminal coupled to the output node 125 of the first inverter 124 and a second terminal coupled to a reference node, here to ground.

[0184] The output node 125 of the first inverter 124 is at a first integration voltage V.sub.A that drops across the capacitor 127.

[0185] The second inverter 128 has a first sampling threshold, hereinafter referred to as the first threshold V.sub.th1, receives at input the first integration voltage V.sub.A and provides at output a first switch signal S1 as a function of the first threshold V.sub.th1 and the first integration voltage V.sub.A.

[0186] In detail, the first switch signal S1 is a logic signal having a high logic value when the first integration voltage V.sub.A is lower than the first threshold V.sub.th1, and a low logic value when the first integration voltage V.sub.A is higher than the first threshold V.sub.th1.

[0187] The second integration circuit 122 comprises a first inverter 130 having an output 131, a capacitor 132 of capacitance CB coupled to the output 131 of the first inverter 130, and a second inverter 133 whose input is coupled to the output 131 of the first inverter 130.

[0188] The first inverter 130 has a supply node coupled to the input node 116 and receives at input a second control signal IN.sub.B.

[0189] In practice, the first inverter 130 is biased by the current k.Math.I.sub.BL,1.

[0190] The capacitor 132 has a first terminal coupled to the output node 131 of the first inverter 130 and a second terminal coupled to a reference node, here to ground.

[0191] The output node 131 of the first inverter 130 is at a second integration voltage V.sub.B that drops across the capacitor 131.

[0192] The second inverter 133 has a second sampling threshold V.sub.th2, hereinafter referred to as the second threshold V.sub.th2, receives at input the second integration voltage V.sub.B and provides at output a second switch signal S2 as a function of the second threshold V.sub.th2 and the second integration voltage V.sub.B.

[0193] In detail, the second switch signal S2 is a logic signal having a high logic value when the second integration voltage V.sub.B is lower than the second threshold V.sub.th2, and a low logic value when the second integration voltage V.sub.B is higher than the second threshold V.sub.th2.

[0194] The switching circuit 123 is a latch formed by two inverters 135, 136 arranged in a ring configuration, a first switch 137 controlled by the first switch signal S1 and a second switch 138 controlled by the second switch signal S2.

[0195] The switching circuit 123 has a first node 140 coupled to the input of the inverter 136 and the output of the inverter 135, and a second node 141 coupled to the output of the inverter 136 and the input of the inverter 135.

[0196] The first node 140 provides the first control signal IN.sub.A. The second node 141 provides the second control signal IN.sub.B.

[0197] The first switch 137 is coupled between the first node 140 and a node at a voltage V.sub.DD, the second switch 138 is coupled between the second node 141 and the node at the voltage V.sub.DD.

[0198] In this embodiment, the switching circuit 123 also receives an enable signal EN, which controls the activation of the switching circuit 123. For example, the enable signal EN may be used to maintain the switching circuit 123 off when not in use, thereby allowing for energy consumption to be optimized. Furthermore, the enable signal EN may be used to set the switching circuit 123 to a defined state, such as when the IMC device 10 is powered up.

[0199] In practice, the control signal IN.sub.A at node 140 indicates the integration voltage V.sub.A reaching the threshold V.sub.th,1 and, therefore, each switching of the control signal IN.sub.A is indicative of a new charge packet to be counted.

[0200] The integrator 105 may also comprise a counting inverter 145 whose input is coupled to the node 140. In practice, the counting inverter 145 provides a packet counting signal CLK_N, having a value opposite to the control signal IN.sub.A. Therefore, the packet counting signal CLK_N is also indicative of the new charge packet to be counted.

[0201] When the digital detector 16; comprises the integrator 105, the digital detector 16; may also comprise a counter configured to update the number of charge packets counted (and therefore the value of the charge signal Q.sub.i,MSC or Q.sub.i,LSC) as a function of the packet counting signal CLK_N.

[0202] According to one embodiment, each digital detector 16; may comprise a counting stage 111 configured to count the charge packets detected by the integrator 105 and comprising the multiplier 56 and the adder 58, as indicated by a dashed rectangle in FIG. 5.

[0203] In detail, FIG. 11 shows a detailed embodiment of the counting stage 111.

[0204] The counting stage 111 is implemented through a ripple counter-type circuit, in particular with D-type flip-flops.

[0205] The counting stage 111 is coupled to the integrator 52, 105 and receives from the integrator 52, 105 a signal indicative of the charge packets measured by the integrator 52.

[0206] For example, with reference to the embodiment of the integrator 105 of FIG. 10, the counting stage 111 may receive the packet counting signal CLK_N.

[0207] Hereinafter, for simplicity and without any loss of generality, the signal received by the counting stage 111 by the integrator 52 will be indicated by CLK_N.

[0208] The counting stage 111 may comprise a number F of flip-flops 147.1, . . . , 147.F and a number GF of multiplication selectors 150, . . . , 150.G, where F is the number of bits of the charge signal q.sub.i.

[0209] In practice, each flip-flop 147.1, . . . , 147.F provides a respective bit q<1>, . . . , q<F> of the charge signal q.sub.i.

[0210] In the embodiment shown, the multiplication selectors 150.1, . . . , 150.G are each arranged upstream of a respective flip-flop 147.1, . . . , 147.G (i.e., a multiplication selector for each of the first G flip-flops). However, the counting stage 111 may comprise a different number of multiplication selectors, depending on the multiplication factors that are intended to be used.

[0211] The flip-flops 147.1, . . . , 147.F each have a clock input (CK-input), a data input (D-input), a reset input (R-input), a Q-output (or first output) and a Q-output (or second output).

[0212] The first multiplication selector 150.1 has a first selectable input from which it receives the packet counting signal CLK_N and a second selectable input from which it receives a reference bit, for example 1 in the example shown.

[0213] The multiplication selectors 150.2, . . . , 150.G each have a first selectable input from which they receive the packet counting signal CLK_N and a second selectable input coupled to the data input D of a respective downstream flip-flop 147.1, . . . , 147.G1.

[0214] The multiplication selectors 150.1, . . . , 150.G are each controlled by one or more control signals, also here identified without any loss of generality by CTL, indicative of the multiplication factor (e.g., P.sub.MSC and/or P.sub.LSC described with reference to FIGS. 7 and 8) that is desired to be applied during the count of the charge packets.

[0215] The R-inputs of the flip-flops 147.1, . . . , 147.F receive a reset signal RESET_N, for example generated by the control unit 31 and configured to reset the flip-flops 147.1, . . . , 147.F when necessary (for example when the IMC device 10 is switched on and, more generally, whenever it is needed to have known starting values stored in the flip-flops 147.1, . . . , 147.F, for example at the beginning of a new computation).

[0216] The CK-inputs of the flip-flops 147.1, . . . , 147.G are connected, in particular directly coupled, each to the output of the respective multiplication selector 150.1, . . . , 150.G upstream. The Q-output of each flip-flop 147.f, with f=1, . . . , G1, is coupled to the input D of the same flip-flop 147.f and to one of the inputs to be selected of the multiplication selector 150.f downstream.

[0217] For example, the Q-output of the flip-flop 147.1 is coupled to one of the inputs to be selected of the multiplication selector 150.2.

[0218] The Q-output of the flip-flops 147.1, . . . , 147.F is each the respective bit q<1>, . . . , q<F> of the charge signal q.sub.i.

[0219] In practice, in response to the detection of each charge packet by the integrator 52, 105 (and therefore to a switching of the packet counting signal CLK_N), the counting stage 111 increases one of the bits of the charge signal q.sub.i, according to the weight that is intended to be assigned to the count of the new charge packet.

[0220] The control signal CTL determines which of the bits of the charge signal q.sub.i to increase, as a function of the desired multiplication factor.

[0221] For example, in case it is not desired to perform a multiplication (or, in other words, the multiplication factor is equal to 1), the control signal CTL controls the first multiplication selector 150.1 in such a way that it provides at output the signal CLK_N only to the flip-flop 147.1.

[0222] In other words, if it is not desired to perform a multiplication, the packet counting signal CLK_N is used to increase the least significant bit q<1> of the charge signal q.sub.i.

[0223] If it is desired to perform a multiplication by a factor of 2, then the control signal CTL controls the multiplication selectors 150.1, . . . , 150.G in such a way that the packet counting signal CLK_N is provided only to the second flip-flop 147.2.

[0224] If it is desired to perform a multiplication by a factor of 4, then the control signal CTL controls the multiplication selectors 150.1, . . . , 150.G in such a way that the packet counting signal CLK_N is provided only to the third flip-flop 147.3.

[0225] In general, if it is desired to perform a multiplication by a factor (P.sub.MSC or P.sub.LSC) equal to 2P, with p=0, . . . , G then the control signal CTL controls the multiplication selectors 150.1, . . . , 150.G in such a way that the packet counting signal CLK_N is provided at input to the p+1-th flip-flop 147.p.

[0226] The counting stage 111 of FIG. 11 may be used both during the first computation window CW.sub.1 and during the second computation window CW.sub.2, without resetting the flip-flops 147.1, . . . , 147.F between the computation window CW.sub.1 and the computation window CW.sub.2.

[0227] Therefore, the counting stage 111 may be used to count the total number of charge packets measured by the integrator 105 during the entire computation interval CW.sub.1+CW.sub.2.

[0228] In practice, the signal q.sub.i provided at output may be indicative of the sum between the charges Q.sub.i,MSC and Q.sub.i,LSC. In other words, the counting stage 111 may be used to also implement the adder 58 of FIG. 5.

[0229] The embodiments described in reference to FIGS. 10 and 11 may contribute, both individually and in combination, to increasing the computation efficiency of the IMC device 10.

[0230] In fact, the integrator 105 allows to perform the integration of the currents of the bit lines BL.sub.i,MSC and BL.sub.i,LSC during the respective computation windows CW.sub.1 and, respectively, CW.sub.2, thus maintaining the overall computation times of the MAC operation low.

[0231] The counting stage 111 allows to provide the signal q.sub.i efficiently, while maintaining the computation times and the energy consumption of the IMC device 10 low.

[0232] Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein without thereby departing from the scope of the present invention, as defined in the attached claims.

[0233] The IMC device 10 may comprise one or more memories and one or more processing units operationally coupled to each other, for example implemented in the control unit 31, configured to store and execute one or more computer programs (software) configured to control the IMC device 10, according to what has been discussed in the present patent application.

[0234] For example, with reference to a generic group of memory cells 22.sub.i,j, the most significant cell MSC may have a number of bits N.sub.MSC different from the number of bits N.sub.LSC of the least significant cell LSC. In this case, as shown schematically in the diagram of FIG. 12, each of the methods described with reference to FIGS. 6-8 may be used to map a computation weight G.sub.i,j having a number of bits equal to N.sub.MSC+N.sub.LSC. In this case, the ratio T.sub.j,MSC/T.sub.j,LSC and/or the ratio P.sub.MSC/P.sub.LSC may be a function of the number of bits N.sub.LSC, in particular equal to 2.sup.N.sup.LSC.

[0235] In particular, it may be T.sub.j,MSC/T.sub.j,LSC.Math.P.sub.MSC/P.sub.LSC=2.sup.NLSC.

[0236] More generally, the ratio T.sub.j,MSC/T.sub.j,LSC and/or the ratio P.sub.MSC/P.sub.LSC may be obtained through one or more multiplication and/or division (i.e., multiplication with a multiplication factor lower than 1) operations, depending on the specific implementation.

[0237] In case the memory cells of a respective group of cells 22.sub.i,j have a different number of bits from each other, then the memory cell having the highest number of bits may be chosen as the most significant cell MSC of the group of cells 22.sub.i,j. Instead, in case the memory cells of the respective group of cells 22.sub.i,j have the same number of bits with each other, then the most significant cell MSC may be chosen randomly among the memory cells of the group of cells 22.sub.i,j.

[0238] For example, as shown schematically in the diagram of FIG. 13, the significance of the MSC cell may be adjusted through a multiplication by a multiplication factor which is a function of a value k and the significance of the LSC cell may be adjusted through a division by a division factor which is a function of a value h, where k+hmax(N.sub.MSC,N.sub.LSC).

[0239] Optionally, one or more of the values mapped by the MSC, LSC cells may also undergo a truncation operation, depending on the specific application.

[0240] For example, the ratio T.sub.j,MSC/T.sub.j,LSC and/or the ratio P.sub.MSC/P.sub.LSC may be a function of one or more of the numbers of bits N.sub.MSC, N.sub.LSC, depending on the specific mapping of the computation weights intended to be implemented.

[0241] For example, the most significant computation window CW.sub.1 may be performed after the least significant computation window CW.sub.2.

[0242] For example, for each group of cells 22.sub.i,j, the most significant cell MSC and the least significant cell LSC may receive the most significant activation signal and the least significant activation signal having the durations discussed above, but be coupled to word lines different from each other.

[0243] For example, for each group of memory cells 22.sub.i,j, the most significant memory cell MSC and the least significant memory cell LSC may be coupled to bit lines that are different but not adjacent to each other. Purely by way of example, with reference to the group of memory cells 22.sub.1,1, the MSC cell may be coupled to the bit line BL.sub.1 and the LSC cell may be coupled to the bit line BL.sub.4.

[0244] For example, the groups of memory cells 22.sub.i,j may each comprise a number of memory cells greater than two, each configured to map a respective group of bits of the respective computation weight G.sub.i,j and each configured to be activated in a respective computation window, similarly to what has been discussed in reference to FIGS. 6-8.

[0245] For example, the memory cells 20 may be resistive memory cells not based on PCM materials, but on different technologies; for example, they may be magnetoresistive (MRAM), resistive (RRAM) or static (SRAM) memory cells.

[0246] For example, the IMC device 10 may comprise a number of digital detectors and/or DSPs lower than the number L of output data y.sub.1, . . . , y.sub.L. In this case, the generation of the charge signals q.sub.1, . . . , q.sub.L starting from the respective bit currents may be controlled by specific multiplexing circuits known per se.

[0247] For example, the DSPs 171, . . . , 17L may be optional and the IMC device 10 may provide at output directly the charge signals q.sub.1, . . . , q.sub.L.

[0248] One or more of the digital detectors 161, . . . , 16L may comprise circuits, units or modules different from what has been shown and described, depending on the specific implementation. For example, one or more of the digital detectors 161, . . . , 16L may comprise, upstream of the integrator 52 (or incorporated in the integrator 52) current conditioning circuits such as for example current mirrors, filters, amplifiers, reducers, etc.

[0249] Finally, the different embodiments described above may be combined to provide further solutions.

[0250] According to one aspect, the present invention also relates to a computer program comprising instructions. Such instructions may be executed by the in-memory computation device 10 comprising the memory array 12 including a group of memory cells 22.sub.i,j comprising a first memory cell MSC coupled to a first word line WL.sub.j and a first bit line BL.sub.i,MSC, where the first memory cell has a first number of bits N.sub.MSC and is programmed to have a first electrical quantity R.sub.i,MSC (or g.sub.i,MSC) as a function of a first computation weight G.sub.i,j, and a second memory cell LSC coupled to a second word line WL.sub.j and to a second bit line BL.sub.i,LSC, where the second memory cell has a second number of bits N.sub.LSC and is programmed to have a second electrical quantity R.sub.i,LSC (or g.sub.i,LSC) as a function of the first computation weight. Such instructions comprise, by an activation circuit 14 and towards the in-memory computation device 10: providing a first activation signal S.sub.j,MSC to the first word line WL.sub.j during a first computation window CW.sub.1, the first activation signal having a first duration T.sub.j,MSC which is a function of a first input value x.sub.j; and providing a second activation signal (S.sub.j,LSC) to the second word line (WL.sub.j) during a second computation window (CW.sub.2) distinct from the first computation window, the second activation signal having a second duration (T.sub.j,LSC) which is a function of the first input value, wherein the first memory cell (MSC) is configured to be traversed, when activated during the first computation window (CW.sub.1), by a first cell current (I.sub.MSC) which is a function of the first electrical quantity (R.sub.MSC) and the first activation duration (T.sub.j,MSC), wherein the second memory cell (LSC) is configured to be traversed, when activated during the second computation window (CW.sub.2), by a second cell current (I.sub.LSC) which is a function of the second electrical quantity (R.sub.LSC) and the second activation duration (T.sub.j,LSC), wherein the first bit line (BL.sub.i,MSC) is configured to be traversed, during the first computation window (CW.sub.1), by a first bit line current (I.sub.BLi,MSC) which is a function of the first cell current (I.sub.MSC) and wherein the second bit line (BL.sub.i,LSC) is configured to be traversed, during the second computation window (CW.sub.2), by a second bit line current (I.sub.BLi,LSC) which is a function of the second cell current (I.sub.LSC), said instructions being further configured to cause the control device to, by a read circuit (15): generate a first integration signal (Q.sub.i,MSC, IN.sub.A) indicative of a time integral of the first bit line current during the first computation window; generate a second integration signal (Q.sub.i,LSC, IN.sub.A) indicative of a time integral of the second bit line current during the second computation window; and provide a digital signal (q.sub.i) indicative of a sum of the first and the second integration signals, wherein the first activation duration (T.sub.j,MSC) is different from the second activation duration (T.sub.j,LSC) and at least one of the first activation duration (T.sub.j,MSC) and the second activation duration (T.sub.j,LSC) is also a function of at least one of the first number of bits (N.sub.MSC) and the second number of bits (N.sub.LSC); and/or wherein providing the digital signal comprises multiplying at least one of the first integration signal and the second integration signal by at least one multiplication factor (P.sub.MSC, P.sub.LSC) which is a function of at least one of the first and the second number of bits.

[0251] In an implementation, wherein each of the first and the second memory cells comprise a respective current path comprising a variable-resistance storage element and a selection element and extending between a common node and a reference potential node, the selection element of the first memory cell and the second memory cell being configured to selectively close the respective current path in response to the reception of the first activation signal and, respectively, the second activation signal.

[0252] In an implementation, the first and the second memory cells are non-volatile memory cells based on phase-change material.