Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a hardware circuit configured as a signed multiword multiplier. The circuit includes a processing circuit that receives inputs that each have a respective bit-width. The processing circuit can represent at least one input as a signed multiword input based on the first input having a bit-width that exceeds a fixed bit-width of the hardware circuit. The circuit includes signed multipliers that are each configured to multiply signed inputs. Each signed multiplier includes multiplication circuitry configured to: receive the signed multiword input; receive a signed second input; and generate a signed output in response to multiplying the signed multiword input with the signed second input.

A group of memory cells includes a first cell with a first number of bits, coupled to a first bit line and programmable with a first weight and a second cell with a second number of bits, coupled to a second bit line and programmable with the first weight. An activation circuit applies first and second activation signals to the first and second cells during first and second windows, respectively. The activation signals have respective durations as a function of an input value and, optionally, a number of bits of the first or second cell. A read circuit generates first and second signals indicative of a time integral of current in the first and second bit lines during the first and second windows, respectively, and outputs a digital signal indicative of a sum between the first and second signals, optionally also as a function of number of bits.