VSG Frequency Control Method, Device and Storage Medium Based on Power Correction

Abstract

VSG Frequency Control Method, Device and Storage Medium based on Power Correction, belonging to the field of power electronics technology, which addresses the problem of suppressing VSG output power oscillations. The technical solution of the present application corrects the output power P.sub.e(s) and feeds the corrected value back to the control loop to suppress power oscillations. The transfer function of the power correction stage G(s) is flexible and can be configured with appropriate parameters according to the system's inherent phase margin. Additionally, principles for selecting the parameters of the correction coefficients .sub.1 and .sub.2 are also provided. The adjustment coefficients of the power correction stage, the values of .sub.1 and .sub.2 do not affect the effect of the steady-state gain during the transient process. The present application can not only suppress VSG output power oscillations, but also provide a larger inertial support, thereby improving the stability of the VSG system.

Claims

1. A Virtual Synchronous Generator (VSG) frequency control method based on power correction, comprising the following steps: S1. obtaining an output power P.sub.e(s) in the VSG control loop, multiplying the out power by a transfer function G(s) of a correction stage, and feeding it back to a frequency generation stage of an active power-frequency control loop, wherein P.sub.e(s) refers to an output power at a VSG grid connection point, obtained through sampling and calculation; S2. obtaining a frequency according to the active power-frequency control stage in the VSG control loop, and compensating the frequency generation stage from the step S1 into the control loop to obtain a compensated frequency *; S3. designing the parameters of coefficients .sub.1 and .sub.2 in the transfer function G(s) of the power correction stage based on the transfer function G(s) of the power correction stage and in combination with the phase margin requirements of a system open-loop transfer function.

2. The Virtual Synchronous Generator (VSG) frequency control method based on power correction according to claim 1, wherein a calculation formula of the output power P.sub.e(s) is: $\begin{array}{cc}{P}_e\left(s\right)=\frac{3}{2}\left(e_d{i}_d+e_q{i}_q\right)& \left(1\right)\end{array}$ wherein e.sub.d, e.sub.q, i.sub.d, and i.sub.q are the d-axis and q-axis components of the voltage and current at the sampling point PCC after abc/dq0 transformation, and s is the transformation parameter in the Laplace transform.

3. The Virtual Synchronous Generator (VSG) frequency control method based on power correction according to claim 1, wherein the expression of the frequency is: $\begin{array}{cc}=\left(P_{\mathrm{ref}}\left(s\right)-P_e\left(s\right)\right)\frac{1}{J{}_{0}s+D_p{}_0}+{}_0& \left(2\right)\end{array}$ wherein J is a virtual inertia coefficient, D.sub.p is a damping coefficient, P.sub.ref(s) is a reference power, and .sub.0 is a grid rated angular frequency.

4. The Virtual Synchronous Generator (VSG) frequency control method based on power correction according to claim 3, wherein the expression of the compensated frequency * is: $\begin{array}{cc}{}^{*}=\left(P_{\mathrm{ref}}\left(s\right)-P_e\left(s\right)\right)\frac{1}{J{}_{0}s+D_p{}_0}+{}_0-P_e\left(s\right)G\left(s\right)& \left(3\right)\end{array}$ wherein G(s) is a transfer function of the correction stage.

5. The Virtual Synchronous Generator (VSG) frequency control method based on power correction according to claim 4, wherein the expression of transfer function of the correction stage is: $\begin{array}{cc}G\left(s\right)=\frac{-{}_{2}s}{\left(1+{}_{1}s+{}_{2}s\right)G_2\left(s\right)}& \left(4\right)\end{array}$ wherein .sub.1 and .sub.2 are regulation coefficients of the power correction stage, and G.sub.2(s) is a transfer function from an angular frequency in a Virtual Synchronous Generator (VSG) small-signal model to output power P.sub.e(s).

6. The Virtual Synchronous Generator (VSG) frequency control method based on power correction according to claim 5, wherein the expression of the transfer function G.sub.2(s) from the angular frequency in the Virtual Synchronous Generator (VSG) small-signal model to output power P.sub.e(s) is: $\begin{array}{cc}{G}_2\left(s\right)=\frac{K_s\left(s\right)}{s}=\frac{\frac{3E{U}_g}{\sqrt{{\left(s{L}_X+R_X\right)}^2+{\left({}_0{L}_X\right)}^2}}}{s}& \left(5\right)\end{array}$ wherein, L.sub.X is the sum of filter inductance L.sub.f and transmission line inductance L.sub.g, R.sub.X is the sum of the resistances in transmission line, E is a VSG output voltage amplitude, and U.sub.g is a grid-side voltage.

7. The Virtual Synchronous Generator (VSG) frequency control method based on power correction according to claim 6, wherein the expression of the system open-loop transfer function is: $\begin{array}{cc}{G}_{\mathrm{open}}\left(s\right)=\frac{1}{\left(J{}_{0}s+D_p{}_0\right)}{G}_2\left(s\right)\frac{1+\left({}_1+{}_2\right)s}{1+{}_{1}s}& \left(6\right)\end{array}$ wherein the system's phase margin is expressed as: $\begin{array}{cc}PM=180+\left[G_{\mathrm{open}}\left(s\right)\right]& \left(7\right)\end{array}$ wherein using the system's phase margin as an indicator to design the parameters of the adjustment coefficients .sub.1 and .sub.2 of the power correction stage.

8. The Virtual Synchronous Generator (VSG) frequency control method based on power correction according to claim 7, wherein the process for designing the parameters of the adjustment coefficients .sub.1 and .sub.2 of the power correction stage is as follows: equivalently representing the power correction stage as a lead-lag compensator, with its characteristic expressed as: $\begin{array}{cc}\{\begin{array}{c}\left({}_m\right)=\arctan \frac{\frac{{}_2}{{}_1}}{2\sqrt{\frac{{}_1+{}_2}{{}_1}}}\\ {}_m=\frac{1}{{}_1\sqrt{\frac{{}_1+{}_2}{{}_2}}}\end{array}& \left(8\right)\end{array}$ wherein (.sub.m) is a maximum lead angle provided by the power correction stage, and .sub.m is an angular frequency corresponding to the maximum lead angle; wherein the cutoff frequency and system's phase margin can be derived from formula (6), with the expression shown in formula (9): $\begin{array}{cc}\{\begin{array}{c}.Math.\frac{.Math.G_2\left(s\right).Math.\sqrt{{\left(\left({}_1+{}_2\right){}_c\right)}^2+1}}{\sqrt{{\left(J{}_0{}_c\right)}^2+{\left(D_p{}_0\right)}^2}.Math.\sqrt{{\left({}_1{}_c\right)}^2+1}}.Math.=1\\ =180-\arctan \frac{J{}_c}{D_p}+G_2\left({}_c\right)+\left({}_c\right)\end{array}& \left(9\right)\end{array}$ wherein .sub.c is the cutoff frequency of the VSG system after adding active power correction, (.sub.c) is the corresponding phase angle at this cutoff frequency after adding power correction, the specific expression is: $\begin{array}{cc}\left({}_c\right)=\arctan \frac{{}_2{}_c}{1+{}_1\left({}_1+{}_2\right){}_c^2}& \left(10\right)\end{array}$ setting .sub.c=.sub.m, and substituting formula (8) and (10) into formula (9) to obtain the binary formula s for .sub.1 and .sub.2 as shown in formulas (11) and (12): $\begin{array}{cc}{}_1=\sqrt{\frac{\begin{array}{c}{D}_p^2\frac{{}_1+{}_2}{{}_1}+\\ \sqrt{{\left(D_p{}_0\right)}^4{\left(\frac{{}_1+{}_2}{{}_1}\right)}^2+4{.Math.G_2\left(s\right).Math.}^2{\left(\frac{{}_1+{}_2}{{}_1}\right)}^3{\left(J{}_0\right)}^2}\end{array}}{2{.Math.G_2\left(s\right).Math.}^2{\left(\frac{{}_1+{}_2}{{}_1}\right)}^3}}& \left(11\right)\end{array}$ $\begin{array}{cc}{}_1=\frac{J{}_0}{D_p{}_0}\frac{2{\left(\frac{{}_1+{}_2}{{}_1}\right)}^{\frac{1}{2}}}{{\left(\frac{{}_1+{}_2}{{}_1}\right)}^{\frac{3}{2}}+2\cot -{\left(\frac{{}_1+{}_2}{{}_1}\right)}^{\frac{1}{2}}}& \left(12\right)\end{array}$ selecting the phase margin , combine formula s (11) and (12) to determine the specific values of parameters .sub.1 and .sub.2.

9. (canceled)

10. (canceled)

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG. 1 is a Flowchart of the VSG frequency control method based on power correction;

[0036] FIG. 2 is a VSG main circuit topology and control structure;

[0037] FIG. 3 is a VSG active power-frequency control stage without correction;

[0038] FIG. 4 is a VSG active power-frequency control stage with power correction stage;

[0039] FIG. 5 is a VSG main circuit topology and control structure with power correction stage;

[0040] FIG. 6(a) is an operating condition under a reference power impact;

[0041] FIG. 6(b) is an operating condition under a reference power step;

[0042] FIG. 6(c) is an operating condition under a grid angular frequency step;

[0043] FIG. 7(a) is a VSG output power response during reference power impact;

[0044] FIG. 7(b) is a VSG output angular frequency response during reference power impact;

[0045] FIG. 8(a) is a VSG output power response during reference power step;

[0046] FIG. 8(b) is a VSG output angular frequency response during reference power step;

[0047] FIG. 9(a) is a VSG output power response during grid angular frequency step;

[0048] FIG. 9(b) is a VSG output angular frequency response during grid angular frequency step.

DETAILED DESCRIPTION

[0049] To make the purpose, technical solution, and advantages of the embodiments of the present application clearer, the following will provide a clear and complete description of the technical solutions in the embodiments of the present application. Obviously, the described embodiments represent only a portion of the embodiments of the present application, not all possible embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary skilled practitioners in the field without creative effort also fall within the protection scope of the present application.

[0050] The following further describes the technical solution of the present application in combination with the specification drawings and specific embodiments:

Embodiment 1

[0051] As shown in FIG. 1, the Virtual Synchronous Generator (VSG) frequency control method based on power correction in this embodiment comprises the following steps: [0052] Step 1: obtaining an output power P.sub.e(s) in the VSG control loop, multiplying the out power by a transfer function G(s) of a correction stage, and feeding it back to a frequency generation stage of an active power-frequency control loop, thereby suppressing power oscillations and increasing system robustness, wherein P.sub.e(s) refers to an output power at a VSG grid connection point, obtained through sampling and calculation; [0053] Step 2: obtaining a frequency according to the active power-frequency control stage in the VSG control loop, and compensating the frequency generation stage from the step S1 into the control loop to obtain a compensated frequency *; [0054] Step 3: designing the parameters of coefficients .sub.1 and .sub.2 in the transfer function G(s) of the power correction stage based on the transfer function G(s) of the power correction stage and in combination with the phase margin requirements of a system open-loop transfer function.

[0055] FIG. 2 illustrates the main circuit topology and control structure of the embodiment based on the Virtual Synchronous Generator (VSG) power correction strategy in the present application, wherein a calculation formula of the output power P.sub.e(s) is shown in formula (1):

[00012]$\begin{array}{cc}{P}_e\left(s\right)=\frac{3}{2}\left(e_d{i}_d+e_q{i}_q\right)& \left(1\right)\end{array}$ [0056] wherein e.sub.d, e.sub.q, i.sub.d, and i.sub.q are the d-axis and q-axis components of the voltage and current at the sampling point PCC after abc/dq0 transformation, and s is the transformation parameter in the Laplace transform.

[0057] FIG. 3 shows the small-signal model of the VSG. According to the active power-frequency control stage in the VSG small-signal model, the expression for frequency can be obtained as shown in formula (2):

[00013]$\begin{array}{cc}=\left(P_{\mathrm{ref}}\left(s\right)-P_e\left(s\right)\right)\frac{1}{J{}_{0}s+D_p{}_0}+{}_0& \left(2\right)\end{array}$ [0058] wherein J is a virtual inertia coefficient, D.sub.p is a damping coefficient, P.sub.ref(s) is a reference power, and .sub.0 is a grid rated angular frequency.

[0059] Adding the frequency generation stage of the active power-frequency control loop mentioned in Step 1 to the VSG control loop to obtain the VSG active power-frequency control stage shown in FIG. 4. The expression of the compensated frequency * is obtained as shown in formula (3):

[00014]$\begin{array}{cc}{}^{*}=\left(P_{\mathrm{ref}}\left(s\right)-P_e\left(s\right)\right)\frac{1}{J{}_{0}s+D_p{}_0}+{}_0-P_e\left(s\right)G\left(s\right)& \left(3\right)\end{array}$

[0060] The corresponding Virtual Synchronous Generator (VSG) main circuit topology and control structure are shown in FIG. 5.

[0061] The expression of the transfer function G(s) of the correction stage in step 3 is:

[00015]$\begin{array}{cc}G\left(s\right)=\frac{-{}_{2}s}{\left(1+{}_{1}s+{}_{2}s\right)G_2\left(s\right)}& \left(4\right)\end{array}$ [0062] wherein .sub.1 and .sub.2 are regulation coefficients of the power correction stage, and G.sub.2(s) is a transfer function from an angular frequency in a Virtual Synchronous Generator (VSG) small-signal model to output power P.sub.e(s), with its expression shown in formula (5):

[00016]$\begin{array}{cc}{G}_2\left(s\right)=\frac{K_s\left(s\right)}{s}=\frac{\frac{3E{U}_g}{\sqrt{{\left(s{L}_X+R_X\right)}^2+{\left({}_0{L}_X\right)}^2}}}{s}& \left(5\right)\end{array}$

[0063] In the formula, L.sub.X is the sum of filter inductance L.sub.f and transmission line inductance L.sub.g, R.sub.X is the sum of the resistances in transmission line, E is a VSG output voltage amplitude, and U.sub.g is a grid-side voltage.

[0064] After adding the frequency generation stage, according to FIG. 4 and combining formula s (4) and (5), the open-loop transfer function of the system can be represented by formula (6):

[00017]$\begin{array}{cc}{G}_{\mathrm{open}}\left(s\right)=\frac{1}{\left(J{}_{0}s+D_p{}_0\right)}{G}_2\left(s\right)\frac{1+\left({}_1+{}_2\right)s}{1+{}_{1}s}& \left(6\right)\end{array}$

[0065] At this point, the system's phase margin can be expressed as:

[00018]$\begin{array}{cc}PM=180+\left[G_{\mathrm{open}}\left(s\right)\right]& \left(7\right)\end{array}$

[0066] From formula (7), it can be seen that the system's phase margin PM can be used as an indicator to design the regulation coefficients .sub.1 and .sub.2 in the power correction stage in formula (6).

[0067] The design process for the coefficients .sub.1 and .sub.2 in the correction stage G(s) is as follows:

[0068] The correction strategy based on power correction feedback mentioned in the present application can be equivalent to a lead-lag compensator, whose characteristics can be expressed as:

[00019]$\begin{array}{cc}\{\begin{array}{c}\left({}_m\right)=\arctan \frac{\frac{{}_2}{{}_1}}{2\sqrt{\frac{{}_1+{}_2}{{}_1}}}\\ {}_m=\frac{1}{{}_1\sqrt{\frac{{}_1+{}_2}{{}_2}}}\end{array}& \left(8\right)\end{array}$ [0069] wherein (.sub.m) is a maximum lead angle provided by the power correction stage, and .sub.m is an angular frequency corresponding to the maximum lead angle. [0070] wherein the cutoff frequency and system's phase margin can be derived from formula (6), with the expression shown in formula (9):

[00020]$\begin{array}{cc}\{\begin{array}{c}.Math.\frac{.Math.G_2\left(s\right).Math.\sqrt{{\left(\left({}_1+{}_2\right){}_c\right)}^2+1}}{\sqrt{{\left(J{}_0{}_c\right)}^2+{\left(D_p{}_0\right)}^2}.Math.\sqrt{{\left({}_1{}_c\right)}^2+1}}.Math.=1\\ =180-\arctan \frac{J{}_c}{D_p}+G_2\left({}_c\right)+\left({}_c\right)\end{array}& \left(9\right)\end{array}$ [0071] wherein .sub.c is the cutoff frequency of the VSG system after adding active power correction, (.sub.c) is the corresponding phase angle at this cutoff frequency after adding power correction, the specific expression is:

[00021]$\begin{array}{cc}\left({}_c\right)=\arctan \frac{{}_2{}_c}{1+{}_1\left({}_1+{}_2\right){}_c^2}& \left(10\right)\end{array}$

[0072] In order to fully utilize the maximum lead angle provided by the power correction stage, setting .sub.c=.sub.m, and substituting formula (8) and (10) into formula (9) to obtain the binary formula s for .sub.1 and .sub.2 as shown in formulas (11) and (12):

[00022]$\begin{array}{cc}{}_1=\sqrt{\frac{\begin{array}{c}{D}_p^2\frac{{}_1+{}_2}{{}_1}+\\ \sqrt{{\left(D_p{}_0\right)}^4{\left(\frac{{}_1+{}_2}{{}_1}\right)}^2+4{.Math.G_2\left(s\right).Math.}^2{\left(\frac{{}_1+{}_2}{{}_1}\right)}^3{\left(J{}_0\right)}^2}\end{array}}{2{.Math.G_2\left(s\right).Math.}^2{\left(\frac{{}_1+{}_2}{{}_1}\right)}^3}}& \left(11\right)\end{array}$$\begin{array}{cc}{}_1=\frac{J{}_0}{D_p{}_0}\frac{2{\left(\frac{{}_1+{}_2}{{}_1}\right)}^{\frac{1}{2}}}{{\left(\frac{{}_1+{}_2}{{}_1}\right)}^{\frac{3}{2}}+2\cot -{\left(\frac{{}_1+{}_2}{{}_1}\right)}^{\frac{1}{2}}}& \left(12\right)\end{array}$

[0073] Generally, the larger the system's phase margin, the more stable the system becomes; however, an excessive phase margin will slow down the system response speed. Therefore, after comprehensive consideration, the present application selects a phase margin of =35. By combining formulas (11) and (12), the specific values of parameters .sub.1 and .sub.2 can be determined.

[0074] To verify the effectiveness of the method proposed in the present application, the main circuit topology and control structure model of the Virtual Synchronous Generator (VSG) system as shown in FIG. 5 were built in Matlab/Simulink. The system parameters are specified in Table 1.

TABLE-US-00001 TABLE 1 Specific Parameters of the VSG System Parameter Symbol Value DC Voltage V.sub.dc 700 V Grid Voltage U.sub.g 220 V Switching Frequency f.sub.s 10 kHz Fundamental Frequency f.sub.0 50 Hz Filter Inductance L.sub.f 0.5 mH Filter Capacitance C.sub.f 50 F Damping Resistance R.sub.c 0.2 Line Inductance L.sub.g 0.5 mH Active Power Reference Value P.sub.ref 3 kW Reactive Power Reference Value Q.sub.ref 0 var Virtual Inertia J 2 kg .Math. m.sup.2 Damping Coefficient D.sub.p 1000 W .Math. s/rad Reactive Virtual Inertia Coefficient k.sub.q 5 mV/var Modulation coefficient D.sub.q 321

[0075] Two groups of comparative experiments were established: one without correction and one with the correction strategy proposed in the present application. The VSG output transient response was observed when the grid frequency and reference power were disturbed, and frequency domain analysis was conducted based on system response performance indicators.

[0076] FIGS. 6(a), 6(b), and 6(c) show the operating conditions under reference power impact, reference power step, and grid angular frequency step in the method of the present application; FIGS. 7(a) and 7(b) show the VSG output power and output angular frequency responses, respectively, during reference power impact in the method of the present application; FIGS. 8(a) and 8(b) show the VSG output power and output angular frequency responses, respectively, during reference power step in the method of the present application; FIG. 9(a) and FIG. 9(b) show the VSG output power and output angular frequency response, respectively, when the grid angular frequency undergoes a step in the present application method. FIGS. 7(a), 7(b), 8(a), and 8(b) demonstrate that whether under reference power impact or reference power step, after implementing the correction control strategy of the present application, both the overshoot and adjustment time of the VSG system output power and angular frequency are reduced, confirming the effectiveness of the control strategy presented in the present application; FIGS. 9(a) and 9(b) show that although the peak value of output power decreases slightly at the moment of disturbance and the system's inertial response capability is somewhat reduced, the magnitude of this reduction is not significant and can be considered negligible compared to the advantages gained from the substantially reduced system oscillations, indicating that this correction strategy can also demonstrate excellent support capability during grid frequency disturbances.

[0077] In summary, the experimental results verify the correctness of the method proposed in the present application, which can dynamically correct the system when power oscillation occurs in Virtual Synchronous Generator (VSG) output to maintain system stability performance and obtain greater inertia support.

[0078] In the VSG control loop of the present application, the output power Pc(s) is obtained and multiplied by the correction stage G(s) before being fed back to the frequency generation stage of the active power-frequency control loop, thereby suppressing power oscillation and increasing system robustness; According to the active power-frequency control stage in the VSG control loop, the expression of frequency is obtained, and the added frequency generation stage is compensated into the control loop, thus deriving the new expression of *; Determine the specific expression of the power correction stage G(s), and design the parameters .sub.1 and .sub.2 in the power correction stage G(s) based on the phase margin requirements of the system open-loop transfer function; verify the correctness of the proposed correction strategy through experiments. The present application enhances the anti-interference capability of Virtual Synchronous Generator (VSG) by adding structures such as power correction to the VSG control loop, which provides a new approach for enhancing the stability of the VSG system. The expression of its power correction stage G(s) is flexible and can be configured with appropriate parameters according to the system's phase margin. The adjustment coefficients .sub.1 and .sub.2 of the power correction stage do not affect the steady-state gain and only take effect during the transient process. It can suppress the power oscillation of Virtual Synchronous Generator (VSG) output while simultaneously enhancing the system's inertia support capability. Compared with VSG systems without correction, the system's anti-interference performance is significantly improved after adding correction, and the ability to suppress overshoot is significantly enhanced.

Embodiment Two

[0079] An electronic device, comprising a memory and a processor, wherein the memory stores programs that enable the processor to execute the VSG frequency control method based on power correction described in Embodiment 1, and the processor is configured to execute the program stored in the memory.

Embodiment Three

[0080] A storage medium storing a computer program, wherein when executed by a processor, the computer program performs the steps of the VSG frequency control method based on power correction described in Embodiment 1.

[0081] The above embodiments are only used to explain the technical solution of the present application, not to limit it; Although the invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the preceding embodiments, or replace some technical features with equivalents; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present application.