Ultra-Thin Super Junction IGBT Device and Manufacturing Method Thereof

Abstract

The present invention discloses an ultra-thin super junction IGBT and a manufacturing method thereof, comprising: a metalized collector; a P-type collector region located on the metalized collector; an N-type FS layer located above the P-type collector region; an N-type FS isolating layer located above the N-type FS layer; a first N-type epitaxial layer located above the N-type FS isolating layer and a second N-type epitaxial layer located above the first N-type epitaxial layer; and a MOS structure located in the second N-type epitaxial layer. According to the present invention, thinning the chip thickness reduces forward conduction voltage drop and switching losses, while reducing thermal resistance and improving current conducting capability.

Claims

1. An ultra-thin super junction IGBT, characterized by comprising: a metalized collector (1); a P-type collector region (2) located on the metalized collector (1); an N-type FS layer (3) located above the P-type collector region (2); an N-type FS isolating layer (4) located above the N-type FS layer (3); a first N-type epitaxial layer (5) located above the N-type FS isolating layer (4) and a second N-type epitaxial layer (6) located above the first N-type epitaxial layer (5); and a MOS structure located in the second N-type epitaxial layer.

2. The ultra-thin super junction IGBT of claim 1, characterized in that a P column (101) is formed on two opposite sides of the first N-type epitaxial layer (5) by a deep trench etching and backfilling process.

3. The ultra-thin super junction IGBT of claim 2, characterized in that the second N-type epitaxial layer (6) comprises a trench (7) formed by reactive ion etching, a thermally grown gate oxide layer (8) provided in the trench (7), heavily doped polysilicon (9) deposited in the gate oxide layer (8), and a P-type body region (10) formed by a self-aligned process, wherein the P column (101) is not connected to the P-type body region (10).

4. The ultra-thin super junction IGBT of claim 3, characterized by further comprising mutually independent N-type emitter regions (11) provided in the P-type body region (10) on both sides of the trench (7), BPSG (12) deposited above the second N-type epitaxial layer (6), and a metalized emitter (13) located above the BPSG (12).

5. The ultra-thin super junction IGBT of claim 4, characterized by further comprising a substrate, wherein the substrate is N-type with random doping concentration or P-type with random doping concentration, and the IGBT is also applicable to P-type super junction IGBT, and semiconductor materials of silicon carbide, or gallium nitride.

6. The ultra-thin super junction IGBT of claim 1, characterized by not comprising a substrate, wherein the first N-type epitaxial layer (5) is made of a float-zone monocrystalline silicon.

7. The ultra-thin super junction IGBT of claim 6, characterized in that the N-type FS isolating layer (4) on a backside of the IGBT can be implanted or not, wherein ions when implanted are phosphorus, arsenic, hydrogen, or helium.

8. The ultra-thin super junction IGBT of claim 7, characterized in that the second N-type epitaxial layer (6) is formed by epitaxy or by steps as follows: the P column (101) is formed by deep trench etching and backfilling process on the first N-type epitaxial layer (5) structure, and then a top portion of the P column in the first N-type epitaxial layer (5) is compensated for N-type by N-type high energy implantation.

9. The ultra-thin super junction IGBT of claim 8, characterized in that the backside of the IGBT is ground to a bottom of the P column (101) and then ground by several microns, followed by implantation of the N-type FS layer (3) and the P-type collector region (2).

10. A manufacturing method for the ultra-thin super junction IGBT of claim 9, characterized by comprising steps of: S1, forming the first N-type epitaxial layer (5) on any substrate, using a reactive ion etching process to form a deep trench on the first N-type epitaxial layer (5), and backfilling the trench by P-type single crystal silicon to form the P column (101); S2, forming the second N-type epitaxial layer (6) above the first N-type epitaxial layer (5), and forming a trench (7) on the second N-type epitaxial layer (6) by reactive ion etching, then forming a gate oxide layer (8) which is thermally grown by means of dry oxidation in the trench (7), and forming a polysilicon gate electrode (9) by depositing heavily doped polysilicon in the gate oxide layer (8) and etching back; S3, forming a P-type body region (10) by using ion implantation through the self-alignment process and high-temperature drive-in, and providing an N-type emitter region (11), formed by photolithograph and implantation, in the P-type body region (10); S4, a BPSG (12) deposited above the second N-type epitaxial layer (6) being subjected to high-temperature reflow, performing contact photolithography above the BPSG (12), etching silicon with a thickness of 3000-5000 A, and depositing an top surface metal to form a metalized emitter (13); S5, turning over the substrate and thinning, grinding for several micrometers after grinding to a bottom of the P column (101), and performing first implantation of the N-type FS layer (3); S6, continuing second N-type FS isolating layer (4) implantation and impurity activation; S7, implanting and annealing the P-type collector region (2) on the side of the P-type collector region (2); and S8, forming the metalized collector (1) by depositing a metal layer on the side of the P-type collector region (2).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG. 1 is a schematic view of the structure of a conventional Trench FS-IGBT;

[0030] FIG. 2 is a schematic view of the structure of a conventional super junction IGBT;

[0031] FIG. 3 is a schematic view showing the structure of an ultra-thin super junction IGBT and the manufacturing method according to the present invention;

[0032] FIG. 4 is a schematic view showing the structure of an embodiment of an ultra-thin super junction IGBT and the manufacturing method according to the present invention;

[0033] FIG. 5-1-15 are structural views showing the manufacturing steps of an ultra-thin super junction IGBT and the manufacturing method according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skills in the art without involving any inventive effort are within the scope of the present invention.

[0035] Referring to FIGS. 1-5, an ultra-thin super junction IGBT includes: a metalized collector 1;

[0036] a P-type collector region 2 located on the metalized collector 1;

[0037] an N-type FS layer 3 located above the P-type collector region 2;

[0038] an N-type FS isolating layer 4 located above the N-type FS layer 3;

[0039] a first N-type epitaxial layer 5 located above the N-type FS isolating layer 4 and a second N-type epitaxial layer 6 located above the first N-type epitaxial layer 5, and a MOS structure located in the second N-type epitaxial layer, wherein when turning off the device, the N-type FS isolating layer formed by hydrogen ion implantation can help to reduce the switching loss.

[0040] Further, two opposite sides of the first N-type epitaxial layer 5 form a P column 101 through a deep trench etching and backfilling process. The floating P column ensures that the device operates in a conductivity modulating mode, and reduces the forward conduction voltage drop of the device.

[0041] Further, the second N-type epitaxial layer 6 comprises a trench 7 formed by reactive ion etching, a thermally grown gate oxide layer 8 arranged in the trench 7, heavily doped polysilicon 9 deposited in the gate oxide layer 8, and a P-type body region 10 formed by a self-alignment process, the P column 101 disconnected from the P-type body region 10.

[0042] Further, mutually independent N-type emitter regions 11 provided on both sides of the trench 7 and in the P-type body region 10, a BPSG 12 deposited above the second N-type epitaxial layer 6, and a metalized emitter 13 located above the BPSG 12 are further included.

[0043] Further, a substrate is further included. The substrate has a random doping concentration of N type or a random doping concentration of P type, and the IGBT can also be applied to P type super junction IGBT, and a semiconductor material of silicon carbide, or gallium nitride.

[0044] Further, no substrate is included. The first N-type epitaxial layer 5 is made of a float-zone monocrystalline silicon.

[0045] Further, the N-type FS isolating layer 4 on the backside of the IGBT can be implanted or not implanted, the ions when implanted are phosphorus, arsenic, hydrogen, or helium, and the backside of the IGBT is the side provided with the N-type FS isolating layer 4.

[0046] Further, the second N-type epitaxial layer 6 is formed by epitaxy or by steps as follows: the P column 101 is formed by deep trench etching and backfilling process on the first N-type epitaxial layer 5 structure, and then the top P column portion in the first N-type epitaxial layer 5 is compensated for N-type by N-type high energy implantation.

[0047] Further, the backside of the IGBT is ground to the bottom of the P column 101 and then ground for several micrometers, and then the N-type FS layer 3 and the P-type collector region 2 are implanted; after the backside of the IGBT is thinned, only one implantation of the N-type FS layer is needed to achieve the isolation between the P-type collector region 2 and the P column 101; further, thinning to remove part of the bottom region of the P column can reduce the electric field concentration when the device blocks voltage, thereby ensuring a sufficient breakdown voltage of the device and also reducing the thickness of the N-Drift region, which can reduce the forward conduction voltage drop of the device and reduce the switching loss. The thinned chip thickness reduces the thermal resistance of the device and increases the current capability of the device.

[0048] With reference to FIGS. 5-1-15, a manufacturing method for an ultra-thin super junction IGBT comprises the following steps:

[0049] S1, forming a first N-type epitaxial layer 5 on any substrate, using a reactive ion etching process to form a deep trench on the first N-type epitaxial layer 5, and using a backfilling P-type single crystal silicon to form a P column 101;

[0050] S2, forming a second N-type epitaxial layer 6 above the first N-type epitaxial layer 5, and forming a trench 7 on the second N-type epitaxial layer 6 by reactive ion etching, then forming a gate oxide layer 8 which is thermally grown by means of dry oxidation in the trench 7, and forming a polysilicon gate electrode 9 by depositing heavily doped polysilicon in the gate oxide layer 8 and etching back;

[0051] S3, forming a P-type body region 10 by using ion implantation through the self-alignment process and high-temperature drive-in, and providing an N-type emitter region 11, formed by photolithographic implantation, in the P-type body region 10;

[0052] S4, a BPSG 12 deposited above the second N-type epitaxial layer 6 being subjected to high-temperature reflow, performing contact photolithography above the BPSG 12, etching silicon with a thickness of 3000-5000 A, and depositing an top metal to form a metalized emitter 13;

[0053] S5, turning over the substrate and thinning, performing grinding for several micrometers after grinding to the bottom of the P column 101, and performing the first implantation of the N-type FS layer 3;

[0054] S6, continuing the second N-type FS isolating layer 4 implantation and impurity activation;

[0055] S7, implanting and annealing the P-type collector region 2 on backside of the P-type collector region 2;

[0056] and S8, forming a metalized collector 1 by depositing a metal layer on backside of the P-type collector region 2.

[0057] The number of equipment and process scales described herein is intended to simplify the description of the present invention, and applications, modifications, and variations of the present invention will be apparent to those skilled in the art.

[0058] While the implementation mode of the present invention has been disclosed above, it is not intended to be limited to the applications set forth in the description and the implementation mode, but it is fully capable of being applied to various fields suitable for the present invention. Additional modifications will readily occur to those skilled in the art, and the present invention is not limited to the specific details and illustrative examples shown and described herein without departing from the general concept as defined by the appended claims and their equivalents.