CABLE FAILURE PROTECTION AND BATTERY KICKSTART IN AN ELECTRONIC DEVICE

Abstract

Cable failure protection and battery kickstart in an electronic device is provided. When the electronic device is attached to an external power supply via a universal serial bus type-C (USB-C) cable, it is important to protect the electronic device from being damaged by a cable failure (e.g., overcurrent, overtemperature, and/or faulty cable). Additionally, when a battery in the electronic device is fully depleted, it is necessary to kickstart recharging of the depleted battery upon attaching to the USB-C cable. Herein, a power management integrated circuit (PMIC) is provided in the electronic device and configured in accordance with the USB-C standard to protect the electronic device from the cable failure and kickstart recharging of the depleted battery. By integrating cable failure protection and battery kickstart functionalities into the PMIC, it is possible to reduce cost and footprint of the PMIC, thus making the PMIC suitable for small formfactor electronic devices.

Claims

1. A universal serial bus type-C (USB-C) charging system comprising: a USB-C connector comprising: a pair of configuration channel (CC) pins configured to indicate whether the USB-C connector is attached to an external power supply via a USB-C cable; and a bus voltage (VBUS) pin configured to receive a bus voltage from the external power supply when the pair of CC pins indicate that the USB-C connector is attached to the external power supply; and a power management integrated circuit (PMIC) coupled to the USB-C connector and comprising: a battery charging circuit coupled to the VBUS pin and configured to charge an internal always-on voltage regulator based on the bus voltage to provide an always-on voltage (VAO); and a control circuit coupled to the pair of CC pins and configured to: emulate a detachment condition to the external power supply via the pair of CC pins in response to detecting a failure condition of the USB-C cable to thereby cancel the bus voltage on the VBUS pin; and emulate an attachment condition to the external power supply via the pair of CC pins when the internal always-on voltage regulator is depleted to thereby kickstart the bus voltage on the VBUS pin to charge the internal always-on voltage regulator.

2. The USB-C charging system of claim 1, wherein the control circuit is further configured to emulate the detachment condition under the failure condition without requiring the USB-C connector to be physically detached from the external power supply.

3. The USB-C charging system of claim 1, wherein the control circuit is further configured to pull up a respective voltage on each of the pair of CC pins in the failure condition to thereby emulate the detachment condition to the external power supply.

4. The USB-C charging system of claim 1, wherein the control circuit is further configured to pull down a respective voltage on each of the pair of CC pins when the internal always-on voltage regulator is depleted to thereby emulate the attachment condition to the external power supply.

5. The USB-C charging system of claim 4, wherein the control circuit is further configured to operate based on the respective voltage on each of the pair of CC pins when the internal always-on voltage regulator is depleted.

6. The USB-C charging system of claim 1, wherein the PMIC further comprises a protection circuit coupled to the battery charging circuit and the control circuit, the protection circuit is configured to detect the failure condition of the USB-C cable and provide a failure correction signal to the control circuit in response to detecting the failure condition.

7. The USB-C charging system of claim 6, wherein the protection circuit is activated when the USB-C connector is attached to the external power supply and the always-on voltage (VAO) is above a reference threshold.

8. The USB-C charging system of claim 6, wherein the protection circuit is further configured to: receive a negative temperature coefficient (NTC) voltage from an NTC thermistor placed in proximity to the USB-C connector; and provide the failure correction signal to the control circuit when the NTC voltage is below a detection threshold.

9. An electronic device comprising a universal serial bus type-C (USB-C) charging system, the USB-C charging system comprises: a USB-C connector comprising: a pair of configuration channel (CC) pins configured to indicate whether the USB-C connector is attached to an external power supply via a USB-C cable; and a bus voltage (VBUS) pin configured to receive a bus voltage from the external power supply when the pair of CC pins indicate that the USB-C connector is attached to the external power supply; and a power management integrated circuit (PMIC) coupled to the USB-C connector and comprising: a battery charging circuit coupled to the VBUS pin and configured to charge an internal always-on voltage regulator based on the bus voltage to provide an always-on voltage (VAO); and a control circuit coupled to the pair of CC pins and configured to: emulate a detachment condition to the external power supply via the pair of CC pins in response to detecting a failure condition of the USB-C cable to thereby cancel the bus voltage on the VBUS pin; and emulate an attachment condition to the external power supply via the pair of CC pins when the internal always-on voltage regulator is depleted to thereby kickstart the bus voltage on the VBUS pin to charge the internal always-on voltage regulator.

10. The electronic device of claim 9, wherein the control circuit is further configured to emulate the detachment condition under the failure condition without requiring the USB-C connector to be physically detached from the external power supply.

11. The electronic device of claim 9, wherein the control circuit is further configured to pull up a respective voltage on each of the pair of CC pins in the failure condition to thereby emulate the detachment condition to the external power supply.

12. The electronic device of claim 9, wherein the control circuit is further configured to pull down a respective voltage on each of the pair of CC pins when the internal always-on voltage regulator is depleted to thereby emulate the attachment condition to the external power supply.

13. The electronic device of claim 12, wherein the control circuit is further configured to operate based on the respective voltage on each of the pair of CC pins when the internal always-on voltage regulator is depleted.

14. The electronic device of claim 9, wherein the PMIC further comprises a protection circuit coupled to the battery charging circuit and the control circuit, the protection circuit is configured to detect the failure condition of the USB-C cable and provide a failure correction signal to the control circuit in response to detecting the failure condition.

15. The electronic device of claim 14, wherein the protection circuit is activated when the USB-C connector is attached to the external power supply and the always-on voltage (VAO) is above a reference threshold.

16. The electronic device of claim 14, wherein the protection circuit is further configured to: receive a negative temperature coefficient (NTC) voltage from an NTC thermistor placed in proximity to the USB-C connector; and provide the failure correction signal to the control circuit when the NTC voltage is below a detection threshold.

17. A method for enabling cable failure protection and battery kickstart in a universal serial bus type-C (USB-C) charging system comprising: indicating, via a pair of configuration channel (CC) pins in a USB-C connector, whether the USB-C connector is attached to an external power supply via a USB-C cable; receiving, via a bus voltage (VBUS) pin in the USB-C connector, a bus voltage from the external power supply when the pair of CC pins indicate that the USB-C connector is attached to the external power supply; charging an internal always-on voltage regulator based on the bus voltage to provide an always-on voltage (VAO); emulating a detachment condition to the external power supply via the pair of CC pins in response to detecting a failure condition of the USB-C cable to thereby cancel the bus voltage on the VBUS pin; and emulating an attachment condition to the external power supply via the pair of CC pins when the internal always-on voltage regulator is depleted to thereby kickstart the bus voltage on the VBUS pin to charge the internal always-on voltage regulator.

18. The method of claim 17, further comprising pulling up a respective voltage on each of the pair of CC pins in the failure condition to thereby emulate the detachment condition to the external power supply.

19. The method of claim 17, further comprising pulling down a respective voltage on each of the pair of CC pins when the internal always-on voltage regulator is depleted to thereby emulate the attachment condition to the external power supply.

20. The method of claim 17, further comprising: receiving a negative temperature coefficient (NTC) voltage from an NTC thermistor placed in proximity to the USB-C connector; and indicating the failure condition when the NTC voltage is below a detection threshold.

Description

DETAILED DESCRIPTION

[0020] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0021] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term and/or includes any and all combinations of one or more of the associated listed items.

[0022] It will be understood that when an element such as a layer, region, or substrate is referred to as being on or extending onto another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly on or extending directly onto another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being over or extending over another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly over or extending directly over another element, there are no intervening elements present. It will also be understood that when an element is referred to as being connected or coupled to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being directly connected or directly coupled to another element, there are no intervening elements present.

[0023] Relative terms such as below or above or upper or lower or horizontal or vertical may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms a, an, and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises, comprising, includes, and/or including when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0026] Embodiments are described herein with reference to cable failure protection and battery kickstart in an electronic device. When the electronic device is attached to an external power supply via a universal serial bus type-C (USB-C) cable, it is important to protect the electronic device from being damaged by a cable failure (e.g., overcurrent, overtemperature, and/or faulty cable). Additionally, when a battery in the electronic device is fully depleted, it is necessary to kickstart recharging of the depleted battery upon attaching to the USB-C cable. In this regard, a power management integrated circuit (PMIC) is provided in the electronic device and configured in accordance with the USB-C standard to protect the electronic device from the cable failure and kickstart recharging of the depleted battery. By integrating cable failure protection and battery kickstart functionalities into the PMIC, as opposed to using discrete solutions, it is possible to reduce cost and footprint of the PMIC, thus making the PMIC suitable for small formfactor electronic devices.

[0027] FIG. 2 is a schematic diagram of an exemplary USB-C charging system 16 wherein a protection circuit 18 and a control circuit 20 can be integrated into a PMIC 22 to enable cable failure protection and battery kickstart when the PMIC 22 is attached to an external power supply 24 via a USB-C cable 26. The PMIC 22 is attached to the external power supply 24 (e.g., wall charger, portable power bank, etc.) via a USB-C connector 28. The USB-C connector 28 includes all the physical pins as defined in release 2.0 of the USB-C cable and connector specification (hereinafter USB-C specification). Among all the physical pins in the USB-C connector 28, only a pair of configuration channel (CC) pins (denoted as CC1, CC2) and a bus voltage pin VBUS are illustrated herein. All other pins in the USB-C connector 28 are omitted for the sake of simplicity.

[0028] According to the USB-C specification, the PMIC 22 will maintain unterminated voltages V.sub.CC1, V.sub.CC2 on the pair of CC pins CC1, CC2, respectively, before the USB-C connector 28 is attached to the external power supply 24. When the USB-C connector 28 is attached to the external power supply 24, the PMIC 22 will pull down at least one of the unterminated voltages V.sub.CC1, V.sub.CC2 such that the external power supply 24 can detect the attachment of the PMIC 22 and assert a bus voltage V.sub.BUS on the bus voltage pin VBUS. Accordingly, a battery charging circuit 30 can generate a charging current I.sub.CHG based on the bus voltage V.sub.BUS to thereby charge a battery 32 to a battery voltage V.sub.BAT. The PMIC 22 may further include an internal always-on voltage regulator 34, which can be a low dropout (LDO) regulator. The internal always-on voltage regulator 34 can generate an always-on voltage (VAO) based on the bus voltage V.sub.BUS to thereby power normal operation of the PMIC 22. When the PMIC 22 is detached from the external power supply 24, the voltages on the pair of CC pins CC1, CC2 will return to the unterminated voltages V.sub.CC1, V.sub.CC2. Accordingly, the external power supply can detect the detachment of the PMIC 22 and cancel the bus voltage V.sub.BUS.

[0029] As described in detail below, the PMIC 22 can be configured to emulate the detachment condition by raising the voltages V.sub.CC1, V.sub.CC2 in response to detecting a cable failure condition (e.g., overcurrent, overtemperature, faulty cable, etc.) to thereby cause the external power supply 24 to cancel the bus voltage V.sub.BUS without having to physically detach the PMIC 22 from the external power supply 24. In the event that the battery 32 is fully depleted, the PMIC 22 can operate based on respective voltages on the pair of CC pins CC1, CC2 to pull down the voltage V.sub.CC1, V.sub.CC2 to thereby emulate the attachment condition. As a result, the external power supply 24 will assert the bus voltage V.sub.BUS on the bus voltage pin VBUS to allow the battery charging circuit 30 to recharge the fully depleted battery 32 to provide the always-on voltage VAO.

[0030] In an embodiment, a negative temperature coefficient (NTC) thermistor 36 (e.g., 10 K, 3380K) is provided in proximity to the USB-C connector 28 to thereby generate an NTC voltage V.sub.NTC. Herein, the NTC voltage V.sub.NTC is inversely related to the temperature of the USB-C connector 28. When the temperature of the USB-C connector 28 increases, the NTC voltage V.sub.NTC will decrease. In contrast, when the temperature of the USB-C connector 28 decreases, the NTC voltage V.sub.NTC will increase.

[0031] The protection circuit 18 can be activated by the battery charging circuit 30 based on an activation signal VAO_OK. Once activated, the protection circuit 18 is configured to determine whether the USB-C connector 28 and/or the USB-C cable 26 is faulty based on the NTC voltage V.sub.NTC. Should the protection circuit 18 determine that the USB-C connector 28 and/or the USB-C cable 26 is faulty, the protection circuit 18 will provide a failure correction signal CC_PLDWN to the control circuit 20. Accordingly, the control circuit 20 will emulate the detachment condition by pulling up one or more of the voltages V.sub.CC1, V.sub.CC2 on one or more of the pair of CC pins CC1, CC2. In response, the external power supply 24 will cancel the bus voltage V.sub.BUS to thereby protect the PMIC 22.

[0032] Notably, the control circuit 20 is also powered by the always-on voltage VAO under normal operating conditions. However, when the battery 32 is fully depleted, the control circuit 20 may no longer be able to operate based on the always-on voltage VAO. In this regard, the control circuit 20 may instead operate based on one or more of the voltages V.sub.CC1, V.sub.CC2 on one or more of the pair of CC pins CC1, CC2. Specifically, the control circuit 20 may pull down one or more of the voltages V.sub.CC1, V.sub.CC2 to thereby emulate the attachment condition. As a result, the external power supply 24 will assert the bus voltage V.sub.BUS on the bus voltage pin VBUS to allow the battery charging circuit 30 to recharge the fully depleted battery 32.

[0033] FIG. 3 is a schematic diagram providing an exemplary detailed illustration of the PMIC 22 in FIG. 2 configured according to an embodiment of the present disclosure. Common elements between FIGS. 2 and 3 are shown therein with common element numbers and will not be re-described herein.

[0034] Herein, the battery charging circuit 30 includes a charging circuit 38 that is coupled to the bus voltage pin VBUS. When the external power supply 24 asserts the bus voltage V.sub.BUS on the bus voltage pin VBUS, the charging circuit 38 generates the charging current I.sub.CHG based on the bus voltage V.sub.BUS to thereby charge the battery 32. The internal always-on voltage regulator 34 is also charged by the bus voltage V.sub.BUS to thereby provide the always-on voltage VAO. In this regard, when the bus voltage V.sub.BUS is present on the bus voltage pin VBUS, both the battery 32 and the internal always-on voltage regulator 34 will be charged.

[0035] The protection circuit 18 is coupled to the NTC thermistor 36 via an NTC pin 40 in the PMIC 22. The protection circuit 18 includes an internal current source 42 that is powered by the internal always-on voltage VAO. The internal current source 42 is coupled to a fault detection circuit 44 via a switch SW. In this regard, the fault detection circuit 44 can be activated in presence of the internal always-on voltage VAO by closing the switch SW or deactivated in absence of the internal always-on voltage VAO by opening the switch SW.

[0036] The fault detection circuit 44 includes a fault detection comparator 46. The fault detection comparator 46 is coupled to the NTC pin 40 to receive the NTC voltage V.sub.NTC and compare the NTC voltage V.sub.NTC against a detection threshold TMP_REF. When the NTC voltage V.sub.NTC is below the detection threshold TMP_REF (V.sub.NTC<TMP_REF), the fault detection comparator 46 will generate a fault indication USB_FAULT and provide the fault indication USB_FAULT to a fault detection logic AND gate 48. The fault detection logic AND gate 48 will then provide the failure correction signal CC_PLDWN to the control circuit 20. Notably, the fault detection logic AND gate 48 will only generate the failure correction signal CC_PLDWN when the fault detection circuit 44 is activated in the presence of the always-on voltage VAO.

[0037] The protection circuit 18 also includes a pair of CC comparators 50, 52, each coupled to a respective one of the pair of CC pins CC1, CC2. Each of the CC comparators 50, 52 compares a respective one of the voltages V.sub.CC1, V.sub.CC2 against a detection threshold DET_TH to determine whether the USB-C connector 28 has been attached to the external power supply 24. A logic OR gate 54 is configured to generate a CC detection indication CC_DET when any of the voltages V.sub.CC1, V.sub.CC2 is above the detection threshold DET_TH.

[0038] The protection circuit 18 further includes a protection control comparator 56 that generates a protection enable signal TMP_PRO when the CC detection indication CC_DET and the activation signal VAO_OK, which indicates the presence of the always-on voltage VAO, are both present. The protection enable signal TMP_PRO will close the switch SW to thereby activate the fault detection circuit 44. In an embodiment, the internal always-on voltage regulator 34 will only assert the activation signal VAO_OK when the always-on voltage VAO is above a certain voltage level. As such, the fault detection circuit 44, and therefore the protection circuit 18, will not be enabled when the battery 32 is fully depleted.

[0039] The control circuit 20 includes a pair of resistors R.sub.A, R.sub.B (e.g., 5.1 K) that are coupled to the pair of CC pins CC1, CC2, respectively. The control circuit 20 also includes a first transistor 58, a second transistor 60, a third transistor 62, and a fourth transistor 64. The first transistor 58 and the second transistor 60 are coupled in parallel between the resistor R.sub.A and a ground (GND), whereas the third transistor 62 and the fourth transistor 64 are coupled in parallel between the resistor R.sub.B and the GND.

[0040] The control circuit 20 further includes a first inverter U1, a second inverter U2, a third inverter U3, and a fourth inverter U4. The first inverter U1 is coupled between the second transistor 60 and a resistor R1, the second inverter U2 is coupled between the fourth transistor 64 and the resistor R1, the third inverter U3 is coupled between the first transistor 58 and the resistor R1, and the fourth inverter U4 is coupled between the third transistor 62 and the resistor R1.

[0041] In an embodiment, the resistor R1 is coupled to the GND to ensure that a default state of the failure correction signal CC_PLDWN is kept low such that the first inverter U1 and the second inverter U2 can turn on the second transistor 60 and the fourth transistor 64, respectively, when the battery 32 is fully depleted and the rest of the PMIC 22 is powered off. Specifically, when the second transistor 60 is turned on by the first inverter U1, the resistor R.sub.A will be coupled to the GND to thereby reduce the voltage V.sub.CC1. Likewise, when the fourth transistor 64 is turned on by the second inverter U2, the resistor R.sub.B will be coupled to the GND to thereby reduce the voltage V.sub.CC2. As described earlier, by pulling down the voltages V.sub.CC1, V.sub.CC2 on the pair of CC pins CC1, CC2, it is possible to emulate the attachment condition to thereby cause the external power supply 24 to assert the bus voltage V.sub.BUS to recharge the battery 32.

[0042] FIG. 4 is a graphic diagram providing an exemplary illustration as to how the protection circuit 18 and the control circuit 20 in the PMIC 22 of FIG. 3 can enable the battery kickstart operation. Common elements between FIGS. 3 and 4 are shown therein with common element numbers and will not be re-described herein.

[0043] Prior to time T.sub.1, the PMIC 22 is not yet attached to the external power supply 24 but the battery 32 is fully depleted. At time T.sub.1, the PMIC 22 is attached to the external power supply 24 via the USB-C cable 26 and the USB-C connector 28. As such, the voltages V.sub.CC1, V.sub.CC2 on the pair of CC pins CC1, CC2 are both held high at the unterminated level. At time T.sub.2 (T.sub.2>T.sub.1), the control circuit 20 pulls down the voltages V.sub.CC1, V.sub.CC2 to emulate the attachment condition. Accordingly, at time T.sub.3 (T.sub.3T.sub.2), the external power supply 24 asserts the bus voltage V.sub.BUS on the voltage supply pin VBUS. Subsequently, at time T.sub.4 (T.sub.4>T.sub.3), the internal always-on voltage regulator 34 is sufficiently charged to the always-on voltage VAO and generates the activation signal VAO_OK. The protection control comparator 56 then generates the protection enable signal TMP_PRO at time T.sub.5 (T.sub.5>T.sub.4) to activate the protection circuit 18. The failure correction signal CC_PLDWN is kept low until the protection circuit 18 detects the cable failure.

[0044] With reference back to FIG. 3, the third inverter U3 and the fourth inverter U4 are each powered by the always-on voltage VAO. In this regard, the third inverter U3 and the fourth inverter U4 will not be operational when the battery 32 is fully depleted. When the internal always-on voltage regulator 34 is sufficiently charged to provide the always-on voltage VAO, the third inverter U3 and the fourth inverter U4 will be operational along with the protection circuit 18. As such, when the fault detection circuit 44 asserts the failure correction signal CC_PLDWN, the third inverter U3 and the fourth inverter U4 will open the first transistor 58 and the third transistor 62. Accordingly, the resistors R.sub.A, R.sub.B will become floating to thereby pull up the voltages V.sub.CC1, V.sub.CC2 to thereby emulate the detachment condition.

[0045] FIG. 5 is a graphic diagram providing an exemplary illustration as to how the protection circuit 18 and the control circuit 20 in the PMIC 22 of FIG. 3 can protect the PMIC from the cable failure. Common elements between FIGS. 3 and 5 are shown therein with common element numbers and will not be re-described herein.

[0046] At time T.sub.1, the protection circuit 18 is activated to monitor the NTC voltage V.sub.NTC. At time T.sub.2 (T.sub.2T.sub.1), the NTC voltage V.sub.NTC falls below the detection threshold TMP_REF. Accordingly, at time T.sub.3 (T.sub.3T.sub.2), the fault detection comparator 46 will generate the fault indication USB_FAULT to thereby cause the fault detection logic AND gate 48 to assert the failure correction signal CC_PLDWN. Accordingly, the third inverter U3 and the fourth inverter U4 will open the first transistor 58 and the third transistor 62, respectively, to raise the voltages V.sub.CC1, V.sub.CC2 on the pair of CC pins CC1, CC2 to thereby cause the external power supply 24 to cancel the bus voltage V.sub.BUS on the bus voltage pin VBUS. At time T.sub.4 (T.sub.4>T.sub.3), the NTC voltage V.sub.NTC rises above the detection threshold TMP_REF. Accordingly, the fault indication USB_FAULT becomes low causing the failure correction signal CC_PLDWN to be de-asserted. The third inverter U3 and the fourth inverter U4, in turn, will close the first transistor 58 and the third transistor 62, respectively, to pull down the voltages V.sub.CC1, V.sub.CC2 on the pair of CC pins CC1, CC2 to thereby cause the external power supply 24 to re-assert the bus voltage V.sub.BUS on the bus voltage pin VBUS.

[0047] The USB-C charging system 16 of FIGS. 2 and 3 can be provided in a communication device to support the embodiments described above. In this regard, FIG. 6 is a schematic diagram of an exemplary communication device 100 wherein the USB-C charging system 16 of FIGS. 2 and 3 can be provided.

[0048] Herein, the communication device 100 can be any type of communication devices, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, base stations (e.g., eNB, gNB, etc.), and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Ultra-wideband (UWB), Bluetooth, and near-field communications. The communication device 100 will generally include a control system 102, a baseband processor 104, transmit circuitry 106, receive circuitry 108, antenna switching circuitry 110, multiple antennas 112, and user interface circuitry 114. In a non-limiting example, the control system 102 can be a field-programmable gate array (FPGA), as an example. In this regard, the control system 102 can include at least a microprocessor, an embedded memory circuit, and a communication bus interface. The receive circuitry 108 receives radio frequency signals via the antennas 112 and through the antenna switching circuitry 110 from one or more base stations. A low-noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using analog-to-digital converters (ADCs).

[0049] The baseband processor 104 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 104 is generally implemented in one or more digital signal processors (DSPs) and application-specific integrated circuits (ASICs).

[0050] For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, which it encodes for transmission. The encoded data is output to the transmit circuitry 106, where a digital-to-analog converter (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission and deliver the modulated carrier signal to the antennas 112 through the antenna switching circuitry 110. The multiple antennas 112 and the replicated transmit 106 and receive circuitry 108 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0051] In an embodiment, the USB-C charging system 16 of FIGS. 2 and 3 can be operated in accordance with a process. In this regard, FIG. 7 is a flowchart of an exemplary process 200 for enabling cable failure protection and battery kickstart in the USB-C charging system 16 of FIGS. 2 and 3.

[0052] Herein, the process 200 includes indicating, via the pair of CC pins CC1, CC2 in the USB-C connector 28, whether the USB-C connector 28 is attached to the external power supply 24 via the USB-C cable 26 (step 202). The process 200 also includes receiving, via the VBUS pin in the USB-C connector 28, the bus voltage V.sub.BUS from the external power supply 24 when the pair of CC pins CC1, CC2 indicate that the USB-C connector 28 is attached to the external power supply 24 (step 204). The process 200 also includes charging the internal always-on voltage regulator 34 based on the bus voltage V.sub.BUS to provide the always-on voltage VAO (step 206). The process 200 also includes emulating the detachment condition to the external power supply 24 via the pair of CC pins CC1, CC2 in response to detecting the failure condition of the USB-C cable 26 to thereby cancel the bus voltage V.sub.BUS on the VBUS pin (step 208). The process 200 also includes emulating the attachment condition to the external power supply 24 via the pair of CC pins CC1, CC2 when the internal always-on voltage regulator 34 is depleted to thereby kickstart the bus voltage V.sub.BUS on the VBUS pin to charge the internal always-on voltage regulator 34 (step 210).

[0053] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.