SENSOR SYSTEM AND DEVICE

Abstract

The invention achieves a lower noise of a sense signal of a FET-type hydrogen sensor. For solving the above problem, one aspect of a sensor system of the invention includes a reference device and a sensor device configured using FETs on a substrate, and further, well potentials of the reference device and the sensor device are electrically isolated from each other.

Claims

1. A sensor system comprising: a P-type semiconductor substrate; a sensor FET that is formed of a P-type FET within a first N-well formed on the P-type semiconductor substrate and has sensitivity to a sensing target; and a reference FET that is formed of a P-type FET within a second N-well formed on the P-type semiconductor substrate and does not have sensitivity to the sensing target, wherein the first N-well and the second N-well are electrically isolated from each other, and the sensor system includes a detection circuit that detects a difference between threshold voltages of the sensor FET and the reference FET in a gas atmosphere.

2. The sensor system according to claim 1, further comprising: a first source-follower circuit that measures the threshold voltage of the sensor FET; and a second source-follower circuit that measures the threshold voltage of the reference FET and is provided independently of the source-follower circuit.

3. The sensor system according to claim 1, further comprising a source-follower circuit that measures the threshold voltage of the sensor FET and the threshold voltage of the reference FET, wherein in measuring the threshold voltage of the sensor FET and the threshold voltage of the reference FET, the source-follower circuit and the sensor FET or the source-follower circuit and the reference FET are switched and connected through switching.

4. The sensor system according to claim 1, further comprising a PN junction portion for temperature measurement on the P-type semiconductor substrate.

5. A sensor system comprising: a semiconductor substrate; a sensor FET that is formed of a FET within a first well formed on the semiconductor substrate and has sensitivity to a sensing target; and a reference FET that is formed of a FET within a second well formed on the semiconductor substrate and does not have sensitivity to the sensing target, wherein the first well and the second well are provided electrically isolated from each other, a source of the sensor FET and the first well are short-circuited, a source of the reference FET and the second well are short-circuited, and the sensor system includes a detection circuit that detects a difference between threshold voltages of the sensor FET and the reference FET in a gas atmosphere.

6. The sensor system according to claim 5, further comprising: a drain current source for sensor FET that is connected to the short-circuited well potential and source potential of the sensor FET; a source voltage buffer for sensor FET that receives the source potential of the sensor FET as an input and outputs the input to the detection circuit; a source-drain voltage generating circuit for sensor FET that maintains a source-drain voltage of the sensor FET constant; a drain current source for reference FET that is connected to the short-circuited well potential and source potential of the reference FET; a source voltage buffer for reference FET that receives the source potential of the reference FET as an input and outputs the input to the detection circuit; and a source-drain voltage generating circuit for reference FET that maintains a source-drain voltage of the reference FET constant.

7. A sensor device comprising: on the same semiconductor substrate, a semiconductor region; a sensor FET that is formed of a FET within a first well formed in the semiconductor region and has sensitivity to a sensing target; a reference FET that is formed of a FET within a second well formed in the semiconductor region and does not have sensitivity to the sensing target; a configuration that prevents electrical continuity between the first well and the second well; a sensor signal output terminal that outputs a signal representing a threshold voltage of the sensor FET or a change in the threshold voltage; and a reference signal output terminal that outputs a signal representing a threshold voltage of the reference FET or a change in the threshold voltage.

8. The sensor device according to claim 7, wherein the semiconductor region is a semiconductor region of a first conductivity type, the first and second wells are wells of a second conductivity type, and electrical continuity between the first and second wells of the second conductivity type is prevented by separating the first and second wells of the second conductivity type by the semiconductor region of the first conductivity type.

9. The sensor device according to claim 7, wherein electrical continuity between the first and second wells is prevented by providing a trench-type device isolation structure between the first and second wells.

10. The sensor device according to claim 7, wherein a structure that generates a signal corresponding to temperature is provided on the semiconductor substrate.

11. The sensor device according to claim 10, wherein a PN junction is provided as the structure generating the signal corresponding to temperature.

12. The sensor device according to claim 10, wherein a resistance member is provided as the structure generating the signal corresponding to temperature.

13. The sensor device according to claim 7, wherein a well potential and a source potential of the sensor FET are short-circuited, and a well potential and a source potential of the reference FET are short-circuited.

14. The sensor device according to claim 13, wherein the source potential of the sensor FET, which is short-circuited with the well potential, is output to the sensor signal output terminal, and the source potential of the reference FET, which is short-circuited with the well potential, is output to the reference signal output terminal.

15. The sensor device according to claim 7, wherein the semiconductor region is a P-type semiconductor region, the first and second wells are formed as N-type semiconductor regions, and the sensor FET and the reference FET are P-type FETs.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0042] FIG. 1 A graphical representation of tolerance comparison data of hydrogen sensors to cyclic siloxane.

[0043] FIG. 2A A cross-sectional view of a reference FET.

[0044] FIG. 2B A cross-sectional view of a sensor FET.

[0045] FIG. 2C A graphical representation showing electrical characteristics of a FET-type hydrogen sensor.

[0046] FIG. 3 A cross-sectional view showing a problem of a conventional N-channel FET-type hydrogen sensor device.

[0047] FIG. 4 A schematic view showing a problem of a conventional N-channel FET-type hydrogen sensor system.

[0048] FIG. 5 Across-sectional view of a P-channel FET-type hydrogen sensor device.

[0049] FIG. 6 A schematic view of a P-channel FET-type hydrogen sensor system.

[0050] FIG. 7A A graphical representation showing a hydrogen response example of a P-channel FET-type hydrogen sensor.

[0051] FIG. 7B A graphical representation showing an output characteristics example of the P-channel FET-type hydrogen sensor.

[0052] FIG. 8A A graphical representation showing an example of the substrate effect.

[0053] FIG. 8B A graphical representation showing the effect of eliminating the substrate effect.

[0054] FIG. 9 A graphical representation showing an example of the effect of reducing the 1/f noise.

[0055] FIG. 10 A graphical representation showing a comparison of output characteristics between an N-channel FET-type hydrogen sensor and a P-channel FET-type hydrogen sensor.

[0056] FIG. 11 A block diagram of a second example of a P-channel FET-type hydrogen sensor chip.

[0057] FIG. 12 Across-sectional view of a first example of a P-channel FET-type hydrogen sensor system.

[0058] FIG. 13 A block diagram of a second example of a P-channel FET-type hydrogen sensor system.

[0059] FIG. 14 A cross-sectional view of a first example in which a temperature meter using a PN junction is mounted.

[0060] FIG. 15 A block diagram of one example of a hydrogen sensor system using a sensor chip of FIG. 13.

[0061] FIG. 16 A cross-sectional view of a first example in which a temperature meter using a metal interconnection resistance is mounted.

[0062] FIG. 17 A cross-sectional view of a first example in which a temperature meter using a diffusion layer resistance is mounted.

[0063] FIG. 18 A block diagram of one example of a hydrogen sensor system using a sensor chip of FIGS. 15 and 16.

[0064] FIG. 19 A cross-sectional view of a third example of a P-channel FET-type hydrogen sensor chip.

[0065] FIG. 20 A cross-sectional view of a fourth example of a P-channel FET-type hydrogen sensor chip.

[0066] FIG. 21 A cross-sectional view of a first example of an N-channel FET-type hydrogen sensor chip.

[0067] FIG. 22 A cross-sectional view of a second example of an N-channel FET-type hydrogen sensor chip.

[0068] FIG. 23 A cross-sectional view of a third example of an N-channel FET-type hydrogen sensor chip.

[0069] FIG. 24A A cross-sectional view of a sensor chip, including an interconnection layer and a protective layer.

[0070] FIG. 24B Across-sectional view of a reference chip, including an interconnection layer and a protective layer.

DESCRIPTION OF EMBODIMENTS

Examples

[0071] Hereinafter, embodiments of the invention will be described in detail based on the drawings. However, the invention should not be interpreted as being limited to the details described in the embodiments shown below. Those skilled in the art will readily understand that the specific configuration may be modified within the scope not departing from the idea or spirit of the invention. In all of the drawings for describing the embodiments, the same members are denoted in principle by the same reference numerals and signs, and a repetitive description thereof may be omitted.

[0072] The terms “first”, “second”, “third”, and the like in the description and the like are used to differentiate components from one another and do not necessarily limit the number or order of the components. Moreover, the numbers for differentiating the component are used for each context, and the number used in one context does not necessarily represent the same configuration in another context. Moreover, a component differentiated by a certain number is not prevented from serving also the function of a component differentiated by another number.

[0073] The position, size, shape, range, and the like of each configuration shown in the drawings and the like may not represent actual position, size, shape, range, and the like for facilitating the understanding of the invention. For this reason, the invention is not necessarily limited to the position, size, shape, range, and the like disclosed in the drawings and the like.

[0074] A component expressed in a singular form includes components in a plural form unless otherwise specified in a context.

[0075] A cross-sectional view of a sensor chip shown in FIG. 5 shows a first example of the present application. A sensor FET (PCHSENSOR) formed of a P-channel FET on a P-type substrate (PSUB) and a reference FET (PCHREFERENCE) also formed of a P-channel FET are formed adjacent to each other. By forming the reference FET and the sensor FET having the same structure adjacent to each other, a manufacturing variation typified by lithography or an implantation concentration can be suppressed, and it is possible to reduce errors when obtaining the difference.

[0076] The first example is the same as the conventional configuration shown in FIG. 3 in that both the reference FET and the sensor FET include a catalytic gate (CATGATE) and that only the reference FET includes a blocking film (PASSI) to eliminate hydrogen sensitivity. The blocking film (PASSI) may be any film as long as it does not transmit a detection target, such as a stable oxide, for example silicon nitride or silicon oxide, or various kinds of organic films. That is, compared to the conventional configuration, the first example of the present application is different in that the sensor FET and the reference FET are configured of, not N-channel FETs, but P-channel FETs while using the same P-type substrate (PSUB).

[0077] N-wells (NWELL) where the respective P-channel FETs are formed are provided independently of each other. As a result of this, the two NWELLs are reversely biased when a feeding potential (SUB) of the P-type substrate (PSUB) is the ground potential, and therefore can be electrically isolated from each other.

[0078] For this reason, the N-well (NWELL) potential of the sensor FET and the potential of the N-well (NWELL) of the reference FET can be controlled independently. As a result, as shown in FIG. 5, a well terminal (BSEN) and a source terminal (SSEN) can be short-circuited in the sensor FET, and a well terminal (BREF) and a source terminal (SREF) can be short-circuited in the reference FET.

[0079] FIG. 6 shows one example of a sensor system using the sensor chip (SENSORCHIP) shown in FIG. 5. In this example, a sensor system (SENSORSYSTEM) is configured using the sensor chip (SENSORCHIP) and a detection circuit (DCTCIRCUIT) as different chips, and this sensor system is further connected to a higher level system (SYSTEM). However, the sensor chip and the detection circuit may be combined into one chip, and further, the higher level system may be included to be combined into one chip.

[0080] Operations of VTH detection circuits (VTHSEN), a reference voltage generating circuit (VGEN), and a correction operation circuit (CAL) are equivalent to those in the description of FIG. 4. However, the N-channel FET is used in FIG. 4, whereas the P-channel FET is used in FIG. 6; therefore, the source and the drain are interchanged. The sensor chip (SENSORCHIP) of FIG. 6 is different from the conventional example shown in FIG. 3 in that the well potential and the source potential are short-circuited in each of the P-channel sensor FET (PCHSENSOR) and the P-channel reference FET (PCHREFERENCE). Due to this, in the sensor system shown in FIG. 6, a threshold voltage Vth_sens of the reference FET and a threshold voltage Vth_ref of the sensor FET are described by Equations (2) below.

Vth_sens=Vth0+α.Math.Vth_sen(1/f)+ΔV

Vth_ref=Vth0+α.Math.Vth_ref(1/f)  [Math. 2]

[0081] Compared to Equations (1), Equations (2) are different in that the term of the substrate effect is absent and further that each of the 1/f noise components becomes small (α<1). The 1/f noise is known to be small in a P-channel FET, compared to an N-channel FET, and α in the third term on the right side can be expected to be approximately 0.5. For this reason, compared to the conventional configuration, the term of the substrate effect is zero and the 1/f noise component is reduced almost by half in the first example of the present application; therefore, a sensing target can be detected with high accuracy. Moreover, when FIG. 3 and FIG. 5 are compared to each other, there is little change in the cross-sectional structure; therefore, there is little difference in ease of manufacturability. That is, higher accuracy of the sensor system becomes possible without increasing manufacturing costs.

[0082] When a FET is used as a common electronic device, it is desirable to make the gate width large for obtaining a sufficient current because a P-channel FET has a small ON-current compared to an N-channel FET. That is, since the device size needs to be made large and the chip area becomes large, there is a concern that costs increase. However, when a FET is used as the sensor system shown in FIG. 6, which senses a target based on the difference between the threshold voltages of the reference FET and the sensor FET, a large drain current is not required. Therefore, the drawback of the P-channel FET incapable of taking a large ON-current does not become a problem.

[0083] FIG. 7 show output characteristics of a sensor FET formed of an actual P-channel FET. FIG. 7A shows hydrogen response characteristics of a sensor output VSEN. The vertical axis is the output (arbitrary unit) of the FET, while the horizontal axis is the time axis. It is seen that the introduction of hydrogen starts at the timing near several tens of seconds and, at the same time, the output rises. Moreover, the hydrogen introduction stops near 180 seconds, and, at the same time, the output is lowered. FIG. 7B shows the relationship between VSEN and the hydrogen concentration. A favorable hydrogen response was confirmed at concentrations from 100 ppm to 10000 ppm, and it is found that the P-channel sensor FET has almost the same performance as the N-channel sensor FET.

[0084] The influence of the substrate effect on threshold voltage sensing will be quantitatively described using FIG. 8.

[0085] FIG. 8A shows the relationship between a substrate voltage VBS and a component Vth_sens_body due to the substrate effect in a threshold voltage change in the sensor FET. The calculation was performed for the case in which an N-channel FET was used and the well potential was grounded without short-circuiting the well and the source. A simplified circuit diagram is as shown in the inset of FIG. 8A, where G is a gate, D is a drain, and S is a source. A constant current source (ICONS) is inserted between the source and the ground potential to realize a constant drain current as shown in FIG. 2C. (VDD) is a power source potential, and (VG) is a gate potential. Moreover, (VSEN) is a sensor output. The calculation was performed at temperatures of 230K, 300K, and 400K. These respectively correspond to −40° C., a room temperature, and approximately 130° C., and cover an operating temperature range required for vehicle applications.

[0086] Since the potentials of the source and the well are different from each other, the sensor output (VSEN) and Vth_sens_body increase with an increase in the constant current source (ICONS). VBS is approximately −1.85 V when the constant current source (ICONS) is set to a magnitude required for sensing, and the sensor output (VSEN) is approximately 1.85 V because the well is grounded. This state is defined as a state when a sensing target is at 0%. When the sensing target is present at 3%, the sensor output is 1.0 V, which means that VBS is −2.85V. In the reference FET, since the output does not change even if the sensing target is present, VBS remains at −1.85 V. Therefore, a difference of 1.0 V occurs in VBS between the sensor FET and the reference FET. Due to this, a difference Δ occurring between the threshold voltage of the sensor FET and the threshold voltage of the reference FET is 27 mV. Since an error of 27 mV occurs with respect to the 3% sensing target, a measurement error of 2.7% occurs.

[0087] FIG. 8B was obtained by plotting concentration detection relative errors of the detection target due to the substrate effect shown in FIG. 8A against the temperature. Normalization was performed with relative errors at a room temperature. It is meant that when the detection target is present at a concentration of 3%, a relative error of −3% is superimposed due to the substrate effect in sensing the 3% detection target at −40° C. On the other hand, a relative error of +4% is superimposed due to the substrate effect in sensing the 3% detection target at 130° C. It should be noted that since there is a temperature dependence in the error to be superimposed due to the substrate effect as described above, temperature calibration is required, to correct this, as an adjustment before the shipment of the sensor. This may be a factor in the increase of sensor costs. A Vth variation Vth_body due to the above substrate effect is described as Equations (3) below.

[00002]$\begin{array}{cc}\mathrm{Vth\_body}=\gamma \left(\sqrt{{\phi }_F-\mathrm{VBS}}-\sqrt{{\phi }_F}\right).Math..Math.{\phi }_F=2.Math.\frac{k_B.Math.T}{q}.Math.\ln \left(\frac{N_A}{\mathrm{Ni}}\right).Math..Math.\gamma =\frac{\sqrt{2.Math..Math.\mathrm{.Math.}.Math..Math.q.Math..Math.N_A}}{\mathrm{Cox}}& \left[\mathrm{Math}..Math.3\right]\end{array}$

[0088] In the equations, kb is the Boltzmann constant, T is the temperature, and Ni is the intrinsic carrier density. Since the impurity density NA has a temperature dependence, the Vth_body changes depending on the temperature.

[0089] In the example of the present application shown in FIGS. 5 and 6, Vth_sens_body=0 V because VBS=0 V, so that the relative error described above does not essentially occur. Therefore, the relative error depending on the temperature is zero as shown in FIG. 8B, extra time and effort for the adjustment can be saved, and an inexpensive and highly accurate sensor can be provided. The advantage due to the removal of the substrate effect by the example of the present application has been described so far. Next, the effect of reducing the 1/f noise will be described using FIG. 9.

[0090] FIG. 9 shows a comparison of the 1/f noises, calculated using a standard N-channel FET model TypN and a standard P-channel FET model TypP provided in a certain semiconductor manufacturing process FAB-A, between a P-channel FET and an N-channel FET. For calculation, Equation (4) below, which is the 1/f noise calculation equation in BSIM3, was used.

[00003]$\begin{array}{cc}\frac{v_n^2}{\Delta .Math..Math.f}=\frac{\mathrm{KF}}{C_{\mathrm{ox}}.Math.\mathrm{LWf}}& \left[\mathrm{Math}..Math.4\right]\end{array}$

[0091] In the equation, vn is the gate input-referred noise, Δf is the band width, KF is the 1/f noise parameter, L is the gate length of the FET, W is the gate width of the FET, and f is the measured frequency. When the 6sigma noise is calculated, the noise level in FAB-A is low by approximately two orders of magnitude in both the N-channel and the P-channel, compared to the output, when the detection target is present at 10 ppm. However, when a production line in which KF>1E-23 is used, the magnitude of the 1/f noise is approximately the same as the signal output of the detection target 10 ppm and is a non-negligible magnitude.

[0092] In this case, since the 1/f noise in the P-channel FET has a magnitude equal to or less than ½ that of the N-channel FET, the P-channel type is advantageous for achieving higher accuracy compared to the N-channel type. The 1/f noise is a random noise as described above and therefore cannot be removed by the difference between the reference FET and the sensor FET. Therefore, it is desirable to make the 1/f noise as low as possible at a sensor chip level. Moreover, the 1/f noise increases as the measurement time is longer; therefore, it is also possible to improve stability or reliability for long-term operation by configuring the sensor FET and the reference FET using P-channel FETs.

[0093] Next, features specific to a P-channel FET will be described using FIG. 10. FIG. 10 shows a comparison of behavior when a detection target gas is sensed (Gas detecting) and behavior when the ambient temperature rises (Temperature rising) between a P-channel FET (PCH) and an N-channel FET (NCH). As the temperature range, it is assumed that the temperature is raised or lowered within, for example, the range in which the device is operable.

[0094] First, the behavior of the sensor FET when the detection target gas is sensed will be described. The dotted lines in the drawing show IDS-VGS characteristics when the gas is not present, and the solid lines show IDS-VGS characteristics when the gas is present. A threshold voltage VTH decreases in a detection target gas atmosphere in the N-channel sensor FET, and conversely increases in the P-channel sensor FET. However, the decrease in VTH in the P-channel sensor FET means that a gate-source voltage VGS required for obtaining the same drain current IDS decreases.

[0095] On the other hand, when the ambient temperature rises, VTH decreases, compared to that before temperature rise, in the N-channel FET, and VTH decreases also in the P-channel FET. The dotted line shows the IDS-VGS characteristics before temperature rise, and the solid line shows the IDS-VGS characteristics after temperature rise.

[0096] The directions of changes in VTH at the time of detection of the detection target gas and at the time of temperature rise are the same in the N-channel sensor FET, while the directions are opposite in the P-channel sensor FET. When the detection target gas is generated with temperature rise, the direction of output is opposite in the P-channel sensor FET; therefore, a VTH change due to the detection of the detection target gas and a VTH change due to temperature rise can be distinctly separated. On the other hand, the VTH changes cannot be separated in the N-channel sensor FET. In applications in which the generation of a detection target gas is accompanied by temperature rise, such as a FCV or a nuclear power plant, the P-channel sensor FET is advantageous over the N-channel in the sense that the possibility of erroneous detection can be reduced. Conversely, it can be said that when the generation of the detection target gas is accompanied by temperature drop, the N-channel sensor FET is more suitable than the P-channel.

[0097] The above described is the advantageous effect obtained by configuring the sensor FET and the reference FET using P-channel FETs.

[0098] FIG. 11 describes one example of a specific configuration of the VTH detection circuit (VTHSENSE) in the sensor system (SENSORSYSTEM) shown in FIG. 6. The output of a drain-source current generating circuit (IDSGEN) that generates a constant drain current is connected to a source potential (VSSEN) for a sensor FET (SENSOR). A source voltage buffer (SBUF) receives the source potential (VSSEN) as an input and outputs the same voltage as the input to a sensor FET device output (VSEN). Due to this, even if the load of the sensor FET device output (VSEN) is large, the voltage level of the source potential (VSSEN) can be transmitted to the operation circuit (CAL).

[0099] A drain-source voltage generating circuit (VDSGEN) receives, as inputs, a drain-source voltage (VDSSEN) for sensor FET generated by the voltage generating circuit (VGEN) and the sensor FET device output (VSEN), and outputs (VDS0). The voltage (VDS0) has a magnitude obtained by adding together the difference voltage between the drain-source voltage (VDSSEN) for sensor FET and the ground based on the sensor FET device output (VSEN), and the sensor FET device output (VSEN). That is, VDS0=VSEN+VDSSEN.

[0100] Since the sensor FET device output (VSEN) is equal to the source potential of the sensor FET, the source-drain voltage of the sensor FET is maintained by the drain-source voltage generating circuit (VDSGEN) at the constant drain-source voltage (VDSSEN) for sensor FET. A drain voltage buffer (DBUF) outputs the voltage (VDS0) to a drain potential (VDSEN) for sensor FET. Due to this, there is the advantage that driving is possible even when a large load is connected to the drain potential (VDSEN) for sensor FET. Even in the situation where the VTH detection circuit (VTHSENSE) and a P-type FET sensor chip (PCHSENSORCHIP) are connected through a long cable, the drain-source voltage of the sensor FET is maintained at (VDS0) by the drain voltage buffer (DBUF). The VTH detection circuit (VTHSENSE) on the reference FET (REFERENCE) is also basically similar to that on the sensor FET side. It is sufficient that the operational amplifier in FIG. 11 is a commercially available operational amplifier having general characteristics.

[0101] A second example will be described below.

[0102] FIG. 12 shows the second example of a sensor chip. The second example is the same as the first example shown in FIG. 5 in that the P-channel sensor FET and the P-channel reference FET are formed on the P-type substrate (PSUB); however, the second example is different in that the gate of the reference FET is configured of a gate (GATE) that does not have a catalytic action on a detection target. In the configuration, a failure in which the reference FET has sensitivity to the detection target due to the degradation of the blocking film (PASSI) shown in FIG. 5 can be essentially avoided. However, the film formations of the gate (GATE) not having the catalytic action and the catalytic gate electrode (CATGATE) need to be separately performed, so that film forming process costs and the number of masks increase.

[0103] FIG. 13 shows a second example of a sensor system. Compared to the first example shown in FIG. 6, the second example is different in that the number of the VTH sensing circuits (VTHSENSE) is reduced to one and that one VTH sensing circuit (VTHSENSE) is shared by the sensor FET and the reference FET through a switch SW. A switch control signal (SWCTRL) is generated by the correction operation circuit (CAL). By employing the configuration, compared to the case in which the VTH sensing circuits (VTHSENSE) are individually provided in the sensor FET and the reference FET, errors caused by a circuit variation can be reduced, and further, costs are reduced because the circuit configuration is simple. Since the sensor FET output and the reference signal output are alternately switched in a time-division manner, the simultaneity of measurement is lost. However, this disadvantage is eliminated by performing switching sufficiently faster than a gas concentration change time constant. Specifically, measurement accuracy is not affected if the switching is performed at a rate of 1 Hz or more.

[0104] FIG. 14 shows a third example of a sensor chip. The third example has a configuration in which a PN junction temperature meter (TEMPMETER) is added to the first example shown in FIG. 5. The PN junction is formed on the P-type substrate (PSUB), which is the same as that of the P-channel sensor FET and the P-channel reference FET. An anode terminal (APN) is connected to a P-diffusion region (P+), and a cathode terminal (CPN) is connected to an N-diffusion region (N+). The respective wells (NWELL) of the sensor FET, the reference FET, and the PN junction are electrically isolated from each other by setting the substrate potential (SUB) to the ground potential.

[0105] Although the gate of the reference FET in FIG. 14 is the catalytic gate electrode (CATGATE), the gate may be the gate (GATE) not having a catalytic action as shown in FIG. 12. That is, providing the PN junction temperature meter on the sensor chip and the configuration of the reference FET have no relation to each other.

[0106] FIG. 15 shows a third sensor system example including the sensor chip of FIG. 14. Compared to FIG. 6, the example is different in that the temperature meter (TEMPMETER) configured of the PN junction is included on the sensor chip and that a circuit block that controls this temperature meter (TEMPMETER) is added.

[0107] A current to be supplied to the temperature meter (TEMPMETER) is generated in a current source (IDIODEGEN). A voltage (VDIODE) for properly controlling the temperature meter (TEMPMETER) is generated in the reference voltage generating circuit (VGEN). The temperature of the sensor chip is obtained by the operation circuit (CAL) using an anode potential (VF) of the temperature meter (TEMPMETER). In the operation circuit (CAL), control for keeping the chip temperature constant or a sensitivity correction operation of the sensor output is carried out using obtained chip temperature information. Since a FET-type gas sensor obtains an output due to a detection target gas being occluded by a catalytic metal, sensitivity changes due to the chip temperature. Therefore, it is desirable to provide the temperature meter on the chip and perform a sensitivity correction, for ensuring reliability in applications in which the ambient temperature changes.

[0108] FIG. 16 shows a fourth example of a sensor chip. Compared to the third example shown in FIG. 14, the temperature meter (TEMPMETER) is configured using an interconnection resistance. FIG. 16 shows a certain cross-section of the entire interconnection resistance, and actually, it is assumed that the interconnection with a required length is formed on the chip. One end of the interconnection is extracted as an RH terminal (RH), and the other end is extracted as an RL terminal (RL). Since a metal interconnection resistance is a function of temperature, information of the chip temperature can be obtained by measuring the resistance value. The interconnection temperature meter can also be utilized as an electrothermal heater that adjusts the chip temperature. In this case, the RH terminal (RH) and the RL terminal (RL) also serve as a connection terminal and a resistance measurement terminal of a heater power source. There is also a method in which the RH terminal (RH) is separately prepared, such as RH1 and RH2, and the RL terminal (RL) is separately prepared, such as RL1 and RL2, because 4-terminal measurement is desirable for measuring the resistance value with good accuracy. As described in the description of FIG. 14, the gate of the reference FET may be replaced by the non-catalytic gate (GATE), and the sensing target blocking film (PASSI) may be removed. That is, the case in which the interconnection resistance temperature meter is applied to the second example of the sensor chip shown in FIG. 12 is also included in the scope of the present application.

[0109] FIG. 17 shows a fifth example of a sensor chip. Compared to the fourth example shown in FIG. 16, the fifth example is different in that the resistance temperature meter (TEMPMETER) is formed of a diffusion layer resistance. Compared to the interconnection resistance temperature meter, the diffusion layer resistance temperature meter has the advantage of high stability. Moreover, since it is easy to achieve a higher resistance, the diffusion layer resistance temperature meter conceivably has advantages such as being capable of increasing heat generating efficiency when utilized as an electrothermal heater. Moreover, because of a configuration in which the interconnection is buried in the P-type substrate (PSUB), thermal efficiency when the diffusion layer resistance temperature meter is utilized as a heater can be improved compared to the interconnection resistance temperature meter. When the diffusion layer resistance temperature meter is utilized as an electrothermal heater, the RH terminal (RH) and the RL terminal (RL) also serve as a connection terminal and a resistance measurement terminal of a heater power source. There is also a method in which the RH terminal (RH) is separately prepared, such as RH1 and RH2, and the RL terminal (RL) is separately prepared, such as RL1 and RL2, because 4-terminal measurement is desirable for measuring the resistance value with good accuracy. Since the diffusion layer resistance temperature meter can be made simultaneously in the diffusion layer manufacturing step, the diffusion layer resistance temperature meter is preferable in that an increase in process costs can be suppressed. As described in the description of FIG. 14, the gate of the reference FET may be replaced by the non-catalytic gate (GATE), and the sensing target blocking film (PASSI) may be removed. That is, the case in which the interconnection resistance temperature meter is applied to the second example of the sensor chip shown in FIG. 12 is also included in the scope of the present application.

[0110] FIG. 18 shows a fourth sensor system example of a sensor system using the sensor chip shown in FIGS. 16 and 17. Compared to FIG. 15, the example is different in that the temperature meter (TEMPMETER) is configured of a resistance. A current source (IRESGEN) is a circuit block that generates a current for controlling the temperature meter (TEMPMETER). A voltage (VRES) for controlling the resistance temperature meter is generated in the reference voltage generating circuit (VGEN). A resistance temperature meter output (VR) is input to the operation circuit (CAL). As described in the description of FIG. 15, higher reliability and higher stability can be achieved by performing the control of the chip temperature and a correction operation of the sensor output using the resistance temperature meter output (VR) including the chip temperature information.

[0111] FIG. 19 shows a sixth example of a sensor chip. In the case of using an N-type substrate (NSUB), a deep P-well (DPWELL) is provided on the N-type substrate (NSUB), and further, a P-channel sensor FET and a P-channel reference FET are formed on the deep P-well (DPWELL). Although process costs to constitute the deep P-well (DPWELL) increase, the sixth example is useful in applications in which the N-type substrate (NSUB) has to be used. In this case, it should be noted that the substrate potential (SUB) needs to be set, not to the ground, but to a high potential.

[0112] FIG. 20 shows a seventh example of a sensor chip, in which the P-channel sensor FET and the P-channel reference FET are configured on the N-type substrate (NSUB) without the deep wells. For isolating the well potential of the sensor FET and the well potential of the reference FET from each other, a trench-type device isolation (STI) is provided therebetween. Due to this, since the impedance between the well of the sensor FET and the well of the reference FET increases, the well potentials can be controlled independently of each other; as a result, a configuration in which the substrate effect is eliminated by short-circuiting the well and the source can be realized.

[0113] Although not specified in FIGS. 19 and 20, the case in which the reference FET includes the non-catalytic gate (GATE) as shown in FIG. 12, the case in which the PN junction temperature meter (TEMPMETER) shown in FIG. 14 is included, the case in which the interconnection resistance temperature meter (TEMPMETER) shown in FIG. 16 is included, and the case in which the diffusion layer resistance (TEMPMETER) shown in FIG. 17 is included are also included as similar derivative examples in the scope of the present application.

[0114] Although the effect of reducing the 1/f noise cannot be expected, the configuration in which the substrate effect is eliminated by short-circuiting the well and the source can be realized also in the case of using an N-channel FET.

[0115] FIG. 21 shows an eighth example in which, with respect to the first example shown in FIG. 5, the P-type substrate is replaced by the N-type substrate (NSUB) and the P-channel FET is replaced by an N-channel FET.

[0116] FIG. 22 shows a ninth example in which, with respect to the sixth example shown in FIG. 19, the N-type substrate is replaced by the P-type substrate (PSUB), the deep P-well is replaced by the deep N-well (DNWELL), and the P-channel FET is replaced by an N-channel FET.

[0117] FIG. 23 shows a tenth example in which, with respect to the seventh example shown in FIG. 20, the N-type substrate is replaced by the P-type substrate (PSUB) and the P-channel FET is replaced by an N-channel FET.

[0118] FIG. 24 each show one example of a cross-sectional structural drawing when a semiconductor device is configured of the P-channel FET shown in FIG. 5. The N-well (NWELL) is formed on the P-type substrate (PSUB), and the P-type FET is formed in the N-well (NWELL). Both the sensor FET (PCHSENSOR) and the reference FET (PCHREFERENCE) include a catalytic gate electrode (SCATGATE, RCATGATE); however, the catalytic gate electrode (SCATGATE) of the sensor FET is exposed in a through hole formed in the blocking film (PASSI), whereas the catalytic gate electrode (RCATGATE) of the reference FET is covered by the blocking film (PASSI). Under the catalytic gate electrode, a gate oxide film (OXIDE) is present. Moreover, there are a device isolation film (OX1) and an interlayer film (OX2).

[0119] The drain terminal (DREF) of the reference FET is connected to a drain pad (DRAINPAD), the source terminal (SREF) of the reference FET is connected to a source pad (SREFPAD), the well terminal (BREF) of the reference FET is connected to a body pad (BREFPAD), the catalytic gate electrode (RCATGATE) is connected to a gate pad (RCATGATEPAD), a substrate (SUB) is connected to a substrate potential pad (SUBPAD), and thus, signals can be input or output.

[0120] The drain terminal (DSEN) of the sense FET is connected to a drain pad (DRAINPAD), the source terminal (SSEN) of the reference FET is connected to a source pad (SSENPAD), the well terminal (BSEN) of the reference FET is connected to a bodypad (BSENPAD), the catalytic gate electrode (SCATGATE) is connected to a gate pad (SCATGATEPAD), and thus, signals can be input or output.

[0121] The sensor FET (PCHSENSOR) and the reference FET (PCHREFERENCE) are separately shown in FIGS. 24A and 24B for the purpose of comparative description; actually, however, the sensor FET (PCHSENSOR) and the reference FET (PCHREFERENCE) are formed on the common P-type substrate (PSUB).

[0122] Although not specified also in the eighth to tenth examples, the pattern in which the gate of the reference FET is configured of the non-catalytic gate (GATE), the case in which the PN junction temperature meter (TEMPMETER) shown in FIG. 14 is included, the case in which the interconnection resistance temperature meter (TEMPMETER) shown in FIG. 16 is included, and the case in which the diffusion layer resistance (TEMPMETER) shown in FIG. 17 is included are also included as similar derivative examples in the scope of the present application. That is, the invention is not limited to the embodiments described above but includes various modified examples. For example, a portion of the configuration of a certain example can be replaced by the configuration of another example, and moreover, the configuration of a certain example can be added to the configuration of another example. Moreover, as to a portion of the configuration of each example, the addition, removal, or replacement of the configuration of another example is possible.

[0123] The functions of the “source” and “drain” of a transistor may be interchanged when a transistor having a different polarity is employed or when the direction of a current changes in circuit operation. For this reason, in the description, the terms “source” and “drain” can be interchanged and used in some cases.

[0124] The terms “electrode” and “interconnection” in the description and the like do not functionally limit these components. For example, the “electrode” may be used as a portion of the “interconnection”, and vice versa. Further, the terms “electrode” and “interconnection” include the case in which a plurality of “electrodes” or “interconnections” are integrally formed.

INDUSTRIAL APPLICABILITY

[0125] The FET-type sensor of the invention is a technique that can also be applied to a hydrogen concentration meter in a hydrogen infrastructure such as a fuel cell vehicle or a hydrogen station, as well as in various types of plants or a nuclear power plant.

REFERENCE SIGNS LIST

[0126] FET field-effect transistor [0127] FCV fuel cell vehicle [0128] VDS drain-source voltage [0129] VG gate potential based on ground potential [0130] VREF reference FET device output [0131] PASSI detection target blocking film [0132] OXIDE gate oxide film [0133] CATGATE catalytic metal gate [0134] DREF drain terminal of reference FET [0135] SREF source terminal of reference FET [0136] BREF well terminal of reference FET [0137] IDS drain-source current [0138] WELL well [0139] SUB semiconductor substrate [0140] PSUB P-type semiconductor substrate [0141] VSEN sensor FET device output [0142] DIPOLE hydrogen dipole [0143] DSEN drain terminal of sensor FET [0144] SSEN source terminal of sensor FET [0145] BSEN well terminal of sensor FET [0146] DCTCIRCUIT detection circuit [0147] VTHSENSE VTH detection circuit [0148] VDSEN drain potential for sensor FET [0149] VSSEN source potential for sensor FET [0150] VDSSEN drain-source voltage for sensor FET [0151] VGEN reference voltage generating circuit [0152] VDSREF drain-source voltage for reference FET [0153] VDREF drain potential for reference FET [0154] VSREF source potential for reference FET [0155] CAL correction operation circuit [0156] VDD High-side power source potential [0157] VBS substrate voltage [0158] VGS gate-source voltage [0159] VTH threshold voltage [0160] GATE non-catalytic gate [0161] IDSGEN drain-source current generating circuit [0162] SBUF source voltage buffer [0163] DBUF drain voltage buffer [0164] VDSGEN drain-source voltage generating circuit [0165] SW changeover switch [0166] SWCTRL changeover-switch control line [0167] APN anode terminal of PN junction [0168] CPN cathode terminal of PN junction [0169] TEMPMETER temperature meter [0170] VDIODE control voltage for PN junction [0171] IDIODEGEN control current generating circuit for PN junction [0172] VF PN junction temperature meter output [0173] RH HIGH terminal for resistance temperature meter [0174] RL LOW terminal for resistance temperature meter [0175] VRES control voltage for resistance temperature meter [0176] IRESGEN control current generating circuit for resistance temperature meter [0177] DPWELL deep P-well [0178] DNWELL deep N-well [0179] STI trench-type device isolation