SEMICONDUCTOR DEVICE

Abstract

On a front surface of an n.sup.+-type SiC substrate becoming a drain region, an n.sup.−-type drift layer, a p-type base layer, and an n.sup.+-type source layer are sequentially formed by epitaxial growth. In the n.sup.+-type source layer, the p.sup.+-type contact region is selectively provided. A trench is provided penetrating the n.sup.+-type source layer and the p-type base layer in the depth direction and reaching the n.sup.−-type drift layer. In the trench, a gate electrode is provided via a gate insulating film. A width between adjacent trenches is, for example, 1 μm or less. A depth of the trench is, for example, 1 μm or less. The width is narrow whereby substantially the entire p-type base layer forms a channel. A cell includes a FinFET structure in which one channel is sandwiched between MOS gates on both side. Thus, ON resistance may be reduced and decreased reliability may be prevented.

Claims

1. A semiconductor device comprising: a semiconductor substrate of a first conductivity type and including a wide bandgap semiconductor material having a bandgap wider than that of silicon; a first semiconductor layer of the first conductivity type provided on a front surface of the semiconductor substrate, the first semiconductor layer including the wide bandgap semiconductor material and having an impurity concentration lower than that of the semiconductor substrate, the first semiconductor layer having a first side and a second side; a second semiconductor layer of a second conductivity type provided on the first side of the first semiconductor layer opposite the second side facing the semiconductor substrate, the second semiconductor layer including the wide bandgap semiconductor material and having a first side and a second side; a third semiconductor layer of the first conductivity type provided on the first side of the second semiconductor layer opposite the second side facing the semiconductor substrate, the third semiconductor layer including the wide bandgap semiconductor material; a second-conductivity-type semiconductor region provided selectively in the third semiconductor layer, penetrating the third semiconductor layer in a depth direction and reaching the second semiconductor layer, the second-conductivity-type semiconductor region having an impurity concentration higher than that of the second semiconductor layer; a trench penetrating the third semiconductor layer and the second semiconductor layer and reaching the first semiconductor layer; a gate insulating film provided on walls of the trench; a gate electrode provided in the trench and sandwiched, in the trench, by the gate insulating film; a first electrode provided in contact with the third semiconductor layer and the second-conductivity-type semiconductor region; and a second electrode provided in contact with a rear surface of the semiconductor substrate, wherein a width between the trench and an adjacent trench is 1 μm or less, and a depth of the trench is 1 μm or less, and the semiconductor device has a breakdown voltage class of 1200V or higher.

2. The semiconductor device according to claim 1, wherein the trench is arranged in planar layout having a striped shape parallel to the front surface of the semiconductor substrate.

3. The semiconductor device according to claim 1, wherein the trench is arranged in a planar layout having a lattice shape parallel to the front surface of the semiconductor substrate.

4. The semiconductor device according to claim 1, comprising a groove provided at a predetermined depth from surfaces on respective first sides of the third semiconductor layer and the second-conductivity-type semiconductor region, the respective first sides being opposite respective second sides of the third semiconductor layer and the second-conductivity-type semiconductor region facing the semiconductor substrate, wherein the first electrode is provided to be in contact with the third semiconductor layer and the second-conductivity-type semiconductor region at an inner wall of the groove.

5. The semiconductor device according to claim 1, wherein silicon carbide is used as the wide bandgap semiconductor material.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] FIG. 1 is a perspective view of a structure of a semiconductor device according to a first embodiment;

[0021] FIG. 2 is a perspective view of a structure of the semiconductor device according to a second embodiment;

[0022] FIG. 3 is a plan view of a planar layout along a cutting line A-A′ in FIG. 2;

[0023] FIG. 4 is a perspective view of a structure of the semiconductor device according to a third embodiment;

[0024] FIG. 5 is a plan view of a cross-section along a cutting line B-B′ in FIG. 4;

[0025] FIG. 6 is a plan view of a cross-section along a cutting line C-C′ in FIG. 4;

[0026] FIG. 7 is a characteristics diagram of current characteristics of a semiconductor device according to an example;

[0027] FIG. 8 is a characteristics diagram of current-voltage characteristics of the semiconductor device according to the example; and

[0028] FIG. 9 is a perspective view of a structure of an active region of a conventional semiconductor device.

DETAILED DESCRIPTION OF THE INVENTION

[0029] Embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present description and accompanying drawings, layers and regions prefixed with n or p mean that majority carriers are electrons or holes. Additionally, + or − appended to n or p means that the impurity concentration is higher or lower, respectively, than layers and regions without + or −. In the description of the embodiments below and the accompanying drawings, main portions that are identical will be given the same reference numerals and will not be repeatedly described. Further, in the present description, when Miller indices are described, “−” means a bar added to an index immediately after the “−”, and a negative index is expressed by prefixing “−” to the index.

[0030] The semiconductor device according to a first embodiment is a metal oxide semiconductor (MOS) semiconductor device configured using a wide bandgap semiconductor material. A structure of the semiconductor device according to the first embodiment will be described, taking as an example, a MOSFET using, for example, silicon carbide (SiC) as a semiconductor having a wider bandgap than silicon (Si) (wide bandgap semiconductor). While embodiments described below refer to SiC as a semiconductor having a wider bandgap than silicon, embodiments of the invention are not limited to SiC, but encompass any wide bandgap material having a bandgap wider than silicon, such as diamond, aluminum nitride, gallium nitride, and boron nitride. FIG. 1 is a perspective view of a structure of the semiconductor device according to the first embodiment. In FIG. 1, the active region alone is depicted and edge termination structure region surrounding a periphery of the active region is omitted from the drawing. The active region is a region in which current flows in an ON state. The edge termination structure region is a region that mitigates electric field on a base front surface side of the drift region and sustains the breakdown voltage.

[0031] The semiconductor device according to the first embodiment depicted in FIG. 1, is an n-channel type MOSFET using a silicon carbide semiconductor base (semiconductor chip). The silicon carbide semiconductor base, for example, is formed by sequentially forming by epitaxial growth on a front surface of an n.sup.+-type supporting substrate (hereinafter, n.sup.+-type SiC substrate) 1 including silicon carbide, an n.sup.−-type drift layer 2, a p-type base layer 3, and an n.sup.+-type source layer 4, each including silicon carbide. The n.sup.−-type drift layer 2, the p-type base layer 3, and the n.sup.+-type source layer 4 may be formed by ion implantation in place of epitaxial growth. The n.sup.+-type SiC substrate 1 functions as a drain region. In a surface layer on a base front surface (surface on the n.sup.+-type source layer 4 side) of the silicon carbide semiconductor base, a trench-gate-type MOS gate structure in which an insulated gate formed by a metal oxide semiconductor (MOS) gate 9 is selectively embedded in a U-shape penetrating the p-type base layer 3 and the n.sup.+-type source layer 4 in a depth direction z is provided.

[0032] The p-type base layer 3 and the n.sup.+-type source layer 4, for example, are deposited on the n.sup.−-type drift layer 2 only in the active region. A total thickness of the p-type base layer 3 and the n.sup.+-type source layer 4 is a dimension thinner than a depth of a trench 6 so that the n.sup.−-type drift layer 2 and a gate electrode 8 described hereinafter face each other across a gate insulating film 7 of a sidewall of the trench 6. This is because when the total thickness of the p-type base layer 3 and the n.sup.+-type source layer 4 is thin, surrounding of the channel occurs easily and when surrounding of the channel may occur, a thick dimension may be set. In the n.sup.+-type source layer 4, a p.sup.+-type contact region 5 is selectively provided. The p.sup.+-type contact region 5 penetrates the n.sup.+-type source layer 4 from the base front surface (surface of the n.sup.+-type source layer 4) in the depth direction z and reaches the p-type base layer 3. The p.sup.+-type contact region 5 may be arranged separately from the MOS gate 9 described hereinafter or may be in contact with the MOS gate 9. In FIG. 1, a case is depicted in which the p.sup.+-type contact region 5 is arranged separately from the MOS gate 9.

[0033] Further, the p.sup.+-type contact region 5 is arranged in a planar layout having a matrix shape in which p.sup.+-type contact regions 5 are arranged at a predetermined interval along a first direction x along which the MOS gate 9 extends in a striped shape and the p.sup.+-type contact regions 5 are adjacent to each other across the MOS gate 9 in a second direction y parallel to the base front surface and orthogonal to the first direction x. The trench 6 is provided penetrating the n.sup.+-type source layer 4 and the p-type base layer 3 to reach the n.sup.−-type drift layer 2 in the depth direction z. When the p.sup.+-type contact region 5 is in contact with the MOS gate 9, the trench 6 penetrates the n.sup.+-type source layer 4, the p-type base layer 3, and the p.sup.+-type contact region 5 in the depth direction z. The trench 6 is arranged in plural in a planar layout extending in a striped shape along the first direction x. A width w1 between adjacent trenches 6 (mesa portion) and a depth d of the trenches 6 are less than a minimum dimension achieving a predetermined current capacity material limit of silicon (for example, about less than 10 μm). In particular, the width w1 between adjacent trenches 6 is, for example, 1 μm or less, and the depth d of the trenches 6 is, for example, 1 μm or less.

[0034] In the trench 6, the gate insulating film 7 is provided along an inner wall of the trench 6 and on the gate insulating film 7, the gate electrode 8 is provided. An upper end (source-side end portion) of the gate electrode 8 need not reach a height position of the base front surface. In other words, in the trench 6, on the gate electrode 8, an interlayer insulating film 11 described hereinafter may be embedded. The trench 6, the gate insulating film 7, and the gate electrode 8 constitute the MOS gate 9. The p-type base layer 3, the n.sup.+-type source layer 4, and the p.sup.+-type contact region 5 provided between centers of adjacent trenches 6 and MOS gates 9 facing each other across these regions constitute one cell (functional unit of an element) 10 of the MOS gate structure. The width w1 between adjacent trenches 6 is narrow whereby a channel (n-type inversion layer) is formed substantially in the entire p-type base layer 3. Therefore, the cell 10 of the MOS gate structure is a so-called double gate structure in which one channel is sandwiched by MOS gates 9 from both sides (both sides in the second direction y). In other words, the cell 10 has a FinFET structure. FIG. 1 depicts a state in which plural cells 10 are arranged in parallel.

[0035] The interlayer insulating film 11 is provided so as to cover the gate electrode 8. In a contact hole 11a penetrating the interlayer insulating film 11 in the depth direction, the n.sup.+-type source layer 4 and the p.sup.+-type contact region 5 are exposed. The contact hole 11a, for example, is provided in a planar layout extending in a striped shape along the first direction x. A barrier metal 12 is provided on a surface of the interlayer insulating film 11 and along an inner wall of the contact hole 11a to be in contact with the n.sup.+-type source layer 4 and the p.sup.+-type contact region 5. The barrier metal 12 has a function of preventing diffusion of metal atoms from a front electrode 13 described hereinafter toward the silicon carbide semiconductor base and the interlayer insulating film 11 and a function of preventing regions that face each other across the barrier metal 12 from reacting with each other.

[0036] The barrier metal 12, for example, may be a 3-layered structure of a titanium (Ti) film, a titanium nitride (TiN) film, and a titanium film sequentially stacked. The barrier metal 12 functions as a source electrode. The front electrode 13 is provided on the barrier metal 12 so as to be embedded in the contact hole 11a. The front electrode 13 is electrically connected to the n.sup.+-type source layer 4 and the p.sup.+-type contact region 5 via the barrier metal 12 and functions as a source electrode together with the barrier metal 12. The front electrode 13, for example, may be formed using aluminum (Al) or aluminum including a rate of 1% silicon (Ai-Si).

[0037] The front electrode 13 and the barrier metal 12 are electrically insulated from the gate electrode 8 by the interlayer insulating film 11. In FIG. 1, to clearly depict planar layouts of the n.sup.+-type source layer 4, the p.sup.+-type contact region 5, and the MOS gate 9, a portion of the barrier metal 12 and a portion of the front electrode 13 in the front of the drawing are not depicted (similarly in FIG. 2). On the front electrode 13, a front electrode pad 14 is provided. Further, on the base front surface, a gate electrode pad (not depicted) is provided separately from the front electrode pad 14. On a base rear surface (rear surface of the n.sup.+-type SiC substrate 1), a rear electrode 15 functioning as a drain electrode is provided.

[0038] A method of manufacturing the semiconductor device according to the first embodiment will be described, taking as an example, a case in which, for example, an n-channel type MOSFET with a breakdown voltage class of 1200V is produced. First, for example, the n.sup.+-type SiC substrate 1 doped with nitrogen (N) and having an impurity concentration of about 2×10.sup.19/cm.sup.3 is prepared. The n.sup.+-type SiC substrate 1 may have a main surface that is, for example, a (000-1) face having an OFF angle of about 4 degrees in a <11-20> direction. Next, on the main surface of the n.sup.+-type SiC substrate 1, for example, silicon carbide doped with nitrogen and having an impurity concentration of 1.0×10.sup.16/cm.sup.3 is formed by epitaxial growth to have a thickness of 10 μm, becoming the n.sup.−-type drift layer 2. Next, on the n.sup.−-type drift layer 2 in the active region, for example, silicon carbide doped with aluminum and becoming the p-type base layer 3 is formed by epitaxial growth.

[0039] Next, on the p-type base layer 3 in the active region, for example, silicon carbide doped with nitrogen and becoming the n.sup.+-type source layer 4 is formed by epitaxial growth. By the processes up to here, the silicon carbide semiconductor base in which then.sup.−-type drift layer 2, the p-type base layer 3, and the n.sup.+-type source layer 4 are sequentially stacked on the front surface of the n.sup.+-type SiC substrate 1 is produced. In place of epitaxial growth, the n.sup.−-type drift layer 2, the p-type base layer 3, and the n.sup.+-type source layer 4 may be formed by ion implantation. Next, by photolithography and ion implantation, the p.sup.+-type contact region 5 is selectively formed in the n.sup.+-type source layer 4. Next, by heat treatment (annealing), the p.sup.+-type contact region 5 is activated. The heat treatment for activation, for example, may be performed at a temperature of about 1620 degrees C. for about 2 minutes.

[0040] Next, by photolithography and etching, the trench 6 is formed penetrating the n.sup.+-type source layer 4 and the p-type base layer 3 in the depth direction z to reach the n.sup.−-type drift layer 2. The width w1 between adjacent trenches 6 and the depth d of the trenches 6 is as described above. The sequence in which the p.sup.+-type contact region 5 and the trench 6 are formed may be interchanged. Next, the base front surface (surface on the n.sup.+-type source layer 4 side) and the inner wall of the trench 6 are thermally oxidized, forming along the inner wall of the trench 6 and the base front surface, the gate insulating film 7 having a thickness of, for example, about 50 nm to 100 nm. The thermal oxidation for forming the gate insulating film 7, for example, may be heat treatment performed in a mixed gas atmosphere including oxygen (O.sub.2) and nitrogen (N.sub.2) at a temperature of about 1000 to 1300 degrees C.

[0041] Next, on the base front surface, a poly-silicon (poly-Si) layer doped with, for example, phosphorus (P) or boron (B) is deposited (formed) so as to be embedded in the trench 6. Next, the poly-silicon layer is etched until the gate insulating film 7 on a substrate front surface is exposed and the poly-silicon layer is left inside the trench 6 to become the gate electrode 8. Next, the gate electrode 8 is used as a mask, and the gate insulating film 7 on the substrate front surface is removed. Next, for example, Phospho Silicate Glass (PSG) is formed to have a thickness of 1.0 μm and so as to cover the gate electrode 8 and become the interlayer insulating film 11. Next, the interlayer insulating film 11 is patterned and selectively removed, forming the contact hole 11a penetrating the interlayer insulating film 11 in the depth direction z, and exposing the n.sup.+-type source layer 4 and the p.sup.+-type contact region 5. Next, heat treatment (reflow) for planarizing the interlayer insulating film 11 is performed.

[0042] Next, for example, by sputtering, the barrier metal 12 is formed along the surface of the interlayer insulating film 11 and the inner wall of the contact hole 11a so as to be in contact with the n.sup.+-type source layer 4 and the p.sup.+-type contact region 5. Next, for example, after the front electrode 13 is formed on the barrier metal 12 by sputtering so as to be embedded in the contact hole 11a, the front electrode 13 and the barrier metal 12 are patterned. A thickness of the front electrode 13 may be, for example, 5 μm. Next, for example, by sputtering, a nickel (Ni) film is formed as the rear electrode 15 on the entire base rear surface (rear surface of the n.sup.+-type SiC substrate 1). For example, heat treatment at a temperature of about 970 degrees C. is performed, causing the n.sup.+-type SiC substrate 1 and the nickel film to react, forming a nickel silicide film, and thereby forming an ohmic contact (electrical contact potion) of the n.sup.+-type SiC substrate 1 and the rear electrode 15.

[0043] Next, for example, a metal layer is deposited on the front electrode 13 by sputtering and is patterned whereby the front electrode pad 14 and the gate electrode pad are formed. Next, for example, a protection film (not depicted) such as a passivation film including a polyimide is formed so as to cover the base front surface exposed in the edge termination structure region (not depicted). Next, for example, titanium, nickel, and gold (Au) films are sequentially formed by sputtering on a surface of a nickel film (a surface of a nickel silicide film by heat treatment conditions for forming an ohmic contact) as the rear electrode 15 whereby the n-channel type MOSFET depicted in FIG. 1 is completed.

[0044] As described above, according to the first embodiment, JFET resistance may be eliminated by configuring a trench gate structure, and the channel resistance may be reduced by reducing the trench depth and shortening the channel length. Further, in an ordinary semiconductor device using silicon, the trench depth based on the material limits of silicon is, for example, about 10 μm. However, in the present invention, a wide bandgap semiconductor material having a critical electric field strength that is 10 times or more than that of silicon is used. Therefore, according to the first embodiment, even when the characteristics of a wide bandgap semiconductor are taken advantage of, the trench depth is reduced to about 1/10 that of an ordinary semiconductor device that uses silicon and the channel length is shortened, a current capacity that is about the same as or greater than that of an ordinary semiconductor device that uses silicon may be obtained. Therefore, the ON resistance may be reduced while maintaining a current capacity that is about the same as or greater than that of an ordinary semiconductor device that uses silicon.

[0045] Further, according to the first embodiment, by employing a FinFET structure in which the width between adjacent trenches is reduced, at low gate-voltage operating area (operating region of a linear region near a boundary with the shutout region), the p-type base layer may be completely depleted. As a result, short channel effects may be suppressed whereby the flow of drain current becomes difficult in the low gate-voltage operating area. Further, after pinch off, in the region (saturation region) operating at a high voltage between the drain and source as well, the flow of drain current becomes difficult. Thus, drain current may be controlled by the gate voltage alone and decreases in the switching operation reliability may be prevented.

[0046] According to the first embodiment, by employing a FinFET structure, cell pitch may be reduced, enabling size reductions. Further, according to the first embodiment, by employing a FinFET structure, the channel impurity concentration may be lowered and channel resistance may be reduced.

[0047] Next, a structure of the semiconductor device according to a second embodiment will be described. FIG. 2 is a perspective view of a structure of the semiconductor device according to the second embodiment. FIG. 3 is a plan view of a planar layout along a cutting line A-A′ in FIG. 2. FIG. 3 depicts the planar layout at cutting line A-A′ transecting a gate electrode 28 in a direction parallel to the base front surface. The semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment in that MOS gates 29 are arranged in a planar layout of a lattice shape. In other words, trenches 26 are arranged in a planar layout of a lattice shape extending in a striped shaped along the first direction x and extending in a striped shape along the second direction y. In the trench 26, the gate electrode 28 is provided via a gate insulating film 27.

[0048] The p-type base layers 3 have a planar layout of a matrix shape in which the p-type base layers 3 are arranged so as to be in contact with the gate insulating film 27 between the trenches 26, and are arranged to be adjacent to each other across the MOS gates 29 in the first direction x and adjacent to each other across the MOS gates 29 in the second direction y. The n.sup.+-type source layer 4 is arranged on the p-type base layer 3. In other words, the n.sup.+-type source layers 4, similar to the p-type base layers 3, are arranged so as to be in contact with the gate insulating film 27 between the trenches 26. The n.sup.+-type source layers 4 have a planar layout of a matrix shape in which the n.sup.+-type source layers 4 are adjacent to each other across the MOS gates 29 in the first direction x and are adjacent to each other across the MOS gates 29 in the second direction y. The p.sup.+-type contact region 5 is arranged individually in each of the n.sup.+-type source layers 4 separated by the trenches 26.

[0049] The method of manufacturing according to the second embodiment may be performed by performing in the method of manufacturing according to the first embodiment, etching for forming the trenches 26 to have a planar layout of a lattice shape. In other words, an etching mask for forming the trenches 26 is patterned in a planar layout of a lattice shape and the etching mask is used as a mask to form the trenches 26. Processes other than the process of forming the trenches 26 in the method of manufacturing according to the second embodiment are similar to those of the first embodiment.

[0050] As described, according to the second embodiment, effects identical to those of the first embodiment may be obtained. Further, according to the second embodiment, by arranging the gate electrodes in a planar layout of a lattice shape, wiring resistance differences of the gate electrodes may be equalized in the chip. As a result, at the poly-silicon layer in which the gate resistance becomes large, even when the gate electrode is formed, wiring delay differences consequent to gate delay at a portion of the gate electrode separate from the gate electrode pad may be reduced. As a result, wiring delay times may be substantially stabilized whereby even in cases of transient operation states, stable element characteristics may be maintained.

[0051] Next, a structure of the semiconductor device according to a third embodiment will be described. FIG. 4 is a perspective view of the structure of the semiconductor device according to the third embodiment. In FIG. 4, to clearly depict planar layouts and cross-sectional views of the n.sup.+-type source layer 4, the p.sup.+-type contact region 5, the MOS gate 9, and a groove 31, a portion of a barrier metal 32 and a portion of a front electrode 33 in the front of the drawing are not depicted. FIG. 5 is a plan view of a cross-section along a cutting line B-B′ in FIG. 4. FIG. 6 is a plan view of a cross-section along a cutting line C-C′ in FIG. 4. The semiconductor device according to the third embodiment differs from the semiconductor device according to the first embodiment in that the groove 31 is provided at a portion of the silicon carbide semiconductor base exposed in the contact hole 11a whereby the area of ohmic contact of a source electrode (the barrier metal 32 and the front electrode 33) and the silicon carbide semiconductor base is increased.

[0052] In particular, as depicted in FIGS. 4, 5, and 6, the groove 31 is provided at the portion (i.e., the n.sup.+-type source layer 4 and the p.sup.+-type contact region 5) of the silicon carbide semiconductor base exposed in the contact hole 11a. The groove 31, for example, is arranged in a planar layout extending linearly along the first direction x. The groove 31 is provided to a depth not reaching the n.sup.−-type drift layer 2 and, for example, may be shallower or deeper than a depth of the n.sup.+-type source layer 4. A width w2 of the groove 31 along the second direction y is narrower than the width w1 between adjacent trenches 6 (w2<w1) and, for example, is about the same as a width of the contact hole 11a. In the groove 31, the front electrode 33 is embedded via the barrier metal 32. At an inner wall of the groove 31, the barrier metal 32 and the silicon carbide semiconductor base are in contact with each other, forming an ohmic contact.

[0053] The method of manufacturing according to the third embodiment may be performed by performing in the method of manufacturing according to the first embodiment, etching using the interlayer insulating film 11 as a mask to form the groove 31 in a portion of the silicon carbide semiconductor base exposed in the contact hole 11a, the etching being performed after the reflow of the interlayer insulating film 11 and before the formation of the barrier metal 32. Along the surface of the interlayer insulating film 11, the sidewall of the contact hole 11a, and an inner wall of the groove 31, the barrier metal 32 is formed to be in contact with the n.sup.+-type source layer 4 and the p.sup.+-type contact region 5. Thereafter, the front electrode 33 may be formed so as to be embedded in the contact hole 11a and the groove 31. In other words, other than adding a process of forming the groove 31, the method of manufacturing according to the third embodiment is similar to the method of manufacturing according to the first embodiment.

[0054] As described above, according to the third embodiment, effects identical to those of the first embodiment may be obtained. Further, according to the third embodiment, the area of the ohmic contact of the source electrode and the silicon carbide semiconductor base is increased, enabling contact resistance to be reduced and enabling the ON resistance to be further reduced. Therefore, even when the cell pitch is decreased and the chip size is reduced, the contact area may be maintained similar to that when the groove is not provided in the portion of the silicon carbide semiconductor base exposed in the contact hole, enabling the contact resistance to be prevented from becoming high. Thus, even when the cell pitch is narrow, the ON resistance may be maintained.

[0055] Static characteristics of the semiconductor device according to the present invention were verified. FIG. 7 is a characteristics diagram of current characteristics of a semiconductor device according to an example. In FIG. 7, point D represents the threshold voltage. FIG. 7 depicts results of simulation of drain current (current between the drain and source) Id characteristics when a gate voltage (voltage between the gate and source) Vgs applied to the described semiconductor device according to the first embodiment (hereinafter, EXAMPLE, refer to FIG. 1) is increased. For comparison, FIG. 7 further depicts the results of similarly simulating drain current Id characteristics of a conventional n-channel type MOSFET of a planar gate structure (hereinafter, conventional example, refer to FIG. 9). A channel length (width between the n.sup.+-type source region 105 and the n-type JFET region 107) L100 of the conventional example was set to be equal to a channel length (thickness of the p-type base layer 3) L1 of the EXAMPLE.

[0056] From the results depicted in FIG. 7, it was confirmed that in the conventional example, the drain current Id increased in proportion to the increase of the gate voltage Vgs. In a MOS gate of a planar gate structure such as the conventional example, to lower the ON resistance, the channel length L100 has to be shortened. By shortening the channel length L100, the amount of charge of the surface inversion layer of the second p-type base layer 104a decreases, recombination of electrons and holes becomes less likely to occur, and the drain current Id flows easily in a region operating at a low gate voltage Vgs. In contrast, in the EXAMPLE, it was confirmed that in a region (region of the linear region near the boundary with the shutout region) operating at a low gate voltage Vgs, the rate of increase of the drain current Id with respect to the gate voltage Vgs is smaller than that in the conventional example. In other words, it was found that compared to the conventional example, in the EXAMPLE, the flow of the drain current Id was impeded in the low gate-voltage operating area. The reason for this is as follows.

[0057] In the present invention, the depth d of the trench 6 is shallow, the channel length L1 is short, and the width w1 between adjacent trenches 6 is narrow whereby parasitic capacitance between the p-type base layer 3 and the n.sup.−-type drift layer 2 decreases. By applying the gate voltage Vgs to the p-type base layer 3 (which has a small parasitic capacitance) from both sides along the second direction y, the electrons and holes recombine, easily returning to an equilibrium state since the charge amount of the n-type inversion layer of the p-type base layer 3 is large. As a result, the p-type base layer 3 may be caused to be completely depleted. Therefore, in the region operating at a low gate voltage Vgs, adverse effects of a voltage Vds between the drain and source are minimal, enabling suppression of the drain current. Therefore, the drain current may be completely controlled by the gate voltage Vgs alone.

[0058] Further, current-voltage characteristics were simulated for both the EXAMPLE and the conventional example and the results are depicted in FIG. 8. FIG. 8 is a characteristics diagram of current-voltage characteristics of the semiconductor device according to the EXAMPLE. In FIG. 8, point E represents the pinch off voltage. From the results depicted in FIG. 8, it was confirmed that in the conventional example, after pinch off, even in a region (saturation region) operating at a high voltage Vds between the drain and source, the drain current Id flows easily and saturation is difficult. In contrast, it was confirmed that in the EXAMPLE, after pinch off, even in a region operating a high voltage Vds between the drain and source, adverse effects of the voltage Vds between the drain and source are minimal, increases of the drain current Id are suppressed, and saturation was possible.

[0059] In the described embodiments, various modifications are possible within a scope not departing from the spirit of the invention. For example, dimensions, impurity concentrations, etc. may be set according to necessary specifications. Further, in the embodiments, as an example, although a case has been described in which on an n.sup.−-type semiconductor layer becoming a drift region, a p-type semiconductor layer and an n.sup.+-type semiconductor layer are formed by epitaxial growth as a base region and a source region, respectively, the p-type base region and the n.sup.+-type source region may be formed by ion implantation in the n.sup.−-type semiconductor layer becoming the drift region. In this case, of the n.sup.−-type semiconductor layer, a portion other than the p-type base region, the n.sup.+-type source region, and the p.sup.+-type contact region become the drift region. Further, a semiconductor substrate including silicon carbide (SiC substrate) may be used as a drift region; and the p-type base region, the n.sup.+-type source region, and the n.sup.+-type drain region may be formed in the SiC substrate by ion implantation. In this case, of the SiC substrate, a portion other than the p-type base region, the n.sup.+-type source region, the p.sup.+-type contact region, and the n.sup.+-type drain region becomes the drift region.

[0060] Further, in the embodiments described, although a MOSFET is described as an example, even with application to a bipolar transistor or IGBT used as a switching device, similar effects are obtained. In the described embodiments, although a case is described in which a (0001) face of a silicon carbide substrate including silicon carbide is regarded as a main surface, without limitation hereto, various modifications such the plane orientation of the substrate main surface, the wide bandgap semiconductor material of the substrate, etc. are possible. For example, a (000-1) face may be set as a substrate main surface; a semiconductor substrate including a wide bandgap semiconductor material such as gallium nitride (GaN) may be used, etc. Further, in the embodiments, although a first conductivity type is set to be an n-type and a second conductivity type is set to be a p-type, the present invention is similarly implemented when the first conductivity type is set to be a p-type and the second conductivity type is set to be an n-type.

[0061] Nonetheless, with the conventional semiconductor device, as described above, in particular, although the channel resistance has to be reduced to reduce the ON resistance, when the channel resistance is reduced, in a low gate-voltage operating area (operating region of a linear region near a boundary with a shutout region), current (drain current) between the drain and source flows easily consequent to short channel effects, making elements difficult to turn OFF. In other words, the threshold voltage varies and becomes lower. In addition, after pinch off, in a region operating a high voltage between the drain and source (saturation region) as well, drain current flows easily, making saturation difficult. In this manner, controlling the drain current by the gate voltage is difficult, arising in a problem of decreased reliability.

[0062] According to the present invention, JFET resistance may be eliminated and channel resistance may be reduced. Further, according to the present invention, since short channel effects may be suppressed, at low gate-voltage operating areas, the flow of current between the first and second electrodes may be impeded. Further, after pinch off, in a region operating at high voltage between the first and second electrodes as well, the flow of current between the first and second electrodes becomes difficult. Therefore, current between the first and second electrodes may be completely controlled by only the gate voltage.

[0063] The semiconductor device according to the present invention achieves an effect in that the ON resistance may be reduced and decreases in reliability may be prevented.

[0064] As described, the semiconductor device according to the present invention is useful for a semiconductor device used as a switching device and is particularly suitable for a vertical MOSFET produced on a silicon carbide semiconductor base.

[0065] Although the invention has been described with respect to a specific embodiment for a complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modifications and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.