LAYERED SOLID STATE ELEMENT COMPRISING A FERROELECTRIC LAYER AND METHOD FOR MANUFACTURING THE SAME

Abstract

A layered solid element includes a ferroelectric layer of a crystalline material Li.sub.1−x(Nb.sub.1−yTa.sub.y).sub.1+xO.sub.3+2x−z which has X- or 33° Y-orientation with respect to a substrate of the layered solid element. The ferroelectric layer is grown epitaxially from a buffer layer having of one of the chemical formulae L.sub.kNi.sub.rO.sub.1.5.Math.(k+r)+w or L.sub.n+1Ni.sub.nO.sub.3n+1+δ, where L is a lanthanide element. Such layered solid element may form a thin-film bulk acoustic resonator and be useful for integrated electronic circuits such as RF-filters, or guided optical devices such as integrated optical modulators.

Claims

1-14. (canceled)

15. A layered solid element comprising a substrate and a layer stack supported by a face of the substrate, the layer stack comprising a buffer layer of a first crystalline material and a ferroelectric layer of a second crystalline material which are in direct contact with one another along an epitaxial interface, the buffer layer being closer to the substrate than the ferroelectric layer, wherein the first crystalline material is based on a first compound with chemical formula L.sub.kNi.sub.rO.sub.1.5.Math.(k+r)+w, where L is a lanthanide element or several lanthanide elements substituted to one another within said first crystalline material, Ni is nickel and O is oxygen, k is a first coefficient comprised between 0.7 and 1.3, r is a second coefficient comprised between 0.7 and 1.3, and w is a third coefficient comprised between −0.5 and +0.5, or the first crystalline material is based on another first compound chemical with formula L.sub.n+1Ni.sub.nO.sub.3n+1+δ, where n is a non-zero integer, and δ is a coefficient comprised between −0.5 and +0.5, and the second crystalline material is based on lithium niobiate, lithium tantalate or a second compound with chemical formula Li.sub.1−x(Nb.sub.1−yTa.sub.y).sub.1+xO.sub.3+2x−z, where Li is lithium, Nb is niobium, Ta is tantalum, x is another first coefficient comprised between 0 and 0.08, y is another second coefficient comprised between 0 and 1, and z is another third coefficient comprised between 0 and +0.5.

16. The layered solid element according to claim 15, wherein the second crystalline material is of ilmenite structure with trigonal structure, and the buffer layer of the first crystalline material is based on L.sub.kNi.sub.rO.sub.1.5.Math.(k+r)+w with trigonal structure, and has a crystallographic plane (0, 1, −1, 2) in hexagonal setting that is parallel to the epitaxial interface, and the second crystalline material within the ferroelectric layer is oriented 33°±5° Y in IEEE convention with respect to said epitaxial interface, or the buffer layer of the first crystalline material is based on L.sub.kNi.sub.rO.sub.1.5.Math.(k+r)+w with trigonal structure and has a crystallographic plane (1, 1, −2, 0) in hexagonal setting that is parallel to the epitaxial interface, and the second crystalline material within the ferroelectric layer has a crystallographic X-axis oriented perpendicular to said epitaxial interface in IEEE convention, or the buffer layer of the first crystalline material is based on L.sub.n+1Ni.sub.nO.sub.3n+1+δ with tetragonal or orthorhombic structure and has a crystallographic plane (0, 0, 1) that is parallel to the epitaxial interface, and the second crystalline material within the ferroelectric layer is oriented 33°±5° Y in IEEE convention with respect to said epitaxial interface, or the buffer layer of the first crystalline material is based on L.sub.n+1Ni.sub.nO.sub.3n+1+δ with tetragonal or orthorhombic structure and has a crystallographic plane (1, 1, 0) that is parallel to the epitaxial interface, and the second crystalline material within the ferroelectric layer has a crystallographic X-axis oriented perpendicular to said epitaxial interface in IEEE convention.

17. The layered solid element according to claim 15, wherein the buffer layer has a first thickness of between 1 nm and 1000 nm, and the ferroelectric layer has a second thickness of between 10 nm to 2000 nm, said first and second thicknesses being measured perpendicular to the epitaxial interface.

18. The layered solid element according to claim 15, wherein the substrate is a silicon-based substrate or a substrate designed for an integrated optical or acoustical device.

19. The layered solid element according to claim 15, wherein the layer stack further comprises at least one among a silica layer, a titanium layer, a titania layer, a tantalum layer, a tantalum oxide layer, a chromium layer, a chromium oxide layer, an electrode layer, a sacrificial layer adapted to be selectively etched and a Bragg mirror, between the substrate and the buffer layer.

20. The layered solid element according to claim 15, wherein a cavity is located between a first part of said layered solid element which comprises the substrate, and a second part of said layered solid element which comprises the buffer layer and the ferroelectric layer.

21. The layered solid element according to claim 15, wherein the ferroelectric layer is located between two electrode layers within the layer stack, along a direction perpendicular to the layers, so that the layered solid element is adapted to implement bulk acoustic waves or optical variations that are generated within said ferroelectric layer by a time-varying voltage applied between said electrode layers.

22. The layered solid element according to claim 15, forming part of an integrated electronic circuit, an integrated acoustic device, an integrated guided photonic device or a pyroelectric device.

23. A method for manufacturing a layered solid element that is in accordance with claim 15, wherein the second crystalline material is grown epitaxially from the buffer layer of said first crystalline material or said another first crystalline material, for forming the ferroelectric layer.

24. The method according to claim 23, wherein the first crystalline material is deposited using a RF-sputtering deposition process or a chemical vapour deposition process, for forming the buffer layer.

25. The method according to claim 23, wherein the second crystalline material is deposited using a chemical vapour deposition process, for forming the ferroelectric layer.

26. The method according to claim 25, wherein the chemical vapour deposition process is a direct-liquid-injection chemical vapour deposition process or a pulsed-injection chemical vapour deposition process.

27. The method according to claim 23, further comprising applying an electrical field to the second crystalline material when said second crystalline material is being deposited for forming the ferroelectric layer, or after said second crystalline material has been deposited, the electrical field being suitable for aligning ferroelectric orientations existing in domains within the ferroelectric layer.

28. An integrated circuit, comprising a layered solid element that is in accordance with claim 15, said integrated circuit forming at least part of an electronic device, at least part of an acoustic device, in particular of a microacoustic device, at least part of an electro-optic device, at least part of a pyroelectric device, or at least part of a guided photonic device.

29. The integrated circuit according to claim 28, forming a RF-filter, a waveguide or an optical modulator.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0038] FIG. 1 is a cross-section of a layered solid element in accordance with the present invention;

[0039] FIG. 2 represents schematically a material deposition assembly which may be used for depositing the ferroelectric layer of the layered solid element of FIG. 1;

[0040] FIGS. 3a and 3b are cross-sectional views of two layered solid elements according to the invention and having SMR and TFBAR structures, respectively; and

[0041] FIG. 4 shows crystalline structures of compounds that can be used for the buffer layer in a layered solid element according to the invention.

[0042] For clarity sake, element sizes which appear in these figures do not correspond to actual dimensions or dimension ratios. Also, same reference numbers which are indicated in these figures denote identical elements of elements with identical function.

DETAILED DESCRIPTION OF THE INVENTION

[0043] With reference to FIG. 1, a layered solid element 100 comprises a substrate 10 which has an upper face S, and a layer stack which is arranged on this upper face S.

[0044] Therefore, a stacking direction D of the layer stack is perpendicular to the upper substrate face S. For example, the substrate 10 may be a portion of a (100)-single-crystal silicon wafer.

[0045] The layer stack comprises a buffer layer 1 and a ferroelectric layer 2 which are in direct contact with one another along an intermediate epitaxial interface ES. The orientation of layer 2 is defined by the orientation of layer 1. Both layers 1 and 2 are crystalline with crystal structure of R-3c and R3c space group, respectively. Layer 1 may be a Ruddlesden-Popper phase with tetragonal or orthorhombic structure. The epitaxial interface ES is perpendicular to the stacking direction D, and parallel to the upper substrate face S. For example, the buffer layer 1 may be 15 nm thick, and the ferroelectric layer 2 may be 250 nm thick, these thicknesses being measured parallel to the stacking direction D. The buffer layer 1 may be of crystalline lanthanum nickelate, with chemical formula LaNiO.sub.3, and the ferroelectric layer 2 may be of lithium niobiate, with chemical formula LiNbO.sub.3, or lithium tantalate, with chemical formula LiTaO.sub.3. But the Li-content of the ferroelectric layer 2 may vary in some extent, and also the material of the ferroelectric layer 2 may be LiNbO.sub.3 with some of the niobium cations replaced by tantalum cations without disturbing the crystal structure. The oxygen amount in the buffer layer 1 and ferroelectric layer 2 may also vary in some extent.

[0046] The layer stack may further comprise a lower stack part 11 which is situated between the upper substrate face S and the buffer layer 1, and also an upper stack part 12 situated on a side of the ferroelectric layer 2 opposite the substrate 10.

[0047] A first layer 3 of the lower stack part 11 may be a silica (SiO.sub.2) layer, for example formed by thermal oxidation of the substrate 10 when in silicon. The lower stack part 11 may further comprise a number of individual layers, including for example a bottom electrode layer 4, for example of platinum-, iridium- or ruthenium-based material, oxide layers such as ruthenia (RuO.sub.2) or cerium oxide (CeO.sub.2), indium tin oxide (ITO), and also possibly a layer subset 5 which is suitable for forming an acoustic Bragg mirror or optical Bragg mirror. In a known manner, such Bragg mirror is designed for reflecting bulk acoustic waves or optical waves produced within the ferroelectric layer 2. Possibly, the lower stack part 11 may also comprise a sacrificial layer, which is intended to be etched later in the manufacturing process to form a thin film bulk acoustic resonator, commonly denoted as TFBAR. Such structures that are compatible with the invention layered solid element will be described further below, in particular with reference to [FIG. 3a] and [FIG. 3b]. The lower stack part 11 may additionally comprise one or several adhesion layers, which may be based on chromium, chromium oxide, titanium, titanium oxide, tantalum, tantalum oxides, metal alloys, etc. Implementation of such adhesion layers is well-known in the art, so that it is useless to describe them further here. In FIG. 1, two adhesion layers 6a and 6b are represented on each side of the bottom electrode layer 4, but usually only layer 6a is sufficient. Layer 6b may be used to prevent diffusion from the buffer layer 1 or ferroelectric layer 2, in particular diffusion of lithium oxide, to the electrode layer 4 or to in general to the layer subset 5.

[0048] The upper stack part 12 may also comprise one or several individual layers, including a top electrode layer 7, other adhesion layers 8a and 8b, and a protection layer or temperature compensation layer 9. The top electrode 7 may be of the same material as that of the bottom electrode layer 4, or of aluminium-, tungsten-, molybdenum- or gold-based materials, or be based on other metals. The layer 9 may be of silicon oxide, aluminium oxide or some other dielectric material, for example.

[0049] Layers other than the buffer layer 1 and the ferroelectric layer 2 are not described further since they do not relate directly to the invention. The actual composition of the layered solid element 100 may differ from that recited just above depending on its application. In particular, for applications other than RF-filters and optical modulators, such as energy harvesting, electrically conducting oxides, including doped oxides, may be used as electrode layer materials.

[0050] The layered solid element 100 may be part of an integrated circuit, such as an integrated electronic device, part of an integrated acoustic device, or part of an integrated guided photonic device. For an integrated electronic device, the substrate 10 may incorporate or support electrical components and connections in a well-known manner, and the layered solid element 100 with the arrangement as represented in [FIG. 1] may constitute a solidly mounted resonator, commonly denoted SMR. Alternatively, for an integrated guided photonic device, the substrate 10 incorporates or supports waveguide segments (not represented) that are arranged in a suitable manner for injecting radiation into the ferroelectric layer 2 and collecting radiation exiting therefrom. For example, for such optical application, the layered solid element 100 may constitute an optical modulator.

[0051] Turning now to FIG. 2, a CVD-reactor suitable for depositing at least the ferroelectric layer 2, or the succession of the buffer layer 1 and the ferroelectric layer 2, is described. This CVD-reactor is of the type commonly known as DLI-CVD, for Direct Liquid Injection Chemical Vapour Deposition, but other types may be used alternately, such as PI-CVD for Pulsed Injection Chemical Vapour Deposition, for example. The DLI-CVD reactor comprises a low-pressure temperature-controlled vessel 20, which may be comprised of two chambers 20a and 20b with a gas passage 20c therebetween. The chamber 20a is designed for vaporizing chemical precursors, and the chamber 20b is designed for making these precursors to react chemically on the substrate 10 in order to form the desired layer. Two double-injectors 21a and 21b may be provided to feed the chamber 20a with the following respective mixtures when the ferroelectric layer 2 is to be deposited: a liquid organic solution which contains a first metal-organic compound as a lithium (Li) precursor with a gaseous mixture of oxygen (O.sub.2), nitrogen (N.sub.2) or argon (Ar) for the injector 21a, and another liquid organic solution which contains another metal-organic compound as a niobium (Nb) or tantalum (Ta) precursor for the injector 21b with the same gaseous mixture as for the injector 21a. A single injector may be used alternatively in the case of a liquid organic solution which contains a mixture of all the metal-organic compounds forming the lithium- (Li), niobium- (Nb) or tantalum- (Ta) precursors with a gaseous mixture of oxygen (O.sub.2), nitrogen (N.sub.2) or argon (Ar). Reference 23a denotes a sealed tank which contains the Li-precursor, for example (2,2,6,6-tetramethyl-3,5-heptandione)Li dissolved in 3,3,5-trimethyl benzene, also called mesitylene, and N,N,N′,N′-tetramethylethylenediamine (TMEDA) and pressurized with argon or nitrogen through pipe 24. The double injector 21a is connected to the tank 23a through the pipe 25a and supplied with the oxygen-nitrogen-argon mixture through the pipe 26a. Similarly, Reference 23b denotes another sealed tank which contains the Nb- or Ta-precursor, for example (2,2,6,6-tetramethyl-3,5-heptandione).sub.4Nb or (2,2,6,6-tetramethyl-3,5-heptandione).sub.4Ta also dissolved in mesitylene and TMEDA. Then, the double injector 21b is connected to the Ar-pressurized tank 23b through the pipe 25b and supplied with the oxygen-nitrogen-argon mixture through the pipe 26b. Suitable heating modules (not represented) are incorporated in the walls of the chambers 20a and 20b and inside the substrate support 22 for producing desired temperature values, and an exhaust 27 of the chamber 20b is connected to a pumping device (not represented).

[0052] The chamber 20b encloses a substrate support 22 on which the substrate 10 is to be fixed. The support 22 may be optionally provided with a spinning mechanism, for producing deposited layers with improved thickness uniformity across a large useful deposition area. In particular, it is possible in this way to process large area substrates which are intended to be cut into separate integrated circuits later on.

[0053] According to first embodiments of the invention, the substrate 10 is already provided with the lower stack part 11 if any and the buffer layer 1, before being CVD-processed. The buffer layer 1, of crystalline LaNiO.sub.3, may have been deposited using the well-known RF-sputtering process, leading to crystal orientation with crystallographic R-planes (0, 1, −1, 2) in hexagonal setting which are parallel to the upper substrate face S, also called 36° Y crystal orientation in IEEE convention. Suitable sputtering conditions for deposition of such buffer layer 1 may be: LaNiO.sub.3 as sintered target material, deposition temperature between 350° C. (degree Celsius) and 600° C., target power between 50 W (watt) and 200 W, chamber pressure between 3.Math.10.sup.−3 Torr and 6.Math.10.sup.−3 Torr, and oxygen/argon ratio between less than 50%. Using La.sub.n+1Ni.sub.nO.sub.3n+1+δ target, the same deposition conditions will allow the growth of La.sub.n+1Ni.sub.nO.sub.3n+1+δ layers with crystallographic plane (0, 0, 1) parallel to the upper substrate face S.

[0054] For these first embodiments, the ferroelectric layer 2 may be deposited directly on the buffer layer 1 using the DLI-CVD reactor of FIG. 2 with the following deposition parameters: temperature inside the vaporization chamber 20a between 250° C. and 270° C., temperature inside the deposition chamber 20b between 600° C. and 700° C., pressure inside the deposition chamber 20b between 2 Torr and 10 Torr, and ratio O.sub.2/(O.sub.2+N.sub.2+Ar) between 30% and 50%. These deposition parameters produce a growth rate for the ferroelectric layer 2 of between 0.5 nm/min (nanometer per minute) and 2 nm/min parallel to the stacking direction D. The LiNbO.sub.3 material thus deposited for forming the ferroelectric layer 2 is crystalline, with 33° Y orientation induced through epitaxy by the 36° Y-orientation of the LaNiO.sub.3 material in the buffer layer 1.

[0055] If tantalum is to used instead of niobium partly or totally in the ferroelectric layer 2, the niobium precursor should be combined with or replaced by the tantalum precursor when supplying the CVD-vessel with the chemical compounds. Such adaptation can be carried out easily by the Man skilled in material deposition, since the deposition parameters provided above for the LiNbO.sub.3 composition also suit for the LiTaO.sub.3 composition.

[0056] According to second embodiments of the invention, both the buffer layer 1 and the ferroelectric layer 2 may deposited successively using DLI-CVD reactors as shown in FIG. 2. The following deposition conditions may be used for the LaNiO.sub.3 material of the buffer layer 1 in the CVD reactor which is dedicated to this layer: (2,2,6,6-tetramethyl-3,5-heptandione).sub.3La dissolved mesitylene-TMEDA as lanthanum precursor in the tank 21a, (2,2,6,6-tetramethyl-3,5-heptandione).sub.2Ni dissolved in mesitylene-TMEDA as nickel precursor in the tank 21b, temperature inside the vaporization chamber 20a between 185° C. and 215° C., temperature inside the deposition chamber 20b between 650° C. and 775° C., gas mixture of oxygen, nitrogen and argon with ratio O.sub.2/(O.sub.2+N.sub.2+Ar) between 30% and 50%, and pressure inside the deposition chamber 20b between 2 Torr and 10 Torr. Adjusting La and Ni precursor ratio in the solution at the same deposition conditions will enable the growth of La.sub.n+1Ni.sub.nO.sub.3n+1+δ layers with crystallographic plane (1, 1, 0) parallel to the upper substrate face S. These deposition conditions produce a growth rate for the buffer layer 1 of between 0.5 nm/min and 1 nm/min. The LaNiO.sub.3 material thus deposited for forming the buffer layer 1 is crystalline, with X-orientation and La.sub.n+1Ni.sub.nO.sub.3n+1+δ layers with (1, 1, 0) orientation. This means that the X-axis of the crystal structure of LaNiO.sub.3 is perpendicular to the substrate face S.

[0057] For such second embodiments, the ferroelectric layer 2 is CVD-deposited directly on the buffer layer 1 thus obtained. The CVD-deposition parameters listed above for the LiNbO.sub.3 material in the first embodiments may be used again for the second embodiments. But now, due the X-orientation of the LaNiO.sub.3 material of the buffer layer 1, the LiNbO.sub.3 material of the ferroelectric layer 2 is obtained through epitaxy with crystal orientation X, meaning that the X-axis of the crystal structure of LiNbO.sub.3 is perpendicular to the epitaxy interface ES, and also that the (2, −1, −1, 0) A-planes of LiNbO.sub.3 are parallel to the epitaxial interface ES.

[0058] Alternatively, the LaNiO.sub.3 material deposited for forming the buffer layer 1 may be crystalline with 36° Y-orientation if the substrate 10 or lower stack part 11 imposes epitaxial growth of (0, 1, −1, 2) planes of LaNiO.sub.3 parallel to the epitaxial interface.

[0059] Also possibly, the LaNiO.sub.3 material deposited for forming the buffer layer 1 may be crystalline with X-orientation if the substrate 10 or lower stack part 11 imposes epitaxial growth of (2, −1, −1, 0) planes of LaNiO.sub.3 parallel to the epitaxial interface.

[0060] When the L.sub.n+1Ni.sub.nO.sub.3n+1+δ material is deposited for forming the buffer layer 1, it may be crystalline with (0, 0, 1)-orientation if the substrate 10 or lower stack part 11 imposes epitaxial growth of (0, 0, 1) planes of L.sub.n+1Ni.sub.nO.sub.3n+1+δ parallel to the epitaxial interface. The L.sub.n+1Ni.sub.nO.sub.3n+1+δ material deposited for forming the buffer layer 1 may also be crystalline with (1, 1, 0)-orientation if the substrate 10 or lower stack part 11 imposes epitaxial growth of these planes of L.sub.n+1Ni.sub.nO.sub.3n+1+δ parallel to the epitaxial interface.

[0061] The ferroelectric layers 2 that have been obtained in such first and second embodiments exhibit large piezoelectric and electro-optic efficiencies due to their 33° Y-orientation or X-orientation. Thanks to such piezoelectric and electro-optic efficiencies, the integrated devices that incorporate the layered solid element 100 allows improved operation and/or larger frequency operation band, whatever the application of this device, in particular RF-filtering and optical modulation.

[0062] For all embodiments of the invention, an electrical poling step may be necessary for aligning varying polarisations which may exist in domains within the ferroelectric layer 2 as-deposited. Such poling may be achieved by applying an electrical field to the layer 2, which is higher that a coercive electrical field. Such electrical field may be applied to the ferroelectric layer 2 during deposition of this latter, so that the as-deposited ferroelectric material has one single polarization throughout the whole layer 2. Alternatively, the electrical poling may be carried out after the ferroelectric layer 2 or the whole layered solid element 100 has been completed. For implementing such poling, one or both of the electrode layers 4 and 7 may be used for electrical connection to an external voltage source. For example, when the coercive electrical field of the ferroelectric material of layer 2 equals 85 kV/cm (kilovolt per centimetre), the poling electrical field to be used may be more than 85 kV/cm.

[0063] The invention layered solid element 100 may be combined with various element structures including high overtone bulk acoustic resonator, or HBAR, bulk acoustic wave solid mounted resonator, or SMR, or thin film bulk acoustic resonator of free-standing type, denoted TFBAR.

[0064] For the HBAR structure, the lower stack part 11 is devoid of acoustic Bragg mirror 5, so that the substrate 10 forms the propagation medium of the acoustic waves.

[0065] For the SMR structure as shown in [FIG. 3a], the lower stack part 11 includes the acoustic Bragg mirror 5, so that the propagation medium of the acoustic waves is limited to the stack part that is located above the Bragg mirror 5, opposite the substrate 10. This propagation medium is thus formed by the lower electrode 4, the buffer layer 1, the ferroelectric layer 2 and the upper electrode 7, and it is isolated from the substrate 10 by the acoustic Bragg mirror 5. [FIG. 3a] also shows electrode connections 4e and 7e that are intended to be connected to an electrical signal source, such as a RF source.

[0066] For the TFBAR structure as shown in [FIG. 3b], the lower stack part 11 includes initially a layer of sacrificial material. This sacrificial material is then etched through an aperture O, after the lower electrode 4, the buffer layer 1, the ferroelectric layer 2 and the upper electrode 7 have been deposited. Reference number 10′ denotes a surrounding material portion that may be of silica. Dry or wet etching processes may be implemented for withdrawing the sacrificial material selectively with respect to the other materials. A cavity 13 is thus created between the lower electrode 4 and the substrate 10. The acoustic propagation medium is formed again by the lower electrode 4, the buffer layer 1, the ferroelectric layer 2 and the upper electrode 7, but it is isolated from the substrate 10 by the cavity 13 instead of the acoustic Bragg mirror 5.

[0067] When the invention layered solid element 100 is intended to form a guided photonic device, it may be either devoid of layer subset 5, or the layer subset 5 may be an optical Bragg mirror.

[0068] The buffer layer 1 may have one of the chemical compositions L.sub.kNi.sub.rO.sub.1.5.Math.(k+r)+w, where L is the lanthanide element or several lanthanide elements substituted to one another, 0.7≤k≤1.3, 0.7≤r≤1.3 and −0.5≤w≤+0.5. But it may alternatively have one of the other chemical compositions L.sub.n+1Ni.sub.nO.sub.3n+1+δ, where n is a non-zero integer, and −0.5≤δ≤+0.5. For n=1, the compound is La.sub.2NiO.sub.4 with K.sub.2NiF.sub.4 structure, and for n very large, it is close to LaNiO.sub.3 with perovskite structure. Such other compositions are known as Ruddlesden-Popper phases and the L.sub.2NiO.sub.4 crystal structure can be derived by alternating along [001] crystallographic direction of LNiO.sub.3 perovskite blocks and LaO layers rotated by 45° in the basal plane of tetragonal cell. [FIG. 4] illustrates such derivation of the La.sub.n+1Ni.sub.nO.sub.3n+1+δ compositions from La.sub.2NiO.sub.4. In each one of the compositions L.sub.kNi.sub.rO.sub.1.5.Math.(k+r)+w and L.sub.n+1Ni.sub.nO.sub.3n+1+δ, L may indicate a mixture of several lanthanide elements provided that the compositions thus obtained for the buffer layer can be deposited in crystal forms which allow subsequent deposition of the ferroelectric material with X- or ≈33° Y-orientation through epitaxy from the buffer layer.

[0069] It is also reminded that the ferroelectric material may be varied in chemical composition in a great extent while maintaining both its ferroelectric efficiency and its epitaxial growth capability from the buffer layer. For this reason, a general composition of the ferroelectric layer 2 which is implemented according to the invention can be expressed as Li.sub.1−x(Nb.sub.1−yTa.sub.y).sub.1+xO.sub.3+2x−z, with 0≤x≤0.08, 0≤y≤1 and 0≤z≤0.5.

[0070] Finally, all details in the design of the CVD-reactor which have been provided as well as all cited numeral values are for exemplifying purpose only, and may be adapted depending on the reactor actually used, the exact chemical compositions implemented and the desired growth rates and layer thicknesses.